DE19983026B4 - Brücke zwischen zwei Bussen mit einem Puffer mit einer einstellbaren Mindestspeicherraummenge für ein Akzeptieren einer Schreibanforderung und Verfahren hierzu - Google Patents

Brücke zwischen zwei Bussen mit einem Puffer mit einer einstellbaren Mindestspeicherraummenge für ein Akzeptieren einer Schreibanforderung und Verfahren hierzu Download PDF

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Publication number
DE19983026B4
DE19983026B4 DE19983026T DE19983026T DE19983026B4 DE 19983026 B4 DE19983026 B4 DE 19983026B4 DE 19983026 T DE19983026 T DE 19983026T DE 19983026 T DE19983026 T DE 19983026T DE 19983026 B4 DE19983026 B4 DE 19983026B4
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Germany
Prior art keywords
bridge
bus
data
buffer
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19983026T
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German (de)
English (en)
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DE19983026T1 (de
Inventor
Barry R. Portland Davis
Nick G. Chandler Eskandari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19983026T1 publication Critical patent/DE19983026T1/de
Application granted granted Critical
Publication of DE19983026B4 publication Critical patent/DE19983026B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
DE19983026T 1998-03-04 1999-02-26 Brücke zwischen zwei Bussen mit einem Puffer mit einer einstellbaren Mindestspeicherraummenge für ein Akzeptieren einer Schreibanforderung und Verfahren hierzu Expired - Fee Related DE19983026B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/034,624 1998-03-04
US09/034,624 US6298407B1 (en) 1998-03-04 1998-03-04 Trigger points for performance optimization in bus-to-bus bridges
PCT/US1999/004234 WO1999045470A2 (en) 1998-03-04 1999-02-26 Trigger points for performance optimization in bridges

Publications (2)

Publication Number Publication Date
DE19983026T1 DE19983026T1 (de) 2001-02-22
DE19983026B4 true DE19983026B4 (de) 2010-12-23

Family

ID=21877567

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19983026T Expired - Fee Related DE19983026B4 (de) 1998-03-04 1999-02-26 Brücke zwischen zwei Bussen mit einem Puffer mit einer einstellbaren Mindestspeicherraummenge für ein Akzeptieren einer Schreibanforderung und Verfahren hierzu

Country Status (6)

Country Link
US (1) US6298407B1 (enExample)
JP (1) JP2002506250A (enExample)
KR (1) KR20010041519A (enExample)
AU (1) AU2793599A (enExample)
DE (1) DE19983026B4 (enExample)
WO (1) WO1999045470A2 (enExample)

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US20040003164A1 (en) * 2002-06-27 2004-01-01 Patrick Boily PCI bridge and data transfer methods
US7103701B2 (en) * 2002-09-23 2006-09-05 Hewlett-Packard Development Company, L.P. Memory bus interface
US6950905B2 (en) * 2003-02-20 2005-09-27 Sun Microsystems, Inc. Write posting memory interface with block-based read-ahead mechanism
WO2004081803A1 (en) * 2003-03-12 2004-09-23 Koninklijke Philips Electronics N. V. Data processing device and method for transferring data
US8386648B1 (en) * 2003-06-26 2013-02-26 Nvidia Corporation Hardware support system for accelerated disk I/O
US8683132B1 (en) 2003-09-29 2014-03-25 Nvidia Corporation Memory controller for sequentially prefetching data for a processor of a computer system
US8356142B1 (en) 2003-11-12 2013-01-15 Nvidia Corporation Memory controller for non-sequentially prefetching data for a processor of a computer system
US8700808B2 (en) * 2003-12-01 2014-04-15 Nvidia Corporation Hardware support system for accelerated disk I/O
US7213094B2 (en) * 2004-02-17 2007-05-01 Intel Corporation Method and apparatus for managing buffers in PCI bridges
US8356143B1 (en) 2004-10-22 2013-01-15 NVIDIA Corporatin Prefetch mechanism for bus master memory access
US7593345B2 (en) * 2004-12-30 2009-09-22 Finisar Corporation Altering latency for network testing
US7487274B2 (en) * 2005-08-01 2009-02-03 Asic Architect, Inc. Method and apparatus for generating unique identification numbers for PCI express transactions with substantially increased performance
US7698493B2 (en) * 2005-08-31 2010-04-13 Ati Technologies, Inc. Methods and apparatus for translating write request messages in a computing system
JP4362135B2 (ja) * 2007-02-13 2009-11-11 富士通株式会社 データ転送装置およびデータ転送方法
WO2009028494A1 (ja) 2007-08-28 2009-03-05 Nikon Corporation 位置検出装置、位置検出方法、露光装置、およびデバイス製造方法
JP5112138B2 (ja) * 2008-03-28 2013-01-09 株式会社日立製作所 セッション管理方法、ストレージ装置、及び、計算機システム
US8356128B2 (en) * 2008-09-16 2013-01-15 Nvidia Corporation Method and system of reducing latencies associated with resource allocation by using multiple arbiters
US8370552B2 (en) * 2008-10-14 2013-02-05 Nvidia Corporation Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions
US8698823B2 (en) 2009-04-08 2014-04-15 Nvidia Corporation System and method for deadlock-free pipelining
JP2011182314A (ja) * 2010-03-03 2011-09-15 Oki Semiconductor Co Ltd データ中継装置及び方法
US8566496B2 (en) * 2010-12-03 2013-10-22 Lsi Corporation Data prefetch in SAS expanders
US8677031B2 (en) 2011-03-31 2014-03-18 Intel Corporation Facilitating, at least in part, by circuitry, accessing of at least one controller command interface
JP5564019B2 (ja) * 2011-08-26 2014-07-30 株式会社東芝 ファイル転送装置およびその方法
US10425456B2 (en) 2017-11-29 2019-09-24 Bank Of America Corporation Request processing system using a splitting engine
US10419265B2 (en) 2017-11-29 2019-09-17 Bank Of America Corporation Request processing system using a combining engine
US11226910B2 (en) * 2019-03-04 2022-01-18 Qualcomm Incorporated Ticket based request flow control

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DE69022872T2 (de) * 1989-04-21 1996-06-13 Ibm Bus-zu-Bus-Umsetzer.
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system

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JP3132509B2 (ja) * 1990-07-06 2001-02-05 富士通株式会社 データ受信処理装置
JP2798107B2 (ja) * 1992-04-15 1998-09-17 日本電気株式会社 データ転送方法
US5941964A (en) * 1992-05-21 1999-08-24 Intel Corporation Bridge buffer management by bridge interception of synchronization events
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JP3519182B2 (ja) * 1995-09-05 2004-04-12 株式会社日立製作所 情報処理システムおよびバスアービタならびにバス制御方法
US5828865A (en) * 1995-12-27 1998-10-27 Intel Corporation Dual mode bus bridge for interfacing a host bus and a personal computer interface bus
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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
DE69022872T2 (de) * 1989-04-21 1996-06-13 Ibm Bus-zu-Bus-Umsetzer.
US5546546A (en) * 1994-05-20 1996-08-13 Intel Corporation Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system

Also Published As

Publication number Publication date
WO1999045470A2 (en) 1999-09-10
AU2793599A (en) 1999-09-20
WO1999045470A3 (en) 2000-03-02
DE19983026T1 (de) 2001-02-22
JP2002506250A (ja) 2002-02-26
KR20010041519A (ko) 2001-05-25
US6298407B1 (en) 2001-10-02

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8125 Change of the main classification

Ipc: G06F 1340

8364 No opposition during term of opposition
R020 Patent grant now final

Effective date: 20110323

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20130903