KR20010038866A - Device for interface control of Peripheral Processor - Google Patents

Abstract

PURPOSE: An interface control apparatus in a peripheral processor is provided to efficiently use peripheral processor ports, regardless of a duplication method based on a random port allocation method and the type of a hardware unit, by assigning ports according to priority so as to seize hardware units randomly and making each port control a different hardware unit. CONSTITUTION: A peripheral processor backboard(30) is comprised of a common bus interface part(33) and a TD-bus selection part(34). The common bus interface part(33) loads TD-buses sequentially between hardware units(41-44) so as to randomly control each of the hardware units(41-44) corresponding to each of the ports(31A,32A) of peripheral processors. The TD-bus selection part(34) selects a TD-bus so that each port(31A,32A) can control each different hardware unit(41-44) through the common bus interface part(33).

Description

Sub-processor interface control device {Device for interface control of Peripheral Processor}

The interface control apparatus of the lower processor according to the present invention relates to the interface control apparatus of the lower processor, in particular, to randomly occupy the interface of the hardware unit managed by the lower processor.

A subprocessor (PP) of a general high-capacity switching system is a unit included in the access switching subsystem (ASS) of the TDX-10A. Since it requires high reliability in terms of function, it is composed of load sharing or redundancy, It is in charge of memory function to store program and operation processing function to execute it.

In addition, IPC (Inter-Processor Communication) function for communication with other lower processors, serial communication function with hardware unit (H / W device), and alarm sending function for detecting faults in the unit and informing the main processor It is configured to have.

In addition, the hardware configuration in the system includes the PIHA-N (H / W name) board of the Peripheral Processor Interface Hardware Assembly (PIHA-N) board with the global bus function, the Peripheral Processor Interface Compact Backboard (PCBB), and the Peripheral Processor (PPBB-N). It consists of a white board such as BcakBoard -Newtype).

The interface control apparatus of the conventional lower processor is as follows.

FIG. 1 is a schematic block diagram showing a structure of a lower processor, and FIG. 2 is a block diagram of an interface control apparatus of the lower processor.

Referring to Figure 1, the PIHA-N A board (1) and PIHA-N B board (2) is redundant and the sub-processor (PP) (1, 2) for operating or managing the subscriber and the trunk line, various test equipment, A plurality of hardware units (AH / W 0,1) (BH / W 0,1) (21 to 24) connected to the lower processor (1, 2) and the TD-Telephone (Telephony Data Bus) (3) (4). It is composed of

In addition, the lower processor (1) (2) is connected to the TD-bus (3) (4) having a certain port to the TD-bus interface control logic (PPTDI) for interfacing with a plurality of hardware units (21 ~ 24); PP Telephony Bus Interface) 11, 12 is configured.

Referring to FIG. 2, ports A, B, C, and D port (1A, 1B) 2A of the redundant subprocessors PIHA 0A, 0B (PIHA 1A, 1B) configured in the subprocessor backboard 10 (2A). 2B and a plurality of hardware units 21, 22, 23, and 24 are connected to any one of the ports 1A, 1B, 2A, and 2B in a TD bus. .

Referring to the interface control apparatus of the conventional lower processor is configured as follows.

First, referring to Figure 1, the subprocessor (1,2) is a board PIHA-N is duplexed to the A, B side (1) (2), depending on the application and control and timing switch of the subscriber and repeater hardware unit and It performs tasks requiring real-time processing to operate or manage various signal test equipment.

To this end, each of the subprocessors (1) (2) has a TD-bus interface control logic (11) (12) via a plurality of hardware units (21-24) through the TD-bus (Telephony Data Bus) (3) (4). ) Are connected directly to each.

In addition, the TD-bus interface control logic (11) (12) has four ports per PIHA-N and eight ports in consideration of redundancy, each of which is required for each subprocessor (1) (2). The hardware units 21 to 24 are connected to the TD buses 3 and 4 to interface.

Here, the TD bus (3) (4) is connected to the actual bus (3) and PIHA-N B board connected to the processor located in the PIHA-N A board (1) in the redundant subprocessor (1,2) It consists of an actual bus 4 which is connected to a located processor.

Accordingly, the PIHA-N A board 1 can access each hardware unit 21 to 25 only through the TD bus 3 and the PIHA-N B board 2 only through the TD bus 4.

Meanwhile, as shown in FIG. 2, the TD bus connection between the hardware units 21 to 24 and the lower processor is located at the corresponding port of the lower processor back board 10 and the hardware units 21 to 24 to be controlled. It is connected by a 1: 1 TD-bus cable between the backlines.

That is, each port 1A, 1B (2A, 2B) provided in the subprocessor backboard 10 is duplicated by the boards PIHA 0A and PIHA 0B (PIHA 1A and PIHA 1B), so that the hardware units 21 to 24 are provided. 1 to 1 by TD bus.

The A and B ports provided in the ports 1A and 1B interface with the hardware units 21 and 22 connected 1: 1 through a TD bus, and the A and B ports are provided in the ports 2A and 2B. The B port enables one-to-one interface with the hardware units 23 and 24 via the TD bus.

That is, since the lower processor boards are duplicated around the hardware units 21 to 24 by the TD-bus, the board-based duplexing method is used.

Since the port allocation method of the subprocessors (1) and (2) is a fixed port allocation method, the interface of the plurality of hardware units (21 to 24) is determined by the application program executed in each of the subprocessors (1) and (2). do.

For example, to control the subscribers and trunk line hardware units most frequently used in switching systems, two PIHA-N boards are needed to serve the subscribers per subsystem and two PINA-N boards are used to serve the trunk lines. .

At this time, since one PINA-N board has 4 ports (A, B, C, D) and needs 2 PIHA-N boards for redundancy, it has 8 ports for hardware unit such as subscriber and relay line. To control.

However, if the system configuration is less than 2048 subscribers for subscribers and less than 16E1 for relay lines, each subprocessor (1,2) uses only one of four ports, port A, and the remaining three ports (B, C). , D) wastes unused resources. In other words, if you consider redundancy, only one of the eight ports is used.

In addition, when the hardware interface structure through the TD-buses of the subprocessors 1 and 2 is not full mounted, the TD- accessing the corresponding hardware units 21 to 24 of each subprocessor 1 and 2 is performed. The problem is that the port resources of the bus are wasted.

In addition, if a port of a subprocessor operating in redundancy is defective, it cannot be occupied by another port, which may cause a problem in system operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problem, and assigns ports according to priorities so as to randomly occupy a hardware unit interface managed by each subprocessor, thereby controlling each hardware unit having different ports. By improving the structure of the TD-bus cable directly connected to the corresponding port of the back board by fixed allocation method when accessing or controlling the hardware units in the existing subprocessor, the random port redundancy according to the random port allocation method is possible. The goal is to enable efficient use of subprocessor ports regardless of the type and type of hardware unit.

1 is a block diagram showing the interface structure of the lower processor of the conventional exchange system.

Figure 2 is a block diagram of an interface control device of a conventional lower processor.

Figure 3 is a block diagram showing the interface structure of the lower processor of the switching system according to the present invention.

4 is a block diagram of an interface control device of a lower processor according to the present invention;

<Explanation of symbols for the main parts of the drawings>

1,2,31,32 ... subprocessor 11,12,311,312 ... TD-bus interface control logic

21 ... 24,41 ... 44 Hardware Unit 10,30 Subprocessor Backboard

1A, 1B, 2A, 2B, 31A, 32A, 31AB ... Port 33 ... Common bus interface

34 ... TD bus selection

The interface control apparatus of the lower processor according to the present invention for achieving the above object,

A common bus interface means for sequentially installing a TD bus between each hardware unit and the back board so that the corresponding hardware units can be randomly controlled for each port of the lower processor, and each port of the lower processor is connected through the common bus interface means. TD-bus selecting means for selecting a TD-bus to control different hardware units.

Here, the TD-bus selecting means is characterized by assigning ports according to priority in a random port allocation scheme so that each port of the lower processor can control different hardware units.

Hereinafter, with reference to the accompanying drawings as follows. 3 is a schematic configuration diagram showing a structure of a lower processor, and FIG. 4 is a configuration diagram of an interface controller of the lower processor.

Sequentially between each hardware unit 41 to 44 and the back board 30 so that the corresponding hardware units 41 to 44 can be randomly controlled by the respective ports 31A and 32A of the lower processors 31 and 32. The common bus interface unit 33 for mounting the TD bus and the hardware units 41 to 44 in which the ports 31A and 32A of the lower processors 31 and 32 are different from each other through the common bus interface unit 33 are provided. It characterized in that it comprises a TD-bus selector 34 for selecting the TD-bus to control.

Reference numeral 31 is PIHA-N A board, 32 is PIHA-N B board 311, 312 is TD-bus interface control logic (PPTDI), 31AB is SPARE PORT.

Hereinafter, with reference to the accompanying drawings as follows.

First, the common bus interface unit 33 implemented on the back boards 30 of the lower processors 31 and 32 is provided to each hardware unit AH / W 0,1 (BH / W 0,1) 41 to 44. The cables of the connected TD buses are sequentially mounted.

The TD bus selector 34 is located between the common bus interface 33 and each of the ports A0 and A1 (B0 and B1) 31A and 32A of the lower processor 31 and 32. 31A and 32A select TD buses mounted on the common bus interface unit 33 to access different hardware units 41 to 44 according to their priorities.

Then, each port 31A, 32A of the subprocessor backboard 30 applies redundancy (A0, A1, B0, B1) (B0, B1, A0, A1) for each port according to a random port allocation method. The TD-bus selector 34 randomly selects the TD-buses according to the priority of each of the ports A0, A1, B0, B1 (B0, B1, A0, A1), and then selects different hardware units 41-. 44 interface with it is possible.

In addition, the lower processor (31, 32) has a program that allows each port (31A, 32A) to control different hardware units (41 ~ 44) via the TD-bus selector 34 in accordance with priority Because it is stored, you can manage the port efficiently.

In this way, by sequentially mounting the TD-bus on the common bus interface unit 33 of the lower processor back board 30, a method of randomly assigning an arbitrary port regardless of the capacity and type of the hardware units 41 to 44 is applied. Access to the hardware units 41 to 44 is controlled.

For example, the A ports A0 and A1 in the boards PIHA O and 1 of the lower processors 31 and 32 control the hardware units AH / W 0 and 1 41 and 42 of the subscriber. The B ports B0 and B1 control the trunk line hardware units (BH / W 0,1) 43 and 44, which are not subscribers.

On the other hand, the lower processors 31 and 32 each port 31AB of the spare board SPARE when the ports A0, A1. B0 and B1 of the boards PIHA 0 and PIHA 1 located on the back board 30 are defective. To control the hardware units 41 to 44.

Accordingly, the present invention sequentially mounts the TD buses connected to the hardware units 41 to 44 in the common bus interface unit 33 provided on the back boards 30 of the lower processors 31 and 32, and the common bus interface. By selecting the TD bus mounted in the unit 33 in accordance with the priority of each port A0, A1, B0, B1 port in the TD bus selection unit 34, the type of hardware units 41 to 44 are selected. Regardless, the port can be efficiently used and interfaces with different hardware units 41 to 44 in an arbitrary port-by-port redundancy method according to a random port allocation method.

As described above, the present invention sequentially mounts the TD-bus cable to the common bus interface unit of the lower processor back board and assigns ports according to priority through a random port-specific duplexing method according to a random allocation method, as well as hardware. Regardless of capacity and type, ports can be used efficiently and the number of unnecessary subprocessors can be reduced.

In addition, the present invention could not control the corresponding hardware unit when the ports of the same location on both sides of the PIHA-A, B are defective during the duplex operation of the existing subprocessor, but the hardware unit is occupied by other ports through redundancy by arbitrary ports. Since it can be controlled, it is possible to secure the reliability of the system.

Claims (2)

In the interface control device of the lower processor of the large-capacity exchange system, Common bus interface means for sequentially installing a TD-Bus (Telephony Device Bus) between each hardware unit and the back board so as to randomly control the corresponding hardware units for each port of the lower processor; And a TD-bus selecting means for allowing each port of the lower processor to control different hardware units through the common bus interface means. The method of claim 1, And said TD-bus selecting means assigns ports according to priorities in a random port allocation scheme so that each port of said lower processor can control different hardware units.