KR970078375A - Matching Method between Subprocessor and Device of Electronic Switching System - Google Patents

Matching Method between Subprocessor and Device of Electronic Switching System Download PDF

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Publication number
KR970078375A
KR970078375A KR1019960019384A KR19960019384A KR970078375A KR 970078375 A KR970078375 A KR 970078375A KR 1019960019384 A KR1019960019384 A KR 1019960019384A KR 19960019384 A KR19960019384 A KR 19960019384A KR 970078375 A KR970078375 A KR 970078375A
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KR
South Korea
Prior art keywords
matching
pcm
matching unit
subhighways
kbps
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Application number
KR1019960019384A
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Korean (ko)
Inventor
김재평
Original Assignee
유기범
대우통신 주식회사
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Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019960019384A priority Critical patent/KR970078375A/en
Publication of KR970078375A publication Critical patent/KR970078375A/en

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Abstract

본 발명은 TDX-100 전전자 교환기에 있어서 타 블록과의 정합을 하도록 하기에 적합한 전전자 교환기의 하위프로세서와 디바이스간 정합 방법에 관한 것으로서, 종래의 기술에 따른 하위 프로세서와 디바이스간의 정합은 TD-버스 정합을 사용하여 이루어졌는데, 이는 비교적 처리 속도가 느리고 신뢰도도 나쁘며, TD-버스의 정합 장치를 확장하기가 곤란하여 디바이스의 확장이 불가능한 결점이 있었으나, 본 발명에서는 TDX-100 전전자 교환기에 있어서 하위 프로세서(200)와 디바이스(220) 간 통신 방법을 PCM 정합 방식으로 결정함으로써 하드웨어적인 PCM 정합 방법을 규격화하여 하위 프로세서 (200)와 정합하는 모든 디바이스(220)에 동일한 회로를 적용하도록 할 수 있을 뿐만아니라 종래의 TD-버스에 비해 처리속도가 향상되고 신뢰도가 좋으며, 정합부(210)의 확장이 용이하므로 상기 결점을 개선시킬 수 있는 것이다.The present invention relates to a matching method between a subprocessor and a device of an all-electronic exchange suitable for matching with another block in the TDX-100 all-electronic exchange. This is achieved by using bus matching, which is relatively slow in processing and poor in reliability, and it is difficult to expand the device because it is difficult to expand the matching device of the TD-bus. By determining the communication method between the lower processor 200 and the device 220 in the PCM matching method, it is possible to standardize the hardware PCM matching method so that the same circuit may be applied to all devices 220 matching the lower processor 200. In addition, the processing speed is improved and the reliability is higher than that of the conventional TD-bus. Because the sheets to facilitate to improve the above drawbacks.

Description

전전자 교환기의 하위프로세서와 디바이스간 정합 방법Matching Method between Subprocessor and Device of Electronic Switching System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 일반적인 교환기 시스템의 구성도, 제2도는 본 발명에 따른 전전자 교환기의 하위프로세서와 디바이스간 정합 방법의 일 실시예를 나타낸 블록도.1 is a block diagram of a general exchange system, and FIG. 2 is a block diagram showing an embodiment of a matching method between a subprocessor and a device of an all-electronic exchange according to the present invention.

Claims (4)

정합부(210)가 하위 프로세서(200)와 디바이스(220)간을 정합함에 있어서, 상기 하위 프로세서(200)와 상기 정합부(210) 간은 전송 속도 64Kbps, 채널 32의 2048Kbps PCM 서브하이웨이 4조로 정합하며, 상기 정합부(210)와 상기 디바이스(220)간은 1조당 전송 대역폭이 128Kbps인 PCM 서브하이웨이 64조로 정합함을 특징으로 하는 전전자 교환기의 하위프로세서와 디바이스간 정합 방법.When the matching unit 210 matches between the lower processor 200 and the device 220, the lower processor 200 and the matching unit 210 may use a pair of 2048 Kbps PCM subhighways of 64 Kbps and 32 channels of transmission speed. And matching between the matching unit (210) and the device (220) with 64 sets of PCM subhighways with 128 Kbps transmission bandwidth per pair. 제1항에 있어서, 상기 정합부(210)와 상기 디바이스(220) 간의 1조당 전송 대역폭 128Kbps은 전송 속도 64Kbps의 2채널로 이루어짐을 특징으로 하는 전전자 교환기의 하위프로세서와 디바이스간 정합 방법.The method according to claim 1, wherein the transmission bandwidth per pair between the matching unit (210) and the device (220) is composed of two channels at a transmission rate of 64 Kbps. 제1항에 있어서, 상기 디바이스(220)중 한개의 디바이스가 사용할 수 있는 전송 대역폭은 120Kbps 내지 2048Kbps임을 특징으로 하는 전전자 교환기의 하위프로세서와 디바이스간 정합 방법.The method according to claim 1, wherein the transmission bandwidth available to one of the devices (220) is 120 Kbps to 2048 Kbps. 제1항에 있어서, 상기 정합부(210)와 상기 디바이스(220) 사이의 각 PCM 정합은, PCM000 내지 PCM015를 설정하여 상기 하위 프로세서(200)와 상기 정합부(210)간 정합된 소정의 PCM0을 2채널씩 16개 PCM 서브하이웨이로 분배하고, PCM100 내지 PCM115를 설정하여 상기 하위 프로세서(200)와 상기 정합부(210)간 정합된 소정의 PCM1을 2채널씩 16개 PCM 서브하이웨이로 분배하며, PCM200 내지 PCM215를 설정하여 상기 하위프로세서(200)와 상기 정합부(210)간 정합된 소정의 PCM2를 2채널씩 16개 PCM 서브하이웨이로 분배하고, PCM300 내지 PCM315를 설정하여 상기 하위 프로세서(200)와 상기 정합부(210)간 정합된 소정의 PCM3을 2채널씩 16개 PCM 서브하이웨이로 분배함을 특징으로 하는 전전자 교환기의 하위프로세서와 디바이스간 정합 방법.According to claim 1, Each PCM matching between the matching unit 210 and the device 220, the predetermined PCM0 matched between the lower processor 200 and the matching unit 210 by setting the PCM000 to PCM015 To each of 16 PCM subhighways by 2 channels, and set PCM100 to PCM115 to distribute the predetermined PCM1 matched between the subprocessor 200 and the matching unit 210 to 16 PCM subhighways by 2 channels. And PCM200 to PCM215 to distribute the predetermined PCM2 matched between the subprocessor 200 and the matching unit 210 to 16 PCM subhighways by 2 channels, and to set the PCM300 to PCM315 to set the lower processor 200. And a matching PCM3 matched between the matching unit 210 and 16 PCM subhighways by 2 channels. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960019384A 1996-05-31 1996-05-31 Matching Method between Subprocessor and Device of Electronic Switching System KR970078375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960019384A KR970078375A (en) 1996-05-31 1996-05-31 Matching Method between Subprocessor and Device of Electronic Switching System

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Application Number Priority Date Filing Date Title
KR1019960019384A KR970078375A (en) 1996-05-31 1996-05-31 Matching Method between Subprocessor and Device of Electronic Switching System

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465300B1 (en) * 1999-10-28 2005-01-13 엘지전자 주식회사 Device for interface control of Peripheral Processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100465300B1 (en) * 1999-10-28 2005-01-13 엘지전자 주식회사 Device for interface control of Peripheral Processor

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