FI78591B - CENTRALSTYRENHET FOER ETT FOERMEDLINGSSYSTEM, SAERSKILT ETT TELEFONFOERMEDLINGSSYSTEM. - Google Patents

Abstract

1. A central control unit of a switching system, in particular a telephone switching system with a plurality of processors (BP, CP) which are of fundamentally-identical construction and which can be provided with individually-assigned stores (LMY) which carry out distributed switching-orientated functions and which, in the event of a funtional failure, are represented by another of the processors and a central bus system (B : CMY) to which the processors (BP, ZP) are connected, characterised in that only two processors (BP), serving as so-called base processors (BP), additionally carry out operational and/or security-orientated functions in such manner that the first base processor (BPO), namely the controlling processor of the two processors, thus in the controlling state, is capable of carrying out alone these instantaneous operational and/or security-orientated functions but for this purpose is only partially loaded, namely up to x % of its computing capacity, so that up to (100-x)% of its computing capacity can additionally assume switching-orientated functions, the second base processor (BP1) which is in the non-controlling state, is equipped in such manner that it always keeps available at least x % of its capacity in order to possibly later take over the control of the operational and/or security-orientated functions from the first, previously-controlling base processors (BPO), the second base processor (BP1) is thus suitable, prior to assuming control, to itself undertake switching-orientated functions in respect of a maximum of up to (100-x)% of its capacity.

Description

1 78591 Central control unit for a relay system, in particular a call relay system

The invention starts from the central control unit mentioned in the preamble of claim 1. In this case, it is a central control unit of a very large relay system, in which the system has to perform a number of relay functions simultaneously or quasi-simulantly, such as subscriber control for handset pick-up and call number selection, path searches,

Such central control units must have a very high availability. For example, any disturbance caused by the central unit of the transmission system must be less than 1 minute per year of operation. Both the availability and reliability of central processing units are known per se.

CPUs, which are made up of a large number of processors or vast, calculators for all processors or vast, calculators using a common bus system, have long been the subject of discussion, have been developed in different ways and have been implemented, in any case in part, at least experimentally.

Bus systems that allow for the optional allocation of tasks to different processors or counters, especially by means of proxies, are known per se in a wide variety of variants. These also have very comfortable, versatile, very reliable bus systems with high availability, cf. e.g., unpublished DE application publication 33 28 405.

It is known that the central control units of transmission systems have other functions in addition to the above-mentioned transmission functions, in particular still operational and safety-technical functions. Operational technical functions include, in particular, caller ID arrangements and reorganisations for 2 78591 subscriber interfaces, control of cooperation between different transmission system bodies in a general, non-individual context, such as tariff changes, memory expansion and associated address space extensions, forwarders, control path control changes and short circuit changes, videophone connection, automatic partial disconnections and gradual reconnections after malfunctions, load sharing changes, etc. On the other hand, , e.g., 50,000 spaces and connection relay systems in a single telephone exchange you.

In addition, it is known to monitor and register the load on processors in a variety of ways continuously, especially when the processor or counter in question has to run several different programs in time quasi-simulantly.

It is an object of the invention to further develop a highly complex central control unit as set out in the preamble of claim 1, comprising a plurality of processors or calculators, often heavily loaded, performing a wide variety of tasks in parallel, so that the hardware input is small. In particular, the technical functions must remain guaranteed with a very high degree of reliability and usability.

This object is solved by the measures set out in claim 1.

The measures set out in the subclaims provide additional advantages, namely the measure according to claim 2, the optimal utilization of processor capacity, even when each processor has to perform a variety of brokerage tasks allocated to it on a case-by-case basis, the measure according to claim 3 that the 100% load of most processors or calculators occurs relatively infrequently, the measure according to claim 4 of severely limiting the storage of identical information in the processor individual memories so that the total storage capacity of the main memory and the processor individual memories is less than the total number of processor quasi-simultane access to the shared main memory of several processors is allowed to take care of it atta, the operation according to claim 5, during the quasi-simultane cooperation of different processors with the main memory, very short access times.

The invention is explained by means of an exemplary embodiment shown in the figure.

The figure shows a central processing unit in which two basic units BPO, BP1 and 10 other processors CP0 ... CP9 work together via the bus system B: CMY. For safety reasons, the bus system has been doubled, cf. B: CMYO and B: CMY1. In addition to the actual processor unit PU, each processor includes each single processor-unique local memory LMY.

All processors BP / CP perform, at least when sufficient connection requirements exist, simultaneously the respective intermediate technical functions, i.e. functions to meet the momentary requirements imposed by the calling and called subscribers on the switching system.

Essentially similar basic processors BP perform operational and / or safety-related functions, as well as, in particular in connection with higher traffic densities, transmission functions. Other processors CP, on the other hand, perform only relay functions. However, both basic BP processors perform operational and / or security functions in different ways. One of the basic processors, e.g. the basic processor BPO, takes over control in each case, 4 78591, while the other basic processor, in this case the basic processor BP1, keeps its capacity free so that it can take over the operational and / or security functions of the first basic processor BPO if necessary. , so that the second basic processor BP1 completely and immediately takes over the control of all operational and / or technical functions, whereby the first basic processor BPO now keeps itself free to control the operational and / or technical functions in order to take over possibly later. This doubling of the basic processors BP is necessary for safety reasons to ensure that a properly functioning basic processor BP is always available to perform these operational and / or safety-related functions, especially in the event of an alarm reconnection after a partial or complete disconnection. These functions cannot then be left to an arbitrary second CP processor, because, especially in extreme emergencies, there is not enough time to first search for a faultless processor from other CP processors, in particular to search for said relay of the proxy system.

However, the performance of basic and security functions does not require the full capacity of the controlling basic processor, but only x—% of its capacity. Thus, this basic controlling processor still has (100-x)% of its free capacity, which it makes available for the performance of relay functions.

The amount of x, i.e. the load strength of the basic controlling processor when performing operational and / or safety functions, can be determined in two different ways:

It is possible to determine x from the beginning so that it corresponds to the maximum conceivable load of the controlling basic processor BP. In this case, the residual capacity (100-x)% made available for the transmission functions is a time-constant variable. However, it is also possible to denote by x the instantaneous load of the basic processor controlling x, in which case the instantaneous load can be considerably less than the maximum load x (max.)% Present in the worst case of this controlling basic processor BP. In this case, the basic controlling processor in question can - and otherwise also the second non-controlling basic processor - can make available in each case a maximum (100-x)% of its capacity for relay technical functions. However, since in the event of an alarm, the capacity requirement to perform operational and / or security functions is often very high, the load on the basic controlling processor BP and the non-controlling basic processor BP should be less than (100-x)% to ensure a single basic processor BP alone, namely to the controlling basic processor BP can always take on all operational and / or safety functions completely alone.

In principle, it is possible for the basic controlling processor BP in question to perform both operational and backup functions at the same time, especially when a processor module with sufficient total capacity has been selected for this purpose as the basic processor BP.

Especially when the scope of operational and security functions is so large that it can hardly be performed on a single basic processor, especially when retrofitting a forwarding system, e.g. from 50,000 subscribers to 100,000 subscribers in a call transfer system, it is appropriate to place two pairs of basic processors BP, the first in particular, the pair performs only the operational functions, and the other pair, in particular only the safety functions - in each of these pairs the other processor controls and at the same time the other processor does not control during that time, but keeps its capacity free to perform the control accordingly.

In the embodiment shown in the figure, only two defined basic processors BP of substantially similar structure are provided, which, in addition to the transmission technical functions, perform operational and / or security technical functions. Since both of these basic processors BP perform up to (100-x)% of their computing capacity up to a maximum of relay-technical functions, the capacities of all processors (BP / CP) can be used to the maximum. The operation according to the invention thus makes it possible to arrange as little hardware as possible as processors, so that very large capacities are available for the transmission technology functions.

In the example shown in the figure, all processors BP, CP can thus have an identical structure in each case, i.e. they may be formed of identical chips.

In the example shown in the figure, the main memory CMY connected to the bus system B: CMY is formed of several additionally doubled memory banks MB0 ... MB3, whereby in principle processors BP, CP have access to all data of the main memory CMY via the bus system B: CMY. e.g., restricting addresses — the right of access is not restricted.

The figure further shows the peripheral units MBG, which directly or indirectly affect the lines of the transmission network, e.g. in the framework of path searches, switching, signaling, etc. These MBG peripherals have been doubled here, cf. wire cruises. In the example shown, they have their own IO units,. . cf.. IOP: MB. Other such IO units are connected to local buses B: IOC, cf. IOPs, although connected to other such peripherals in each case, but which are no longer shown in the figure for the sake of clarity.

These IO units IOP: MB ... IOP or equivalent, their local buses B: IOC are connected via the IOC of the IO processors, cf. IOCO, I0C1, to bus system B.-CMY. The dots show in the figure that other such IO processors IOC can be provided, especially in very large relay systems.

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Peripherals, cf. The MBG can in each case be connected to different processors BP / CP, depending on the case, divided differently and / or also to the main memory CMY or, respectively, to the MB parts of its memory banks.

These interfaces can be used to make notifications and / or inquiries about MBG peripherals and notifications and / or inquiries about such MBG peripherals. The relay messages and / or queries of the slave MBG are then distributed autonomously via the IOP of the connected IO unit per call, preferably so that the IO unit IOP in question, when receiving a call from the slave MBG, distributes one of the processors to this calling slave MBG CP or vast, the CMY / MB part of the main memory, or vast, allows to be shared via the B: CMY bus system.

In this case, the division of a special part of the special processor and / or the main memory CMY into e.g. two peripheral units MBG (1 connection reserves e.g. two MBGs) is then further stored in a data field, whereby this data field can also be located in the main memory CMY memory bank. These recordings in the data field, in particular with the help of the IOPs of the respective IO units of the MBG of the peripheral unit in question, make it possible to send all subsequent messages or queries of the MBGs of these peripherals following this call to the same BP / CP or above part of the main memory. MB to continue those relay functions that are triggered by the call.

This autonomous division per call allows all processors to CP or resp. BP with near-constant load relay technology - at least this allocation can then be controlled according to the current BP / CP load of the processors in question, so that subsequent relay notifications and / or queries can be executed really quickly on one of the processors with sufficient spare capacity.

The selection or division of the processors for performing the relay functions, which are triggered by the call, can then take place cyclically, in which case, however, in the event of a CP / BP overload of the processor, this processor is skipped in the cyclic 8 78591 selection method. The cyclical division of such tasks or calls into such processors allows a uniform load of processors to be smoked up to a certain amount. Fast, usually all processors have at least a certain part load. Also, an error or a tendency to erroneous processing is always searched for quickly in the processors, as a result of which the operational functions performed by the controlling basic processor BP temporarily disable the erroneous processor and can be skipped in cyclic division, whereby the central control unit - possible partial - self-correction can be performed e.g. by backing up and saving memory contents.

When, as shown in the figure, the main main memory CMY or vast is connected to the bus system B: CMY, its memory banks MB, at least on most BP / CP processors, if not all BP / CP processors, can have quasi-simulamically allocated time slots or time slots. via time multiplexing according to the access to the main memory CMY or vast, its parts. Thus, with this time-of-time duplex mode of operation of the bus system B: CMY, it is not necessary to take long-term communications between the CMY of the main memory and the CP or resp. BP in between, until the second processor CPx, in turn, can finally access the CMY data in the memory, or the other can leave data in it. This time-multiplex mode of operation is thus very advantageous in view of the many processors BP, CP operating simultaneously in parallel and performing different tasks in each case, in order to reduce the access time to the common memory CMY. It is very advantageous when the main memory has several memory controllers or decoders operating independently of each other, in which case one such memory control can in each case be arranged individually for one of the CP / BP processors temporarily. This is especially the case when the main memory consists of several memory banks MB operating in parallel, in which case, in the case of quasi-simulate access to the main memory CMY according to the time multiplex principle, individual time slots or time channels in the bus system B: CMY are arranged for individual memory banks MB.

9 78591 Structure of the individual elements of this central control unit, e.g. processors BP / CP, memory banks MB or equivalent, main memory CMY, IO processors with e.g. different number of local system buses B: IOC, cf. The IOCO outputs 0 ... 7 of the IO processor can be arbitrary in each case. They must be compatible only with the selected bus system B: CMY or equivalent, they must be adapted to its structure or method of operation.

In the local, processor-individual memory LMY, codes and local data that are dynamically important for the flow can be stored in the main memory CMY in order to reduce accesses. However, the processors BP / CP can in each case also be autonomous or vastly autonomous calculators, which can also operate via the bus system B: CMY together with other bodies of the central control units, as the case may be.

The operational and also safety-related tasks controlled by the basic processors BP produce, relatively dynamically, only relatively small loads, so that they do not usually require special load sharing for several processors. The brokerage functions have a much larger scope compared to the operation and backup functions, so that two basic processors BP are usually sufficient for a large number of CP processors.

The peripheral units can be both hardware technical units and the intermediate technical sub-functions of the peripheral units, which perform a larger complex of different functions. It is usually sufficient for them to be connected via non-duplicated, i.e. simple, IO units, cf. IOP: MB ... IOP, IO-processors IOC, when peripherals, cf. MBG, include cruises, cf. pattern. These IO units IOPs and / or their associated IO processors IOCs themselves may have additional inspection functions to complicate uncontrolled error-based access to processors BP, CP, and main memory CMY.

In the example shown in the figure, for the BP / CP processors, SAB 80286 microprocessors, 10,78591, each with a physical address space of 16 MB, have been used. A total of 12 such processors are provided, each with two LM memory LMY. All processors, not just the basic processors, have been doubled to improve error detection and can only be shut down in pairs at a time. These processor pairs operate synchronously.

In the write cycles, signals are always taken from the cheaper processor of each pair, in the read cycles both processors of the pair are taken care of.

The distinction between local, processor-individual memory and main memory is made at, i. addresses reserved for local, processor-individual memory cannot be accessed in main memory directly for that particular processor pair. Communication between processors takes place via the bus system using the urgency setting.

For safety reasons, doubled units of IO processors IOC, with their associated local bus B: IOC and IO unit IOP, usually share the resulting loads.

In the example shown, the data exchange between the IOPs of the IO units and the processors BP / CP is performed via the main memory CMY, in which case the modules 8086 can be used for the processors IOC.

Local buses B: IOC have also been used in time-division multiplexing, i. with cycle insertion, which significantly increases the throughput of this bus so that the second cycle can be started even before the first cycle has ended. The bus of the bus system B: CMY has also been doubled for security reasons, as has the main memory CMY or equivalent, its parts, cf. the corresponding symbolically represented wires in the figure. In addition, the cable cruises shown in the figure mean that in the absence of modules, e.g. bus system part B: CMY1, spare paths are always available for the second part of all dual devices.

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Normally, both buses of bus system B: CMY operate in parallel and process identical information.

Bus system B: CMY operates according to the multiplex method with four time slots, which is sufficient when using 12 processors for the BP / CP relay system, in any case initially. Four memory banks MBO are arranged for four time slots ...

MB3 so that each time slot is fixedly arranged for one memory bank, which has proved to be sufficient for a long-distance call transfer system with a few tens of thousands of subscribers. The arbitration has been performed before the time slot is allocated to the processors to improve the performance of the BP / CP / IOC bus system.

Ancillary units also include O / M (Operation and Maintenance) units, which have been used frequently in central control units to date, cf. e.g., a description of such central control units, in particular type SSP112D, in Siemens, telcom report 4 (1981), appendix "Digitalv'ermittlungssystem EWSD". This publication also describes in more detail the operation of the ancillary units in particular.

Other details of the example shown in the figure are in Finnish patent applications Nos. 843755, 843756, 843757, 843759, 843760 filed simultaneously.

Claims (5)

1. A central control unit for a relay system, in particular a call relay system, comprising: - a plurality of substantially similar processors <BP, CP), which may have individually dedicated memories (LMYs), which perform shared relay functions and for which one of the processors acts in the event of a fault, and - one central bus system <B: CMY) to which the processors (BP, CP) are connected, characterized in that - only two processors (BP) perform, in addition to the basic processor (BP), additional operational and / or security functions, so that - the first, the basic processor (BPO) in the controlling state tends to perform these current operational and / or safety-related functions alone, but is loaded for this purpose only x -% of its pocketing capacity, so that it can take on up to (100-x)% - the second basic processor (BP1), which is not in control mode, is equipped so that e it keeps at least x * of its capacity available at any given time in order to take over the operational and / or safety functions from the first basic processor (BPO) at a later date, - the second basic processor (BP1) therefore tends to take on a maximum of 100-x ) up to% of its capacity for transmission functions. Central control unit according to Claim 1, characterized in particular by a main memory (CMY) connected to the bus system (B: CMY>), characterized in that - at least some of the dissertation peripherals (MBGs) are connected via IO units (IOPs) and IO processors (IOCs) bus to the system (B: CMY), - peripheral gigs (MBGs), which affect the transmission network cables and can be shared with different processors (BP, CP) and / or the main processor (CMY) for notifications and / or queries, share their relay notifications and / or its queries autonomously via its IO units (IOPs) per call 13 78591, so that each IO unit (IOP), when it receives the call, allocates one of the processors (BP, CP) and / or main memory (CMY) to the calling peripheral unit (MBG); ) part or equals, part or equivalents of its memory bank (MB), preferring it to be shared by the bus system 03: CMY) and these peripherals (MBGs) can be used to send all the messages and / or queries of these peripherals (MBGs) following this call to the same processor (BP, CP) or, respectively, to the same part of the main memory (MB). Central control unit according to Claim 2, characterized in that - the selection or division of the processors (CP, BP) is generally cyclical for performing the transmission functions, - but when the processor (BP, CP) is overloaded, this processor is skipped in the cyclic selection method. Central control unit according to Claim 1, 2 or 3, characterized in that - the main memory (CMY) is connected to the bus system (B: CMY), and - at least the majority of processors (BP, CP) have access to the main memory quasi-simultaneously according to the time-multiplex principle. (CMY) through time slots allocated to them, or time slots. Central control unit according to Claim 4, characterized in that - the main memory (CMY) consists of a plurality of memory banks (MB) operating in parallel, and - in connection with access to the quasi-simulative main memory (CMY), individual time slots or time channels are arranged in each case for individual memory banks (MB ). 78591 1 4