KR820002241B1 - Distributed control digital switching system - Google Patents

Abstract

A disbributed control digital switching system is described in which a plurality of subscriber lines and trunks are provided with a switched access to various processing functions shared over a plurality of time shared multiplexed lines. Each processor of a first group of processors is dedicated to a group of terminals such as subscriber lines or trunks, and communicate with processors in a second group to provide pooled processing functions to one or more of said groups of teminals through a digital switching matrix.

Description

Distribution Control Digital Switching System

1 is a block diagram of a distribution control system in the present invention.

2 is a diagram showing a certain amount of extended functionality of the switching network in the present invention.

3 is a schematic block diagram of a multiport switching element in the present invention.

4 is a view showing one plane of the switch network in the present invention.

5A, 5B, 5C and 5D show the expansion of the switching network in the present invention.

6 is a block diagram of a line terminal servo unit.

7 is a block diagram of a trunk terminal subunit.

8 is a schematic diagram of a TDM bus of a multiport switching element in the present invention.

9 is a block diagram of the logic of one port of a multiport switching element in the present invention.

10A, 10B, 10C, 10D, and 10E show channel word formats used in the present invention.

11A, 11B, 11C, and 11D are diagrams of additional channel word formats used in the present invention.

12 is a representative connection diagram between terminals via a switching network in the present invention.

13a, 13b, 13c, 13d, 13e, 13f, 13g, and 13h are timing diagrams showing the operation of the switching element in the present invention.

14A, 14B, 14C, 14D and 14E are detailed timing diagrams showing the operation of the switching element in the present invention.

FIG. 15 is a diagram showing a TDM bus line of a switching device in the present invention. FIG.

FIELD OF THE INVENTION The present invention generally relates to distributed control digital communications and computer systems for toll, tandem, local, local, convergence and expansion, digital switching networks and telephone exchanges. The present invention also relates to data processing functions or other terminal processing functions provided by a first group of processors or computers in a multiprocessor or multicomputer communication system, where the second pool processor group is independently different from other large groups of terminals. In connection with other processing functions, communication and data exchange between two different groups of processors or computers are related to a system between common transmission lines through a digital switching network.

The invention also relates to a multiport switching element characterized by a port acting as an inlet or an outlet depending on network application conditions as one side, bilateral and multilateral switches in a network.

In modern telephone switching systems, data indicating the status of subscribers and trunks must be provided in the switching system, and data must also be specified by the switch in response to the status of subscribers and trunks, respectively. The data to be displayed is determined according to signals such as the network, the service class of the subscriber, the class of the trunk call, the conversion of the directory number into the device number, and the conversion of the device number into the directory number.

In a conventional central control system, the data can be obtained from a common memory, doubled for safety and reliability and achieved as a serial operation on the extracted data by the central control computer. Conventional multi-processing common control systems are achieved by co-memory and require more than one processor to simultaneously acquire data, but as the number of processors increases, the actual loss of production and tonality problems increase.

The decentralization of control and distributed data processing is intended to solve the problems inherent in the central control system. A switching system in which a memory program controller is distributed over the entire conventional system is described in US Patent 3974343. Another conventional gradually controlled distribution control switching system is described in US Pat.

Conventional systems have focused on achieving high efficiency of processing functions to provide increased processing power by multiprocessing. However, the unwanted interaction between software packages results in unpredictable interference with other features currently in operation due to changes and additions to the software features.

The reason for the problem of the conventional common control architecture is that the efficiency of the stored software package is efficient because the memory program control processing function must share a number of things arbitrarily according to the demand of traffic occurring and terminated over time, whether it is a multiprocessor system or not. The operation could not be made.

The present invention provides a net of the necessary processing functions of a subsystem provided by such a distribution processor, as a system that is specifically used without separate control or central computer complex. Thus, a group of control functions of a subsystem is performed by the processor on which the subsystem depends. However, when it is more efficient for another processing function of the subsystem to be performed by another processor, it is performed by another processor.

In addition, the present invention provides a switching network structure including path selection and other control signals by the same transmission path through the network as well as data between the multi-channel numbers and the terminal delivered by the PCM voice sample or network. Each terminal carrying a line or a line of data from a crunk or other data source communicates to the other terminal through another terminal unit and provides, maintains, and terminates the way to the other terminal unit through the switching network. It contains various devices and control logic. All processors communicate through a switching network. The switch, which includes switching elements that provide time and space switching headroom, is constantly scalable and increases in traffic traffic from about 120 to 128000 terminals or more without disrupting service and rearranging current connections. load, and actually operates as a non-blocking network. The faulty switch element is easily and automatically identified, separated and passed through the traffic.

In the present invention, a group switch in which a multiport one-way switching element can be arranged in an inlet / outlet structure is provided. For example, there are 8x8 switches that include space and time switching in the ST structure. The path selection through the network of switching elements is carried out by control commands transmitted by the voice channel.

In addition, a reflective switching device is provided, for example, the path setup at the second stage switch is reflected to form a folded network through the voice line when the third stage is not provided. However, the exit of the second stage switch is reserved for future connections in the expansion of the network. When expanded as a third stage, a possible outlet of the second stage is connected to the input of the third stage switch.

1 illustrates a block diagram of a distributed control digital switching system. In this system, a group switch 10 is provided to provide a transmission path of coupling data provided by a terminal unit between terminals. Switch multiple connection points between terminal units.

The terminal unit in the present invention is a subsystem that assists the terminal group terminating in the first stage switch in every plane of the group switch. Each terminal unit has eight access switches through which data from the terminals are connected to the group switch 10.

The terminal subunit in the present invention is also a subsystem of terminal units that assists the terminal group terminating in a safety pair of access switches.

Each terminal unit contains four safety pairs of access switches. PCM data at each terminal is, for example, a signal from a telephone line circuit of the type described in US Patent Application No. 773,713, filed March 3, 1977, assigned to the assignee as the present invention.

Terminal units 12, 14 and 16 are symbolically represented. However, the group switch 10 enables switching of 128 terminal units or more. Therefore, terminal units 12, 14 and 16 are merely shown. Each terminal unit has an interfacing function. For example, it is possible to interface with 480 trunks of four subunits, namely, 1920 subscriber line terminals, which are terminal subunits 18, 20, 22, and 24 shown in terminal unit 12. FIG. .

A 32-channel PCM multiplexed digital line multiplexing 30 bidirectional subscriber lines is connected to the terminal unit.

Each terminal unit, such as terminal unit 12, is connected to the group switch 10 by a plurality of multiplex transmission links, each comprising two unidirectional transmission paths. Each terminal subunit 18, 20, 22, 24 of the terminal unit 12 is connected to each plane of the group switch 10 by the two transmission links described above. Terminal subunit 18 is thus connected to plane 0 of group switch 10 by transmission links 26 and 28, and plane 3 of group switch 10 by transmission links 30 and 32. Is connected to. The terminal subunit 18 is likewise connected to planes 1 and 2 of the group switch 10 by way of a transmission link. Also in the same manner as the terminal subunit 18, the subunits 20, 22 and 24 are also connected to respective corresponding planes of the group switch.

Each transmission link 26, 28, 30, and 32 is a bidirectional feature, as shown in the terminal unit 18, a pair of unidirectional transmission paths in which each transmission path allows only one-way data flow. Consists of 32 channels of digital information are time-division multiplexed (TDM) in serial bit format through each unidirectional tactic path. Each frame of the TDM format includes 32 channels. Each channel consists of 16 bits of information. The bit rate is 4,096 Mb / S. This rate is clocked across the system, thus the system can be characterized as ratio synchronous.

As will be described later, because the system is phase asynchronous, there is no constant phase relationship between whether data bits in one frame are received by another switching element or leucine on a different port than one switching element. Such ratio synchronous and phase asynchronous switching systems can be fabricated by multiple multiport switching elements in group switches and access switches. When digital sound samples are sent anywhere in the system or received from a specific terminal, they must be time-multiplexed with the correct channel on the transmission path between the switching elements connecting the terminals. Since the channels interconnecting the terminals can be changed, time slot exchange is provided by the switching element. It is well known that time slot exchange, i.e., exchange the difference between the data of one channel and the data of another channel, is disclosed, for example, in US Patent Application No. 6 assigned to the assignee and the same person of the present invention. 776,396 (filed Feb. 7, 1977). As will be described below, a unique multiport switching mechanism is provided that includes a 16-port switching element that acts as a 32 channel time switch and a 16 port spatial switch, usually within 1 frame time for all applied inputs. The digital speech sample occupies 16 baht of 16-bit channel words, and the remaining two bits are used as primitive bits (indicating whether the data is 14 bits from other channel words). Thus, 16-port switching elements are used, for example, for 14-bit linear PCM samples, 13-bit linear PCM samples, 8-bit compressed PCM samples, 8-bit data bytes, and the like.

Each terminal unit contains two groups of processors. For example, in the terminal subunit 18, a first group processor such as processors A ₀ , A ₁ ..... A ₇ is attached to separate terminal groups called terminal clusters. It has a special group of processing functions, such as setting up and providing the terminal's interface within a terminal cluster. High traffic clusters, such as telephone trunk lines, can contain up to 30 terminals, while low traffic clusters, such as telephone subscriber lines, can contain up to six terminals. Each terminal subunit can interface up to four high traffic clusters. Thus, it includes four type A processors, while the low traffic subunit can interface to eight low traffic clusters, thus including eight type A processors. Each A-type processor may include, for example, Intel's Model 8085 microprocessor interface and accompanying PAM and ROM memory. Thus, each terminal unit may include, for example, 1920 low traffic terminals (in the case of subscriber lines) or 480 high traffic terminals. Each terminal cluster, such as terminal cluster 36 in subunit 18, includes one A-processor and an accompanying cluster terminal interface. These cluster terminal interfaces are each connected to two access switches 42 and 44 in terminal subunit 18 by a pair of bidirectional links 38 and 40, respectively.

The access switching elements such as the access switch elements 42 and 44 of the sub unit 18 have the same switching element structure as the switching elements of the group switch 10. Access switching elements 42 and 44 may access one of the second group processor pairs, such as processors B ₀ and B ₁ , respectively, in subunit 18. Other pairs of B-type processors are included in terminal subunits 20, 22, and 24. However, only the B-processor of the subunit 18 is shown for effective techniques. The second group processor, the B-processor, provides a second group processing function such as call control (processing of data related to a call such as signal analysis, conversion, etc.) to the terminal interfaced by the terminal subunit 18. It can be manufactured by Intel Corporation and microprocessor model No 8085 or equivalent. For safety reasons, the processor is constructed by insertion of the same processing functions as in the B-processors 46 and 48 and the access switches 45 and 44 of the terminal unit 18. Therefore, each terminal cluster, such as the A ₀ cluster, selects one of the stable pairs.

That is, if there is a failure in one of the safety pairs, the B-processor 45 is selected through the access switch 42, or the B-processor 48 is selected through the access switch 44, thereby providing another path. .

In FIG. 2, a group switching matrix is shown with four switching capability planes, plane 0 at 100, plane 1 at 102, plane 2 at 104, plane 3 at 106, and plane 3 at 106. FIG. Multiple planes are provided to meet traffic and service requirements for specific system applications. As an example, it is possible to provide two, three or four switching planes, thus serving over 120,000 terminals. (I.e., subscriber line terminating in the line circuit as in US Patent Application No. 773,713 is possible.

In one embodiment, each switching plane may include up to three switching elements. Access switching to select a particular plane to be connected may be located in the terminal unit 12, not in the group switch 10, respectively. The particular swept element plane is selected to be connected at the terminal unit and by the access switching stage. Thus, the access switching element 42 in the sub unit 18 may select plane 0,100 via the link 26 and plane 3,106 via the link 30, for example.

The group switch 10 may increase the number of planes in order to improve data traffic processing efficiency, or increase the number of stages of switching elements or the number of switching elements in each stage to increase the number of terminals provided by the group switch. It can be expanded constantly. In typical applications, the number of stages per plane of the group switch 10 can be scaled as follows.

Referring to FIG. 3, the basic switching element, which is the structure of all switching stages in the present invention, includes a multiport one-way switch 300, denoted as a 16-port switching element. Here, the number of ports may be more or less than 16, and 16 is merely an example. A one-way switch may be defined as a switching element comprising a plurality of ports with bidirectional transmission capability in which data received at any arbitrary port can be switched and transmitted by any port. All data transfers from port to port within switching element 300 are performed through parallel bit time division multiplex (TDM) bus 302 to operate, thereby transferring paths between any two ports in the switching element. Spatial switching, defined as providing, is possible.

Each of the ports 0 to 15 of the switching element 300 includes respective reception control logic R × 302 and transmission control logic T × 306 as indicated by port number 7 as an example. Data can be transmitted from any port, such as port 7 of switching element 300, to another port, and can also be transmitted to the reception control input line 308 from a switching element such as switching element 300. Each of the control output lines 310 is connected to transmit one frame of 512 serial bits corresponding to 32 channels of 16 bits at a 4,096 Mb / s system clock rate.

The data transmitted serially from the 16 ports are all rate synchronous and phase synchronous. In other words, the transmission control logic 306 and the corresponding transmission control logic of the other 15 ports of the switching element 300 transmit the same bit position of one frame at every 4,096 Mb / s click rate. On the other hand, the reception of serial bit data in the reception control logic 304 of the port 7 and the reception control logic of the other port of the switching element 300 is only ratio synchronous. That is, since there is no particular correlation for any bit in one frame, the signal can be received at any moment on any two ports. Thus the reception is phase asynchronous. Each of the reception control logic 304 and the transmission control logic 306 includes a control logic section and a RAM, the details of which are shown in FIG.

4 shows one plane (eg plane 0,100) of the group switch 10. As described in the third path, the switching elements such as 108, 110, and 112 from the group switch plane are composed of 16 port one-way switching elements 300. By definition, the location of a switching network means that the switch pod is designed as an inlet or outlet. Ports 0 to 7 of the switching elements 108 and 110 of the first and third stages of the third stage group switch plane 100 are used as inlets and used as ports 8 to 15. Is used as an outlet. Therefore, all switching elements, such as the switching element 112 which is seen bidirectionally in the third stage, are designed to be unilateral, ie all ports are inlet.

In general, because any group switch stage requires additional stages and thus requires constant growth of the network, the stage should be provided as a bidirectional stage with outlets reserved for growth.

However, if at any stage the size of the network must be greater than half the maximum required terminal, then the stage is a one-way stage. This allows for constant expansion to the size of the maximum required circuitry without rearrangement of the links between the stages.

The constant extension of the switching element 300 to the switching plane 100 is well illustrated in FIGS. 5A to 5D. 5A shows the size of the group switch plane of the group switch 10 required for application to a terminal unit as long as it has about 1000 subscriber lines as an example.

Port 0 is thus connected to line 26 of terminal subunit 18 and ports 1 through 7 are connected to other access switches of terminal unit 12. Ports 8 to 15 are reserved for the growth of the network.

5C is an example of the next stage of growth of the group switch plane 100 in two terminal units such as the terminal units 12 and 14. Thus, the two first stage switching elements are provided to be connected, for example, to each plane having 0, 1, 2, 3 second stage switching elements and the plane of the group switch. The exit from the second stage is reserved for the next network growth, which network (one plane is shown) is reserved about 2000 subscriber lines and this network (one plane is shown) is about 2000 subscriber lines To service.

5c shows the growth of the switching plane 100 for application to eight terminal units. The first and second stage switching elements are shown to be fully connected and only the second stage outlet is available for future saints, thus connecting the subgroups of up to eight terminal units, as shown in Figure 5d. As shown, third stage switching per plane must be added. That is, in FIG. 5D, the group switch planes in which 16 terminal units are extended are connected. Usually the switching capability on the circuit of FIG. 5c is about 10,000 subscriber lines and the switching capability of the network of FIG. 5d is about 20,000 subscriber lines. The unconnected ports shown in Figures 5b, 5c, and 5d are used for expansion and each plane of the network is extended by the connection of these ports as in Figure 5d, and Figure 4 has switching capability of more than 100,000 subscriber lines. It can be extended to network.

Referring to FIG. 6, a line terminal subunit is shown in which each terminal cluster includes up to eight terminal clusters 36 including 60 subscriber lines, terminal interfaces, A-microprocessors, and the like. The three terminal clusters are (36), (37) and (39). The access switches 180 and 181 of the terminal subunit 18 serve eight terminal units, and only three simplify the technology. Each terminal interface, such as interface 190, is associated with, for example, sixty subscriber lines from sixty line circuits and an A-micro processor 198, which may be routed or terminated through a switching network. It has the same processing function as the control and is connected to the line at the terminal interface 190. Each terminal interface 190 has a bidirectional transmission link, such as link 199, and is connected to the ports of each access switch, such as access switches 180 and 181. Each access switch, such as access switch 180, includes a 16 port switching element as shown in FIG. 3, with the switch grouped through an outlet port such as (8), (10), (12), or (14). The B-processor 293 is accessed through an exit, such as an exit port 9, or a plane of the switch 10. Here the B-processor performs other processing functions such as call control. Outlet ports of unused access switches such as ports 11, 13 and 15 are shown as redundant and are used to install other devices such as alarms, monitors and diagnostic controllers.

FIG. 7 shows a trunk terminal subunit, such as subunit 18, which is functionally identical to the line terminal subunit described in FIG. However, the subunit serves a small number of high traffic inputs. To address the increased traffic strength of trunk groups compared to line terminals, trunk terminal subunits include up to each terminal interface terminal. Therefore, in this structure, the inlets 4 to 7 on each of the access switches 180 and 181 are not used.

Thus, trunk terminal clusters 60 and 61 of four trunk terminal clusters, each comprising terminal interfaces 62 and 63 and an A-processor and memory 64 and 65 are shown.

The B-processors and accompanying memory 66 and 67 are connected to the access switch 180 and the B-processors and memory 68 and 69 are connected to the access switch 181, they are shown in FIG. As a structure such as the structure may include, for example, Intel's Model 8085 microprocessor.

Referring to FIG. 8, the 16 port switching element 300 described in FIG. 3 is described in more detail. Each port includes, for example, reception control logic 304, transmission control logic 306, input and output unidirectional transmission paths 308 and 310, such as port 15 of switching element 300, A parallel time division multiplexing bus 302 can be accessed within the switching element 300.

In the embodiment of the present invention, the connection is made through the switching element 300 in the basic view of unidirectional. The unidirectional connection of one port's input channel (one of the 32 channels) and one port's output channel (one of the 512 channels) is made by an inchand command called a "select" command. This "select" command is contained within one 16-bit word of the input channel requesting the connection. Several types of connections are possible through switching elements, which are differentiated by information on the "selection" terrain. Typical selection commands are as follows. Any port, any channel, and this command signal are received by the receive control logic of that port, allowing access to any channel at any exit of any port. &Quot; Port N, arbitrary channel ", this command signal is, for example, a selection signal to be connected to an arbitrary channel in a feature port N such as port 8. This command signal is " port N, channel M ", which is a selection command for connecting to a predetermined channel M such as channel 5 on a specific port N such as port 8. As described above in Fig. 9, other specific "selection" commands, such as "connection command to any odd or even port" and commands such as a specific channel 16 command and a channel (0) holding command, may be used as a switch module (one module). It is included in a port) as long as a sieve is included. The reception control logic 304 of each port is synchronized with inflow data from other switching elements. The channel number 31 of the incoming channel is used to fetch the port and channel address from the storage RAM. The receiving logic 308 when the Mulplex module accesses the channel's bus 302. Transmits the received channel word along with the channel destination port and channel address to the TDM bus 383 of the switching element 300. Every bus cycle (data from the receive control logic 308 to the transmit control logic 306). The transmission logic at each port gets the port address from the TDM bus 302.

If the port number on the bus 382 matches any address of a particular port, the data on the bus 302 (the channel word is read from the channel RAM to the data RAM of the address-recognition port of the address, such as the address read from the channel RAM). This results in a single word data transfer from the reception control logic to the transmission control logic via the bus 302.

The port transmit and receive control logic of the port 300 operates as follows. 4,096 Mb / s data on line 308 is applied to input synchronization circuit 400, which provides information and bit and word registration on line 308.

The output of the registration circuit 400 is a 16-bit channel word and its channel number (indicating the channel position in one frame), the output of which is connected to the FIFD (Fifst-in-first-out) buffer register stack 402 and is connected to the line. Since the data on 308 and the timing of the bus 303 are asynchronous, the data on the required line 403 and the timing of the bus 302 are synchronized.

The FIFD buffer 402 output consists of a 16 bit channel word and a 5 bit channel number. Information included in the 16-bit channel word indicates the content of the information included in the word. This information is contained in the protocol bits of the channel word and, together with the information in the receive control RAM 404, determines what operation this channel of this frame should perform by the receiver circuit 406.

Actions by five commands "SPATA", "SELECT", "INTERDGATE", "ESCAPE", and "IDLE / CLEAR" are possible.

If the protocol is a "sparta" (voice and data word), the channel word is sent to the bus 302 unmodified and the channel address is the channel RAM 408 and the port RAM 410 and hence the destination port and channel add. Patches the connections and connects them when the port is in the receive logical bus access time slot. If the selection command is "random port, arbitrary channel", the first freeport selection circuit 432 selects the transmission logic of the idle channel. During the access logic TDM bus 309 access time, " first free channel selection " is also performed in the selection transmission logic of the selection port, and the selection transmission logic returns from the first free channel search circuit 414 to the " free channel " number. . The " NACK " receiving circuit examines the contents of channel 16 for path setup fault indications from the following stages of the switching network set up via the transmit logic 306 of the module. The "naked" search logic 408 examines the unrecognized channel of the reception control RAM 404, and the channel number of the unrecognized channel is pulsed out of the transmission logic of channel-16.

The transmission logic 306 checks the state of the port address line of the bus 302 with the module identification code in the decode port logic.

If the correct port address is decoded in the course 420 and the selection line of the bus 302 does not operate, the contents of the spata line of the bus 30a may be changed by the state of the channel address line of the bus 302. Write to the data RAM 422 of a given address.

If the selection line of the bus 302 is operated and the first free channel search is requested by reception control such as 406 (in the case of random channel selection), no write operation occurs in the data RAM 422 and the free channel number Is returned to the request reception logic such as the buffer 304 to the first free channel search circuit 414.

The data RAM 422 is a time slot exchange and is read sequentially by the control of a counter included in the transmit / vistiming circuit 428. The word read from the data RAM 422 is loaded into a register 430 of parallel input-serial output type to couple the line 300 to a serial bit stream for transmission at 4,096 Mb / s. The word locked in the output register 430 may be modified in channel 0 or channel 16. In channel (0) an alarm signal can be inserted on line 432 for error checking, and " nak " channel information can be inserted in channel- 16 by logic 424 as needed. The transmit control RAM 426 contains status information of each outgoing channel. Transmission control logic 424 associates read and write operations in data RAM 422, transmission control RAM 426, free channel search 414, and output register 430 loading.

The connection between the terminals via the network will now be explained.

As mentioned above, the 16-port switching element provides time and space switching in all transmission paths. Information arriving at an inlet to any port on any channel is sent to any port outlet by a 16-port switching element, whereby spatial switching is achieved, and by any channel therein. Time switching takes place. The transmission of all voice and data (SPATA) over the network, from the input channel (one of 512) to the output channel (one of 512), as determined by 32 channel words per frame on any given transmission path during path setup. This is the result of each port in a multi-port switching device implementing the switching. FIG. 10 shows an example of a channel word format applicable to all channels from channels 1 to 15 and from channels 17 to 31 (all are “sparta” channels).

11 shows the channel word format of channel 0 (maintain and synchronize) and the channel word format of channel 16 (special purpose control, " nak ", etc.).

The "sparta" channel can be used for both digital voice and data transfer between processors. When voice is transmitted, 14-bit is used for encoding PCM samples in the channel word and 2-bit is used for network protocol selection. When used for path setup control, 13-bit channel words are used for data and 3-bits are used for protocol selection.

The channel word format enables switching over the entire network, including focusing through multiple 16-port switching elements.

This connection is unidirectional. For bidirectional connections, two unidirectional connections are required.

10, channel word formats of all channels except channels 0 and 19 are illustrated. 11 illustrates a channel word format of channel 16. 10A to 10B, data feed formats of "selection", "question", "future", "sparta" and "idle / clear" signals are shown. 11A through 11E show the "Select", "Escape", "Hold", and "Idle / Clear" formats of channel 16 and the alert format of channel 0. The channel word in channel 0 includes a frame sync bit pattern (6-bit) between adjacent 16-port switching elements.

The "select" command sets up the connection via the switching element.

The "question" command is used to determine the port that is selected for the switching elements of the path after the path is set up.

The " future " command is a command for distinguishing between the digitalized syllable samples and the information when a path for information transfer between the two terminal clusters is set up.

The "sparta" format is a command for transferring voice and data information between any two terminals.

The "idle / clear" command format indicates whether the channel is cleared.

In the case of the channel 16, the "select", "future", and "idle / clear" commands are similar to those illustrated in FIG. However, in the case of the channel 16, there is no "sparta" crowd, no "question" instruction is necessary, and the channel 16 has a "naked" channel, so a command of the type "selection" is prohibited. The " hold " command maintains the connection of the channel 16 once set up by the " select " command. Channel 0 is reserved for maintenance and diagnosis of the network.

According to FIG. 12, the terminal subunit comprising the access switching stage described in FIG. 1, part of the access switches 42 and 44, and a group switch 10 comprising three stages of switching ( 18) is shown. The individual planes in the group switches and the individual switching elements in each stage are not shown for the sake of the technology's fun.

The connection through the switching network is set up from one terminal interface, such as 690, to another terminal interface, such as 190. Or from a B-processor, such as 183, to another processor, such as the A-processor 198, associated with the terminal interface 190 by a series of "select" instructions. In other words, a series of "select" signals refers to the channel word format inserted in the PCM frame bitstream between the original terminal interface (or processor) and the accessor switch in successive frames of the channel assigned to the connection.

The connection via the switching network is made by a sequential series of connections through each switching stage. This connection proceeds from the lower numbered stage to the higher numbered stage by the "inlet and outlet" through the switching element until a predetermined "reflection stage" is reached. Reflective connection refers to a connection between inlet ports of a switching element, whereby a connection can be made without penetrating into more switching networks than is required to complete the desired connection. A detailed description of the concept of reflection in a switching network is well described in the application filed in co-pending US application no.766396 (filed Feb. 7, 1977).

When a "inlet to inlet" connection is made via the switching element at the reflecting end, the connection proceeds from the higher numbered end to the lower numbered end by the "outlet to inlet" connection via the switching typo.

The choice of "reflective end" is predetermined by the unique network address of the required terminal interface, such as 190. The general rule is:

If the terminating terminal interface is in the same terminal subunit, reflection occurs at the access switch.

If the terminal terminal interfaces are in the same unit, reflection occurs at the first stage.

If the terminating terminal interface is in the same group as the terminal unit, reflection occurs in the second stage.

In all other cases the reflection takes place in the third stage.

Figures 1 through 4, again, have eight bidirectional transmission links in each group switch plane as shown in plane 0 of Figure 4, the transmission link being terminated in one switching element in each plane. Figure 12 shows the characteristics of the unique network structure of the terminal unit. This switching element is seen to have a unique address when viewed from the center (third stage) of the group switch 10. Thus, when viewed from any switching element in the third stage, for example as shown in FIG. 4, the switching element 108 is accessible through inlet 0 of the third stage, followed by inlet 0 of the third stage.

This determines the address of the terminal unit, that is, Tu (0,0). Furthermore, it is determined to be introduced by the second stage inlet in the address terminal unit of the terminal subunit. That is, as in FIG. 1, the terminal subunit 18 is seen as TSu (0) of Tu (0,0) because the first stage switch (0,0) is only addressed from inlets 0 and 4. . In a similar manner, each terminal interface in each terminal cluster is uniquely addressed through an entry address on an access switch. Thus, the address of a terminal interface, such as interface 190 of FIG. 12, is shown, for example, by any other interface, such as 690 in terminal unit 16, independent of the switching elements in the third stage. "Reflection".

Thereby, the path setup control A-processor 698 sends the following sequential " select " commands to the network to set up a connection to the terminal interface 190 whose network address is (a, b, c, d) as an example. Will be exported.

Frame 1. "Selection", "Arbitrary Storm Port", "Arbitrary Channel": This command enables "Spartater" access to the group switch end through the access switch.

Frame 2. "Selection", "Any Port", "Any Channel": This command allows connection through the first end of the selected plane.

Frame 3. "Selection", "Any Port", "Any Channel": This command allows the connection through the second end of the selected plane.

Frame 4. "Selection", "Port (a)", "Any Channel": This command reflects the second stage connection through the third stage.

Frame 5. "Selection", "Port (b)", "Any Channel": This command reverses the connection via the second stage.

Frame 6. "Selection", "Port (c)", "Any Channel": This command reverses the connection via the first stage.

Frame 7. "Select", "Port (d)", "Any Channel": This command reverses the connection to the terminal interface (a, b, c, d) via the access switch.

This network advances the switching to any reflective point at the stage determined by the reflective stage, and retracts through the network with a constant address at that stage regardless of the reflective switching element.

This series of "select" commands can be used to set up the connection to TI (a, b, c, d) by any terminal interface, and the "first free channel" selection mechanism described above is the minimum transmission delay on the channel. Guarantees. The subset of the sequence can be used where the reflection from the preceding switching stage is possible from the above decision rule. Thus, as shown in FIG. 12, the B-processor 183 in the same terminal subunit 18 as the terminal interface 190 only needs the following subset of the sequence.

Frame 1. "Select", "Port (d)", "Any Channel":

The processing functions performed by the A and B processors are performed by the specific computer program used. However, examples of processing functions are as follows: Terminal control-provides various services to subscribers or trunk lines. Generates signals for calling terminals under signal control-terminal control processing and decodes and interprets a series of signals and numbers related to the operation of the terminal control processor as a telephone event.

Switching Control-Change, maintain and set up the path through the network indicated by the terminal control and signal control functions.

Perform all operations on a database bare-physical database and allow all processing to work independently of the organization of a particular database. Hardware Control-This actually controls the control of the hardware that interfaces subscriber lines and trunks and the processing for terminal units and switching devices. An example of processing function distribution is the allocation of hardware control, which is performed by each A-microprocessor up to 60 line terminals, or 30 trunk terminals, and by B-micro processors for further terminals. Of course, switch control can also be accomplished by an A-micro processor.

Referring to FIG. 13, a timing diagram showing the operation of the switching element 300 is shown.

FIG. 13A shows the eight time slots of channels (0), (1) and channel (2), with 16 time slots forming one channel and each time slot number recorded in hexadecimal notation. 302) time slot number and channel number are shown.

Figure 13b is a 4,096 Mb / S bus clock.

FIG. 13C shows frame synchronization, which is a port synchronization command that appears on the bus 302 of the time slot E of the channel 31.

13d to 3b, in the case of ports (0), (1), (2), (14) and (15) of the switching element 300, the time enveloping of the bus 302 is Indicates passing the crop. Ports 3 to 13 are not shown, but the operation is the same.

Bus transfer envelopes 501, 502, 503, 504 and 505 for each port (0), (1), (2), (14) and (15) Time multiplexed. Each envelope is any time on any one line of TDM bus 302, including four time slots P, D, W, and R when a particular operation occurs on a particular line of TDM bus 302 at a particular time. Back only one port is transported. The exact start time of the transport envelope is determined by the unique port address code.

According to FIG. 14, FIG. 14A shows the system clock shown in FIG. 13B. 14B to 14E are the expansions of the time slots P, D, W, and R of the normal bus exit envelopes 501, 502, 503, 504, or 505. FIG.

The bus 302 includes 36 unidirectional lines for performing bus intercommunication functions between all 16 ports as shown in fifteenth. The signal transmitted from the receiving logic 304 of the module to the bus 302 is "data" (16 bits each line), "destination address" (4 bits per line), "destination channel address" ( 5 bits per line), "data valid" (1 bit), "select" (1 bit), and "mode" (1 bit). (The signals received from bus 302 are "Selected Channel" (5 bits per line), "Acknowledge" (1 bit), "Module Busy" (1 bit). "FIFO Data from FIFO Buffer 402" According to the contents of the " receive control RAM " 404 addressed by the " word and channel number output of the FIFO 402 ", various signals are transmitted to the bus 302, received from the bus 302, and enabled. Various words are recorded in the "port", "channel", and "receive control RAM" of the reception logic 304 for the specified port. The "SET WRITE ACTIVITYLINE" of the sub 302 determines the above decision. It is a special function line that surpasses the occurrence of the function.

During the time slot P shown by (1) in FIG. 14B, the currently enabled reception logic 304 transmits the destination transmission logic number to the bus 302, and the " data valid " Apply appropriate signals such as "select", "mode", "module busy", etc. In front of the clock shown in FIG. 14B (2), the transmission logic 306 for all 16 ports puts the state of the bus line into a register associated with the decode port number circuit 420 and the transmission control 424. In the time slot D shown in (3) of Fig. 14C, the reception logic of the enabled port is loaded with information on the "data line" and the destination channel address line. In diagnostics, this information is passed to a buffer register associated with data RAM 422. During the time slot W shown in (5) of Figure 14d, it is represented by four bits on the "Destination Port Address Line" generated during time slot P. If the port number matches the port identification coat of a particular port that is unique for each port, the operation takes place in the port's transmission logic.

The operation may be a write to the data RAM 422 of the port, or may be in response to a "select" command. Also, during the time slot W, the fitted value of the selected channel number is connected from the first free channel search circuit 414 to the " selected channel number line " if the acknowledgment signal value (logical 1 or 0) is properly calculated.

"Nac" only indicates the absence of an acknowledgment signal. In the time slot R shown in (6) of Fig. 14E, the destination port transmission logic responds to the " selected channel " number and the acknowledgment line. Enabled receive logic appears in Fig. 14A (7) and then communicates the state of this line to a register associated with Receive Control 466 at the front of the clock, and after some time has elapsed in Fig. 8E (14). It updates its own channel and receiver RAMs 410, 408, and 406, respectively.

The "nak" channel number received by the "nak" receiver 416 in the receive logic of a particular port sets the reject bit in the receive logic of the port all day at the address specified by the received "nak" channel number. . That is, the "nak" of channel 16 may be decoded, for example, into "nak" channel 7. The next receiving logic that has set up a path to channel 7 attempts to write to channel 7. At the moment, it will point out that no acknowledgment signal has been obtained and that the channel to channel 7 has been "naked." The "naked" search circuit 418 then pulses the number of the channel that has been "naked" from the transmission of channel 16. Will be exported to.

Delays through the network are automatically minimized by the first free channel search technique. The first free channel search circuit 414 continuously determines whether the lowest channel number higher than the current output channel number connected to the serial data on the PCM line 300 in the " busy bit " of the transmission control RAM 424 is an idle channel. Find. While the present invention has been described in connection with the above embodiments, it will be understood that additional embodiments, modifications, and applications that can be made by those skilled in the art without departing from the spirit of the present invention are included within the scope of the present invention. will be.

Claims (1)

To ensure that one terminal of a terminal group is connected to another terminal, switching of the terminal group by selectively interconnecting multiple terminal groups representing subscribers or trunk lines through a digital switching network having an access switching stage and one or more other switching stages. A distribution control digital switching system for controlling a power supply; A first group of data processors (A ₀ -A ₇ ) comprising memory and logic control circuitry to operate to provide a first set of pull processing functions for connecting a plurality of terminal groups to subscriber terminals in the same group with each other; A second set of pooling processes coupled to this first group of data processors A ₀ -A ₇ to slow the subscribers of different groups to each other, independent of the functions provided by this first group of data processors. A second group of data processors B ₀ -B ₁ each comprising a memory and a control circuit to provide a function to one or more terminal groups in pairs; The first (A ₀ -A ₇ ) and first described above by means of one or more multiplexed transmission paths 26, 28 to connect subscriber terminals in terminal groups of different terminal units 12, 14 ..., 16 to each other. As it is coupled to two groups of processors (B ₀ -B ₁ ), the communication data and passage selection control signals are transmitted in the form of frames containing a plurality of channels of these data via these transmission paths 26 and 28. Thus, the above-mentioned path selection control signals flow before the data on the multiplexed transmission path in the same channel to establish a data processor communication path of the first and second groups, and transmit on the channel designated by this path selection control signal. A distributed control digital switching system comprising a digital network (10) for selectively interconnecting the aforementioned subscriber terminals via furnaces (26, 28).

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