GB1243464A - Stored-programme controlled data-processing systems - Google Patents

Abstract

1,243,464. Digital data processor. PLESSEY TELECOMMUNICATIONS RESEARCH Ltd. 9 Jan., 1970 [17 Jan., 1969], No. 2913/69. Heading G4A. [Also in Divisions H3-H5] Control of a system, such as a reed-relay trunk switching network, is effected by a number of asynchronously operating data processors which are functionally interchangeable and each of which operates in respect of a fraction of the programmes required for operation of the total system, a group of data transmission highways being provided so that processor to processor and processor to peripheral data transmission can be effected as and when required by seizure of an idle one of the highways. As shown the switching network SN is controlled by markers M and has incoming and outgoing junctions ILE, OLE served by scanners IS and OS. The data processors P1 to PN receive data from and send data to the peripheral markers and scanners by way of three highways H1, H2, H3, which form a closed loop. Each processor and peripheral has access to the highways by means of a highway station such as HSP4 comprising a buffer store HDB and a so-called logic station CL1, CL2, CL3, for each highway. Each highway is a 15-conductor cable, 10 carrying data; 4 carrying a code to indicate the type of data, and 1 being used as a gating sign . Data circulates in an anti-clockwise direction and in their idle conditions the logic stations CL provide continuity for their respective highways. An idle highway is characterized by a particular code present in the highway. The processors P1 to PN are of preferably identical structure, each processor being loaded with one or more programmes up to a maximum of 16. The presence of a particular programme is advertized in the associated highway station by means of a so-called symbolic address so that demands for service may be routed to an appropriate processor. The processors are also given hardware addresses which are necessary in fault location and programme loading routine. Highway protocol.-The example of processor P4 sending an instruction to a marker M is given. The highway station HSP4 in response to a processor request seizes a free highway and breaks the highway loop so that its ends are terminated on the buffer HDB. The processor then sends its priority status as a code round the highway in order to sort out concurrent seizure situations. If the priority code is received back from round the loop the channel is deemed clear and available. If a higher priority code is received from another seizure attempt the processor withdraws and applies for seizure of an idle highway afresh. Given a clear highway the processor sends the identity of the wanted peripheral which picks up its own code and responds to break the highway loop and send back its own address together with a free or busy code. If the peripheral is busy the processor retires and attempts a connection at a later time. If the peripheral is free the returned address is checked and a code is sent to determine the mode of operation of the peripheral. Given a satisfactory reversion of this data a series of data characters are sent to build up a data block. The peripheral on its own judgment reverts an end-of-block code the correct positioning of which is tested by the processor before it retires having completed the instruction. Service peripherals.-Bulk data storage is provided by tape, drum, and core stores MTS, DS and CS which a tape reader, output printer, and control console TR, OP, and MC are also provided. Each of these facilities has a corresponding highway station for data transmission over the highway loops. To effect data retrieval from bulk storage for purposes such as class-ofservice codes, route translation codes, or switching network map data, an access instruction is sent followed by a transmit instruction with the requesting processor changing over to a receive mode. Fault routines.-Each processor has a fault response based on a hardware micro-programme. Where a process deems itself faulty in the pursuit of a programme the symbolic address advertizing this programme on the highways is withdrawn. Processor P1 is held spare to take-up functions that are withdrawn from faulty processors, processors P2 and P3 being employed as duplicated supervisory processors to effect recording among the processors. A clean duplicate of all programmes is available in the tape store MTS whereby the spare processor P1 or any other spare capacity may be called in to replace lost programme capacity. If necessary programmes of low priority may be withdrawn to make space for programmes being relocated. Alternative highway configurations.-In place of the single loop of highways common to all processors and peripherals two loops may be provided, the first loop of three highways embracing all the network peripherals and the processors while a second loop of seven highways embraces the service peripherals and the processors, Fig. 2, not shown. In this arrangement processor to processor transmissions have a choice of ten highways . The processor network peripheral highway loops may be comprised of two groups of three, each group serving a set of scanners and markers corresponding to a particular section of the network or corresponding to a separate network, Fig. 3, not shown. The processors may be duplicated, a first set of processors may be duplicated, a first set of processors being looped to a first set of network k peripherals, the second set of processors being separately looped to a second set of network peripherals and all the processors in both sets being looped by a yet further group of highways to a common set of service peripherals, Fig. 4, not shown. Instead of being placed in the highway loop common to both sets of processors the common service peripherals may be embraced by separate loops to each set of processors, Fig. 5, not shown.