GB1243464A - Stored-programme controlled data-processing systems - Google Patents

Stored-programme controlled data-processing systems

Info

Publication number
GB1243464A
GB1243464A GB291369A GB291369A GB1243464A GB 1243464 A GB1243464 A GB 1243464A GB 291369 A GB291369 A GB 291369A GB 291369 A GB291369 A GB 291369A GB 1243464 A GB1243464 A GB 1243464A
Authority
GB
Grant status
Application
Patent type
Prior art keywords
processor
highway
processors
data
highways
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB291369A
Inventor
John Michael Cotton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PLESSEY TELECOMM RES Ltd
Plessey Telecommunications Research Ltd
Original Assignee
PLESSEY TELECOMM RES Ltd
Plessey Telecommunications Research Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023Failover techniques
    • G06F11/2025Failover techniques using centralised failover control functionality
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023Failover techniques
    • G06F11/2028Failover techniques eliminating a faulty processor or activating a spare
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2046Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share persistent storage
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455Multi-processor, parallelism, distributed systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space

Abstract

1,243,464. Digital data processor. PLESSEY TELECOMMUNICATIONS RESEARCH Ltd. 9 Jan., 1970 [17 Jan., 1969], No. 2913/69. Heading G4A. [Also in Divisions H3-H5] Control of a system, such as a reed-relay trunk switching network, is effected by a number of asynchronously operating data processors which are functionally interchangeable and each of which operates in respect of a fraction of the programmes required for operation of the total system, a group of data transmission highways being provided so that processor to processor and processor to peripheral data transmission can be effected as and when required by seizure of an idle one of the highways. As shown the switching network SN is controlled by markers M and has incoming and outgoing junctions ILE, OLE served by scanners IS and OS. The data processors P1 to PN receive data from and send data to the peripheral markers and scanners by way of three highways H1, H2, H3, which form a closed loop. Each processor and peripheral has access to the highways by means of a highway station such as HSP4 comprising a buffer store HDB and a so-called logic station CL1, CL2, CL3, for each highway. Each highway is a 15-conductor cable, 10 carrying data; 4 carrying a code to indicate the type of data, and 1 being used as a gating sign . Data circulates in an anti-clockwise direction and in their idle conditions the logic stations CL provide continuity for their respective highways. An idle highway is characterized by a particular code present in the highway. The processors P1 to PN are of preferably identical structure, each processor being loaded with one or more programmes up to a maximum of 16. The presence of a particular programme is advertized in the associated highway station by means of a so-called symbolic address so that demands for service may be routed to an appropriate processor. The processors are also given hardware addresses which are necessary in fault location and programme loading routine. Highway protocol.-The example of processor P4 sending an instruction to a marker M is given. The highway station HSP4 in response to a processor request seizes a free highway and breaks the highway loop so that its ends are terminated on the buffer HDB. The processor then sends its priority status as a code round the highway in order to sort out concurrent seizure situations. If the priority code is received back from round the loop the channel is deemed clear and available. If a higher priority code is received from another seizure attempt the processor withdraws and applies for seizure of an idle highway afresh. Given a clear highway the processor sends the identity of the wanted peripheral which picks up its own code and responds to break the highway loop and send back its own address together with a free or busy code. If the peripheral is busy the processor retires and attempts a connection at a later time. If the peripheral is free the returned address is checked and a code is sent to determine the mode of operation of the peripheral. Given a satisfactory reversion of this data a series of data characters are sent to build up a data block. The peripheral on its own judgment reverts an end-of-block code the correct positioning of which is tested by the processor before it retires having completed the instruction. Service peripherals.-Bulk data storage is provided by tape, drum, and core stores MTS, DS and CS which a tape reader, output printer, and control console TR, OP, and MC are also provided. Each of these facilities has a corresponding highway station for data transmission over the highway loops. To effect data retrieval from bulk storage for purposes such as class-ofservice codes, route translation codes, or switching network map data, an access instruction is sent followed by a transmit instruction with the requesting processor changing over to a receive mode. Fault routines.-Each processor has a fault response based on a hardware micro-programme. Where a process deems itself faulty in the pursuit of a programme the symbolic address advertizing this programme on the highways is withdrawn. Processor P1 is held spare to take-up functions that are withdrawn from faulty processors, processors P2 and P3 being employed as duplicated supervisory processors to effect recording among the processors. A clean duplicate of all programmes is available in the tape store MTS whereby the spare processor P1 or any other spare capacity may be called in to replace lost programme capacity. If necessary programmes of low priority may be withdrawn to make space for programmes being relocated. Alternative highway configurations.-In place of the single loop of highways common to all processors and peripherals two loops may be provided, the first loop of three highways embracing all the network peripherals and the processors while a second loop of seven highways embraces the service peripherals and the processors, Fig. 2, not shown. In this arrangement processor to processor transmissions have a choice of ten highways . The processor network peripheral highway loops may be comprised of two groups of three, each group serving a set of scanners and markers corresponding to a particular section of the network or corresponding to a separate network, Fig. 3, not shown. The processors may be duplicated, a first set of processors may be duplicated, a first set of processors being looped to a first set of network k peripherals, the second set of processors being separately looped to a second set of network peripherals and all the processors in both sets being looped by a yet further group of highways to a common set of service peripherals, Fig. 4, not shown. Instead of being placed in the highway loop common to both sets of processors the common service peripherals may be embraced by separate loops to each set of processors, Fig. 5, not shown.
GB291369A 1969-01-17 1969-01-17 Stored-programme controlled data-processing systems Expired GB1243464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB291369A GB1243464A (en) 1969-01-17 1969-01-17 Stored-programme controlled data-processing systems

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB291369A GB1243464A (en) 1969-01-17 1969-01-17 Stored-programme controlled data-processing systems
FR7001339A FR2028517A1 (en) 1969-01-17 1970-01-15
DE19702001832 DE2001832C3 (en) 1969-01-17 1970-01-16
NL7000738A NL166169C (en) 1969-01-17 1970-01-19 A system for processing data in accordance with an up-beaten progamme.

Publications (1)

Publication Number Publication Date
GB1243464A true true GB1243464A (en) 1971-08-18

Family

ID=9748435

Family Applications (1)

Application Number Title Priority Date Filing Date
GB291369A Expired GB1243464A (en) 1969-01-17 1969-01-17 Stored-programme controlled data-processing systems

Country Status (4)

Country Link
DE (1) DE2001832C3 (en)
FR (1) FR2028517A1 (en)
GB (1) GB1243464A (en)
NL (1) NL166169C (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2741379A1 (en) * 1977-09-14 1979-03-15 Siemens Ag computer system
EP0062463A1 (en) * 1981-03-31 1982-10-13 British Telecommunications Computer or processor control systems
US4757497A (en) * 1986-12-03 1988-07-12 Lan-Tel, Inc. Local area voice/data communications and switching system
US5544163A (en) * 1994-03-08 1996-08-06 Excel, Inc. Expandable telecommunications system
GB2328352A (en) * 1997-08-12 1999-02-17 Lucent Technologies Uk Limited Redundant communication network
US6002683A (en) * 1994-03-08 1999-12-14 Excel Switching Corporation Bridge for expandable telecommunications system
US6278718B1 (en) 1996-08-29 2001-08-21 Excel, Inc. Distributed network synchronization system

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4032899A (en) * 1975-05-05 1977-06-28 International Business Machines Corporation Apparatus and method for switching of data
GB2125254B (en) * 1982-07-30 1985-10-23 Plessey Company The Telecommunications digital switchblock
FR2538662B1 (en) * 1982-12-22 1988-04-29 Trt Telecom Radio Electr telephone switching system
GB2143403B (en) * 1983-07-15 1986-10-29 Standard Telephones Cables Ltd Telecommunication exchange
DE3334792A1 (en) * 1983-09-26 1984-11-08 Siemens Ag Central control unit of a switching system in particular automatic telephone-switching system
FR2591777B1 (en) * 1985-12-13 1991-03-15 Cimsa Sintra Computerized network of high operating safety and control method using such network
JPH10506483A (en) * 1994-06-10 1998-06-23 テキサス・マイクロ・インコーポレーテッド Main memory system and the check point for the protocol for the fault-tolerant computer system
US5737514A (en) * 1995-11-29 1998-04-07 Texas Micro, Inc. Remote checkpoint memory system and protocol for fault-tolerant computer system
US5864657A (en) * 1995-11-29 1999-01-26 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2741379A1 (en) * 1977-09-14 1979-03-15 Siemens Ag computer system
EP0062463A1 (en) * 1981-03-31 1982-10-13 British Telecommunications Computer or processor control systems
US4757497A (en) * 1986-12-03 1988-07-12 Lan-Tel, Inc. Local area voice/data communications and switching system
US5544163A (en) * 1994-03-08 1996-08-06 Excel, Inc. Expandable telecommunications system
US5737320A (en) * 1994-03-08 1998-04-07 Excel Switching Corporation Methods of communication for expandable telecommunication system
US5864551A (en) * 1994-03-08 1999-01-26 Excel Switching Corporation Method of operating a bridge for expandable telecommunications system
US6002683A (en) * 1994-03-08 1999-12-14 Excel Switching Corporation Bridge for expandable telecommunications system
US6118779A (en) * 1994-03-08 2000-09-12 Excel Switching Corp. Apparatus and method for interfacing processing resources to a telecommunications switching system
US6522646B1 (en) 1994-03-08 2003-02-18 Excel Switching Co. Expandable telecommunications system
US6278718B1 (en) 1996-08-29 2001-08-21 Excel, Inc. Distributed network synchronization system
GB2328352A (en) * 1997-08-12 1999-02-17 Lucent Technologies Uk Limited Redundant communication network

Also Published As

Publication number Publication date Type
NL166169B (en) 1981-01-15 application
DE2001832B2 (en) 1980-05-29 application
NL7000738A (en) 1970-07-21 application
DE2001832A1 (en) 1970-07-30 application
DE2001832C3 (en) 1981-02-05 grant
FR2028517A1 (en) 1970-10-09 application
NL166169C (en) 1981-06-15 grant

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