FI83139B - FOERFARANDE FOER DRIFT AV ETT I NORMALDRIFTSTID PARALLELLT DRIVET MINNESBLOCKPAR. - Google Patents

Abstract

Method for the operation of a couple (MB3a, MB3b) of memory blocks working in parallel. At least one processor (BP, IOC) reads and writes information into the two blocks (MB3a, MB3b) in a normal operating time with read-write operation, the first block (MB3) respectively storing under one of its addresses the same information as the second block (MB3b) does under the same address. The first and second blocks (MB3a, MB3b) can be switched off in order to block access in a special operating time, at least during reading from said switched-off block (MB3b), in which case only the first block (MB3a) is operated completely in read-write operation. During the special operating time, an address generator (e.g. in IOC1) can systematically produce all the addresses of the blocks (MB3) sequentially, at least in stages. At the end of the special operating time, upon transition to the normal operating time, for the purpose of updating the information to be stored in the switched-off block (MB3b) during writing into the first block (MB3a), the same information is written into the second block under the same address. The address generator gradually supplies all the addresses of the pair (MB3) of blocks, for example during a pause in the read-write operation, the information read out in this process from the first block (MB3a) being written into the second block (MB3b) under the same address. Thereafter, both blocks (MB3) can once again be operated in parallel. <IMAGE>

Description

1 83139

A method for using a pair of memory blocks used in parallel during normal operation

The invention starts from the method according to the preamble of claim 1.

Methods according to the preamble of claim 1, in which the connections, including the memory blocks, are doubled for safety reasons and which are used in parallel, e.g. read and write by means of one or more processors, are known to the person skilled in the art, cf. eg electronics, oak. 27 1983, pp. 103-105. Generally, such processors or .vast, calculators that do not have their own local memories or have their own local memories are connected together with a pair of memory blocks or several such pairs of memory blocks to a bus system common to them all.

The method according to the invention has been developed in particular for a central control unit of a very large call transfer system, which has to perform a very large number of transfer functions simultaneously or quasi-simulantly, such as subscriber monitoring etc. Such multiprocessor central control units need not only to have a high processing capacity but also a very high availability, i.e. they should only be out of operation for a maximum of minutes or seconds per year, so they should also deal with local disturbances reliably or, if necessary, they should recover on their own. Both processing capacities and high availability, as well as hardware input savings, are known per se for such multiprocessor central control units. However, the invention can in principle be used in general in all the methods defined in the preamble of claim 1.

2 83139

It is an object of the invention to further develop the method set out in the preamble of claim 1 so that - the time input for terminating the initially disturbed operation of the second block, namely updating the information stored in the (re) switched second block, is as small as possible, and - this updating can be performed during the operation of the processors and the first block automatically and without inhibiting the operation of the first block.

This task is solved by the measures set out in the claim.

The invention is explained in more detail by means of an embodiment shown in the figure.

The figure shows a central control unit in which twelve processors BP / CP and several processors ioc operate via the bus system B: CMY together with the main memory CMY. As such, all processors BP / CP can be similar in structure and, in principle, they can also handle all the same task complexes. With different reference marks BP / CP

however, it is shown that different structures and / or task complexes are permissible per se - the method according to the invention can also be used.

The BP / CP / IOC / IOP processors thus perform, at least when sufficient connection requirements exist, the individual steps of the various transmission, security and / or operational functions for all current connections, quasi-simulantly. These details will be explained later. Aspects that relate closely to an essential part of the invention will first be explained here.

The invention distinguishes between a normal operating time and a special operating time. In normal operation, both blocks of each pair of memory blocks, li 3 83139 in this case MB3a / MB3b, e.g. MB3a and MB3b are used microsynchronously in parallel, whereby four such pairs of memory blocks MBO ... MB3 are placed in the main memory CMY, each pair can be controlled independently from three regarding. Thus, at least one of the processors BP, CP, IOC, IOP reads information from both blocks of the loco pair, e.g. BM3a, MB3b, or writes information to both blocks, e.g. MB3a, at the addresses provided to it, possibly recoded during this normal operation. MB3b.

During this normal operation period, so that, in the absence of any interference, the first of the blocks, e.g. MB3a, at one of its addresses in each case stores the same information as the second block, i.e. in this case MB3b, at the same address.

To increase operational reliability from both blocks, cf. MB3a, MB3b The information read during this normal operation is compared with each other - and / or there is a continuous self-check of each block MB3a, MB3b, e.g. by means of an EDC code. If such checks reveal an error in the read information, the block, e.g., MB3b, from which the error originates is truncated. For this purpose, both the first and second blocks can be disconnected separately from the respective access-seeking processor, e.g.

CPx, to prevent access to the currently truncated block, referred to herein as the "second" block, cf. MB3b, at least during this so-called special operation time, to prevent reading from this truncated second block MB3b; - in which case, during this special period of operation, the first block alone, cf.

MB3a, is used entirely in read-write operation, so that the first block MB3a then also alone maintains read-write operation and write operation for the respective processor, e.g. CPx.

The invention further uses an address generator, which can be located e.g. in the IO processor I0C1 and which can systematically produce, at least in stages, all the addresses of the blocks, i.e. also the addresses of the blocks MB3a / MB3b, during this special operation period.

4 83139

The invention relates in particular to the truncated second block, cf. MB3b, updating the stored data before switching from special operation to normal operation again. Namely, according to the invention, in particular, this second block MB3b is used initially at the end of the special operating time before the transition to the normal operating time for updating the information stored therein in a special way. Namely, even before this transition, during normal writing to the first block MB3a, the same information is already written to the second block MB3b with the same address. Further before the transition - e.g., preferably during one or more rather pauses in read-write operation, where the processor BP or CP / IOC / IOP is not written to the first block MB3a and is not read from this first block MB3a, especially in that processor BP / CP / IOC / For further processing - the address developer is started so that it successively produces the addresses of the first and thus the second block MB3a, MB3b to the first and second blocks MB3a, MB3b, in which case the information read from the first block MB3a is then written to the second block MB3b.

In this way, the memory contents of the second block MB3b are updated - again or for the first time - as soon as all the addresses of the block pair MB3 have been provided by the address developer, i. then all information is identical in all blocks of the address MB3. Thus, normal operation can now begin - again or for the first time - i.e. both blocks of the MB3 can be used for both reading and writing - again or for the first time - in parallel.

The details of the example shown in the figure are explained in more detail below. It schematically shows a multiprocessor-central control unit of a relay system, in which processors BP, CP, IOC communicate via main bus system CM: CMY with main memory CMY. Bus systems that allow different processors or counters to optionally access the main memory connected to them, cf. CMY, or counters, to its memory banks by means of MB arbitration devices (Arbitern) are known per se in various variations. They also have very 5,833,139 comfortable, versatile, highly secure bus systems with dual busses and very high availability, cf. e.g. DE application publication 33 28 405. The bus system is then often doubled for safety reasons, also in the example shown in this figure, cf. B: CMYO and B: CMY1; possibly also the processors BP / CP / IOC have been doubled. In the example shown in the figure, each processor BP / CP contains, in addition to the actual, otherwise similarly doubled, processor unit PU, preferably in each case also one more own local processor memory LMY. The IOC processors have eight outputs 0-7 with local buses B: IOC, through which they communicate with the IOPs of the IO units and the MBGs of the peripheral units of the call transfer system, e.g., control group controls, switching field, voice generators, etc. Namely, in most cases, these peripheral units MBG directly or indirectly affect the lines of the transmission network, e.g. in the framework of path searches, switching, signaling, etc. These peripheral units MBG have been doubled here as well, cf. wire cruises. In the example shown, they each have their own IO units, cf. IOP: MB. Other such IO units are connected to local buses B: IOC, cf. IOPs, although connected to other such peripherals in each case, but which are no longer shown in the figure for the sake of clarity.

These IO units IOP «MB ... IOP or equivalent, their local buses B: I0C are connected via the IOC of the IO processors, cf. I0C0, I0C1, to bus system B: CMY. The dots in the figure show that still other such IO processors IOC can be provided, especially in very large relay systems.

Peripherals, cf. MBG, can in each case be connected to different processors BP / CP, depending on the case in a differently distributed manner, and / or they can also be connected in accordance with the invention to the main memory CMY or, respectively, to the MB parts of its banks. Through these connections, notifications and / or inquiries can be made about the peripheral units MBG and notifications and / or inquiries to such peripheral units MBG during normal operating hours and special operating times. In this case, the relay messages and / or queries of the slave MBG are preferably distributed autonomously via the IOC of the connected IO processors per call, so that the respective IO IOP, when it receives a call from the slave MBG, distributes one of the processors BPG or CPG to this calling slave. resp., main memory CMY or resp. MB part, or vast, allows to be distributed via the bus system B: CMY. This allocation of the special processor and / or the special part CMY / MB of the main memory to the peripheral unit MBG in question is then stored in a further data field, in which case this data field can also be placed in the bank MBG of the main memory CMY. With these recordings in the data field, in particular with the contribution of the IOP of the IO in question, the subsequent messages or queries of the MBG of the associated slave following this call can be sent to the same CP or CPU shared above. MB in order to continue mediation functions and / or registrations. Such an autonomous distribution per call allows the BP / CP of all processors to be almost evenly loaded with forwarding functions - at least this distribution can then be controlled according to the current CP load of those processors, so that subsequent messages and / or queries can be processed really quickly by one of the processors. still enough spare capacity. The selection or division of the processors BP / CP to perform the functions - especially those triggered by the call of the peripheral unit - can then take place cyclically, however, if one of the processors CP / BP is overloaded, this processor is skipped in the cyclic selection method. With such a cyclic division of tasks or calls, a largely uniform processor load can be achieved for these processors. Fast, usually all processors have at least a certain part load. Also, an error, or an attempt to malfunction, is always detected quickly in the processors, so that the operational functions, which are preferably performed on one of the BP processors, allow the faulty processor in question to be temporarily disabled and skipped in each case I; 7 83139 in connection with cyclic partitioning, in which case self-correction of the central control unit - possibly partially - can also be carried out, e.g. by means of replacement circuits and saving of memory contents.

The IOC structure of the individual elements of this multiprocessor calculator, e.g. processors BP and CP, banks MB or vast, CMY, 10 processors, which may also have, for example, different numbers of local system buses B: I0C (cf. IO processor I0C0 outputs 0 .. .7), may in each case be arbitrary in the context of the invention. They only have to match the B: CMY interface of the selected bus system, or they have to match its structure or mode of operation when such a B: CMY bus system is connected.

The peripheral units MBG shown in the figure can likewise have an arbitrary structure per se with arbitrary functions. They can be both technical units or special transmission sub-functions of ancillary units that perform a larger complex of different functions. Despite the high availability required, it is usually sufficient for these peripherals or counter units to be connected to the IOC processors IOC via non-duplicated, i.e. simple IO units I0P: MB ... I0P, when these peripherals, cf. MBG, is connected independently via cruises, cf. pattern. These IO units IOPs and / or their associated IO processors IOC may independently have additional inspection functions to complicate uncontrolled access to BP / CP / IOC processors and CMY / MB main memory accesses based on errors.

In the currently developed example according to the figure, the BP / CP processors use, for example, SAB 80286 microprocessors, which in each case have the physical address space of their local memories LMY 16 MB. In the IOC processors, for example, 8086 modules have been used. In order to improve error detection, the processors are preferably doubled β 83139 and can then only be switched off in pairs.

In the example shown in the figure, as already mentioned above, the main memory CMY connected to the bus system B: CMY is formed of four different banks, MB0 ... MB3, which are doubled in each case for security reasons. In principle, all processors BP / CP / IOC / IOP can have access via the bus system B: CMY to all data in the main memory CMY or, in contrast, to all data in its banks MB, if - e.g. by restricting addresses - the access is not restricted.

The special processor multiprocessor presented by this multiprocessor central control unit requires, normally simultaneously, a statistically arbitrarily distributed arbitrary number of processors BP / CP / IOC to access the main memory CMY or, in most cases, its various block pairs MB. In this case, the buses of the bus system B: CMY are allocated alternately to these different processors in each case, e.g. has access to the main memory CMY / MB connected to bus system B: CMY in succession or equivalent, alternately in both normal and special operation according to bus priority (Arbitrierungen) or equivalent, according to bus system B: CMY divisions - in which case the processors BP / CP may also be arranged can also communicate indirectly with each other via main memory CMY / MB during both normal and special operating hours.

Typically, each of these processors in question communicates with another area in the main memory CMY at a time. In order to reduce the latency of these processors, the main memory CMY in the example shown contains four memory banks MB, each with its own memory control. This own memory control directs its memory bank MB at a time, regardless of the MB memory controls of other memory banks. In this way, these four memory banks can be used simultaneously during both normal operation and special operation.

ii 9 83139

Furthermore, in the bus system B: CMY, according to the time multiplex principle, the time frames can be provided with time slots or time channels, whereby one or more time channels are fixedly arranged for each memory control, and whereby BP, CP, IOC in each case time slots or vast, time channels. Thus, the duration of the shared time slots may be much shorter than the duration of the memory cycle. For this reason, although only a single doubled bus system B: CMY is provided in this further development, the information flow, however, is quasi-simultaneous due to the time-multiplex operation, i.e. well condensed, which reduces the hardware input of the bus system compared to the respective bus system per MB of memory bank.

Thus, also in this further development, the write cycles can be further driven autonomously by the bus system B: CMY when receiving information at the processor-bus system interface or after this reception. Immediate acknowledgment to the communicating processor allows it to proceed immediately, even if that write cycle to the database has not yet ended. This allows for a very high multiprocessing capacity of the Sori central control unit.

According to a further development of the invention, the read cycles to the bank MB can take place so nested that the retransmission of the read data can take place simultaneously with respect to the next read access address transfer. This further significantly improves the capacity or vast processing speed.

‘Normally, both buses of bus system B: CMY operate in parallel and process advanced information. Bus Arlitrierung is performed before the time slot is allocated to the BP / CP / IOC / IOP processors to improve the performance of the bus system B: CMY. The priorities of the bus priority Arbiter can be PROM programmable. The MB as uniform a load as possible for all banks can be achieved, e.g., by arranging an address for these banks via address bits lower than MB, e.g. in an 8-byte overlap raster.

Various other details of this example are also presented in Finnish patent applications 843755, 843756, 843758, 843759 and 843760.

Tue

Claims (1)

A method for using a pair of memory blocks (MB3a, MB3b) used in parallel during normal operation, i.e. the first {MB3a) and the second block (MB3b), in which - at least one processor (BP, CP, IOC) is arranged, which reads the , possibly with recoded addresses during normal operation with read-write operation information from both blocks (MB3a, MB3b) and writes to both blocks (MB3a, MB3b), during which normal first of both blocks stores the same information at one of its addresses at the same time as the other block - microsynchronously comparing the information read from both blocks (MB3a, MB3b) during normal operation and / or checking each block (MB3a, MB3b) by continuous self-checking, eg by means of an EDC code, - both the first and second blocks (MB3a, MB3b) can be truncated separately the process of access in question (e.g., CPx) to prevent access to the currently truncated block, referred to herein as the second block (MB3b), special operation. at least when reading from this truncated second block (MB3b), in which case the first block (MB3a) is then used alone in full read-write operation, so that the first block (MB3a) can also alone maintain the respective read-write and write operation of the respective processor ( e.g. for CPx) and having an address developer (e.g. in IOCl) which can systematically sequentially, at least in stages, all the addresses of the blocks (MB3) during various operations, in particular several such blocks of a relay system, e.g. a call transfer system multiprocessor control unit (MB3) ), characterized in that first at the end of the special operation period before the normal operation time for updating the information to be stored in the second block (MB3b) - during writing to the first block (MB3a) i2 831 39 the same information is written to another block at the same address, during a special operation, for example during one or more pauses in a read-write operation, from the processor or, respectively, the processors (CP; IOC) is not written to the first block (MB3a) for storage and is not read from this first block (MB3a) for further processing in that processor (CP, IOC), - the address developer (in IOCl) generates all the addresses of the first block and thus the second block (MB3a, MB3b) in succession to the first and second blocks (MB3a, MB3b), in which case the information read from the first block (MB3a) is then written to the second block (MB3b) at the same address, and after the address developer (in the IOC) has generated all the addresses and after all the information is identical in all addresses in both blocks (MB3), from the beginning of the (new) normal operating time - both blocks (MB3) are used (again) in parallel. For example, drift av et i en normaldriftstid parallell-Drivet minnesblockpar (MB3a, MB3b), alltsä ett första (MB3a) och ett andra (MB3b) blocket, däri - det har anordnats ätminstone en processor (BP, CP, IOC) som avläser under in the case of a block, the address of the addressee in the normal block of information with the block block (MB3a, MB3b) and in the case of the block block (MB3a, MB3b), the color of the standard block of the block block (MB3a, MB3b) you address samma information som det andra blocket under samma adress, - det genomförs mikrosynkron jämförelse av de i bäda blocken (MB3a, MB3b) i normaldriftstiden avlästa informat-tioner och / eller varje block prövas med ständig självpröv-Ning t.ex. medelst EDC-koden, - bäde det första blocket och det andra blocket (MB3a, MB3b) är fränkopplingsbara av ätkomst av den ifrägavarande accesvilliga processorn (t.ex. CPx) account det i3 831 39 fränkopplade blocket, som Kallas här blocket, under special driftstiden - ätminstone vid läsning frän detta fränkopplade block (MB3b) - varvid det första blocket (MB3a) .ex. CPx), och - en adressgenerator (t.ex. i I0C1) kan under specialdriftstiden generera samtaliga adresser hos blocken (MB3) system-tiskt efter varandra, ätminstone i stagesper, speciellt fért ett huvudminne (CMY) av en multiprocessor- central operating system, special communication system, special telephone system, flashing key and remote control block (MB3), switching from image to connection aldriftstiden före övergäng account normal-driftstiden för aktalisering av de informationer som skall lagras i det andra blocket (MB3b) - vid inskrivandet i det första blocket (MB3a) under or under the pause of the source-scratch-drift, in the case of the processor or the process sorter (CP, IOC) of the incremental block (MB3a) for the test or in the field of the block (MB3a) processorn, - adressgeneratorn (i I0C1) levererar i rad samtliga adresser hos det första och härvid ocksä det andra blocket (MB3a, MB3b) account det första och andra blocket (MB3a, MB3b), varvid de härvid frän det första blocket (MB3a) avlä the information is stored under the same address as the block and the block (MB3b), and after the address (i0C1) is set to the same address as the block and the information is indented under the address if the block is blocked (MB3), free blocken (MB3) drives (yes) parallel.