GB2086624A - Multi processor computer system - Google Patents

Abstract

Prior art multiprocessor systems either employ a single set of common resources that are shared by all the processors, or employ a plurality of resources, each of which are dedicated to a particular processor. In this latter situation, serial intercommunication links requiring both the transmitting and the receiving processors to participate are used to transmit data between processors. The subject processor interconnection system interconnects n independent processors (209-1 to 209-n), each of which has associated therewith a plurality of resources (205-i to 207-i), which resources are connected to the processor by a local bus (214-1 to 214-n), such that any processor in the system has direct access to any system resource even though such a resource may be associated with another processor.

Description

SPECIFICATION Multi processor computer system This invention relates to multiprocessor computer systems.

Prior art multiprocessor systems either employ a single set of common resources that are shared by all the processors, or employ a plurality of resources, each of which are dedicated to a particular processor. In this latter situation, serial intercommunication links are typically used to transmit data between processors. Both the transmitting and the receiving processors are required to participate in this data transfer and this unnecessarily burdens the two processors.

The claimed multiprocessor computer system overcomes this problem by interconnecting n independent processors such that the resources associated with each processor can be directly accessed by any other processor in t#he system. Each processor has a local bus which connects the processor to its associated resources, which resources may be memory devices, I/D ports, serial communication devices, etc.

The system uses a global bus to interconnect all the processors in the system.

In a preferred embodiment, each processor generates a virtual address when requesting access to a resource and a memory management circuit associated with the processor translates this virtual address into an actual hardware resource address. If the resource requested is associated with another processor, the processor interconnection system directly connects the requesting processor, via the global bus, to the local bus to which the resource requested is connected. Thus, each processor can directly access all resources in this multiprocessing environment.

The preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings.

in which: Figure 1 illustrates the preferred embodiment of the processor interconnection system in block diagram form; Figure 2 illustrates the details of a typical Processor-Memory-l nterface Module shown in Fig. 1; and Figures 3 and 4 illustrate trypical applications of the subject system.

The disclosed invention comprises a processor interconnection system which can be used to build a multiprocessor computer system from a number of independent or quasi-independent processor-based modules. Each module contains a local data bus that connects the processor to its associated memory and various interface circuits. Each such processormemory-interface (PMI) module, therefore, will be a small computer in its own right. The subject processor interconnection system serves to combine a multitude of these small computers to form an efficient multiprocessing environment.

Such a system is shown in Fig. 1, and includes a priority arbiter module 101, a packet switch network 105, and a number (n) of PMls (102-1 to 102-n). A global data bus 106 interconnects the several PMls. The priority arbiter 101 controls access to global data bus 106 and resolves priority of access to global data bus 106 among the PMls according to any of several conventional formulae. The packet switch network 105 serves as an interface between any pair of serial data links including those from outside of the system as well as those within the PMls. The PMI module is shown in detail in Fig. 2.

Each PMI assembly includes a processor 209-1, global bus access circuits 202-1 to 204-1, 208-1, 215-1 accessible local resources 205-1, 206-1, 207-1, and a local data bus 214-1 which connects local resources 205-1 to 207-1 to global bus 213 via bus connect circuit 202-1 or to processor 209-1 via local buffer 216-1 and memory management circuit 208-1. Only a real time clock 21 2-1 and an interrupt system 210-1 are dedicated solely to processor 209-1 and, therefore, these circuits are not connected to either bus. The global access circuitry within each assembly include a memory management circuit 208-1, bus connection circuit 202-1, and local and global bus arbiters 204-1, 203-1. Other resources contained in each assembly are: one or more memory modules 205-1, one or more parallel input/output ports 206-1, and one or more serial communication interfaces 207-1.Both local and global busses 213 and 214-1 are considered, for illustrating purposes, to carry parallel data.

Bus Selection Although a given processor 209-1 normally uses the resources 205-1 to 207-1 connected to its local bus 214-1, processor 209-1 does not discriminate between buses.

Bus selection is the function of the memory management module 208-1 which works as follows.

When seeking information, processor 209-1 requests the contents of a virtual memory address. The memory management module 208-1 consults an internal address mapping memory which may be realized by either Read Only Memory (ROM) or Random Access Memory (RAM). Whether its contents are fixed or dynamically loaded, however, each mapping memory holds translations of virtual memory addresses to physical memory addresses. Using these data, the memory mangagement circuit 208-1 can accept a virtual memory address from its dedicated processor 209-1 and thereby access the physical memory address sought.

Each processor 209-1 normally executes code located in its local memory 205-1, but it can access any of the memory modules in the system. So data called for by dedicated processor 209-1 outputting a virtual memory address may be either in the local memory 205-1 or in a remote memory 205-i which is its opposite number in another (ith) PMI module 202-i. The first step taken by the local memory management circuitry 208-1 is to find the physical address in its mapping memory that is the translation of the requested virtual memory address.

If the physical address is in the local memory 205-1, memory management 208-1 signals the local/remote arbiter 204-1 via lead SELECT that the processor 209-1 needs access to the local bus 214-1. The local/global selection line, lead SELECT, from memory management 208-1 to the global arbiter 203-1 and the local/remote arbiter 204-1 carries only a single bit, so one or the other is always selected and a change of state calls for a change of bus access. Thus, in the present situation, when the local bus 214-1 is free, the local/remote arbiter 204-1 enables the local buffer 216-1, thereby connecting processor 209-1 to the local bus 214-1 by way of memory mangagement 208-1.

If the physical address generated is of a remote memory 205-i which is the opposite number of 205-1 in module 202-i, memory management 208-1 signals global arbiter 203-1 via lead SELECT that processor 209-1 needs access to global bus 213. The global arbiter 203-1 then notifies the system arbiter 201 via lead REQUEST-1. The system arbiter 201 only decides which of several competing PMls will get the global bus 213 at a given time. When access to the global bus 213 is granted by the system arbiter 201, system arbiter 201 transmits a bus access signal to global arbiter 203-1. In response to this bus access signal, the global arbiter 203-1 enables the global buffer 215 via lead CONTROLG to connect memory management 208-1 to the global bus.Memory management 208-1 then requests the resources of the remote PMI 202-i by placing the hardware address on leads DATAG, which address is placed on global bus 213 by global buffer 215-1.

At the addressed PMI (202-i), the local/ remote arbiter 204-1 receives any request for access from the global bus 213. If the addressed local bus 214-i is free, the local/remote arbiter 204-i is busy, access is denied until it is free. The local/remote arbiter 204-i then grants access to the processor with the highest priority. Any processor can lock the bus it is currently using until completion of a semaphore operation.

Alternative Communication Methods Besides the global and local busses 213 and 214-1, each processor 209-1 has two other communication means. These are the serial communication interface 207-1 and parallel data input/output port 206-1, means that are known in the art and are included here to complete the illustration of this invention. Each local serial communication interface 207-1 connects to a packet switch network 211 which in turn distributes serial data to external serial links and to other serial communication interface modules opposite numbers of 207-1 systemwide. By way of the parallel input/output ports 206-1, the processors can control widely diverse peripheral devices.Thus, the several serial communications interfaces 207-1 combined with the packet switch network 211 comprise a serial data communication subsystem, and the input/output ports 206-1 combined with the dual bus system comprise a parallel data communication subsystem.

Description of a Typical Application Fig. 3 shows a system composed of a number (n) of PMls. The illustrated PMls are connected to function in several ways. One PMI 301 of Fig. 3 connects the system to any of several kinds of system or network: a processor network 308 is the example given in Fig. 3. Another PMI 302 joins a terminal 305 to the system for the operator's use. The program in the memory of PMI 302 arranges the output of the terminal so that it can communicate in the language of the PMls, thus creating a virtual terminal for system use.

So given a programmable memory, PMI 302 would make it possible for the system to use a wide variety of terminals with no change of hardware. The third PMI 303 of Fig. 3 is shown controlling a small set of telephones 306 and the associated telephone switching network 309. Finally, PMI 30n is depicted as an interface between the system and a mass storage unit 307, such as a disc or tape drive.

Since each local processor has dedicated I/O and memory, each PMI amounts to a separate computer and can execute an operating system program. Each PMI also includes a dedicated real time clock and interrupt system connected to the processor so that PMls can be operated in logical parallelism. Because of the speed of the subject dual bus system, this distributed computer system compares quite favorably with a centrally operated system.

An operation can be performed by a system such as the subject system regardless of the limitations of any given component processor.

Assume, for example, that a function were called for by the operator of terminal 305.

PMI 302 would then use the subject dual bus system to call for the required program from mass storage unit 307. According to a protocol given in the program, PMI 302 might send subroutines to the memory modules of several other PMls according to the comput ing power available to each and regardless of their nominal functions. Finally, PMI 302 might order subroutines and supply data as needed until the requested function is performed.

Description of an Alternative Application Fig. 4 reveals a Private Branch Exchange PBX telephone system embodying the subject invention. This embodiment comprises switching network 404 and port circuits 406, 407 controlled by a network PMI 403 and scanner PMls 405, 409 supplemented by feature processing PMI 401, console 402, mass storage devices 412, mass storage control PMI 411 and a maintenance PMI 413. Each PMI in this system is configured as illustrated in Fig. 2 wherein each PMI has a local bus 214-i, processor 209-i, etc.

Ope'rnting features available to the system depend on two things: the configuration of the hardware and the contents of the feature PM l's memory. The system operator uses the console 402 to call up routines from the feature PMI 401. Because of the characteristics of the subject system, features can be added or subtracted by programming the feature PMI and, if necessary, adding or removing PMls.

Port circuits are monitored by the scanner PMI e.g. 405 for such signals as "off-hook or on-hook" from its associated telephones e.g.

408-1 in response to which it can connect or disconnect them from the ports by use of port selection means within the port circuits e.g.

406. A scanner PMI 405 or 409 can then use the dual bus system comprising busses 400 and 214-i (wherein 214-i is the local bus of the scanner) to find from the feature PMI 401 what privileges are assigned to a calling telephone, for example, whether it is allowed to call long distance.

Dialing signals into the switching network 404 from the port circuits 406 or 407 are interpreted by the network PMI 403 and used as data on which to base connection from the calling port to the addressed port. Before connection, the dual bus system may be used by the network PMI 403 to determine from the feature PMI 401 what privileges accrue to the telephone being called.

Requests for data beyond that contained in the memories of the several PMls are referred to the mass storage device 412 by way of the dual bus system and the mass store control PMI 411.

Because it interacts with all system components, a description of maintenance PMI 413 operation will be used to illustrate how the subject embodiment works. In the course of ordinary system operation, maintenance PMI 413 constantly monitors the global bus 213 for commands and responses among the system PMls. Within PMI 413, these messages are routed through bus connect 202-1 (see Fig. 2) and memory management 208-1 to the processor 209-1. Processor 209-1 then compares these commond/response sets read from the global bus to master patterns in memory 205-1. If the messages from the global bus match these ideal patterns, the system is known to be working. Besides these online test routines, the maintenance PMI 413 can interrupt system operation for offline routines.

According to a programmed schedule, for example, it can transmit commands on the global bus 213 to the other PMls. These commands are transmitted by the means described in the paragraphs on bus selection.

Then maintenance PMI 413 can compare the response to these commands to master patterns stored in its memory 205-1. It can also perform any or all of these offline system tests upon orders by an operator on system console 402.

In case of an apparent malfunction, therefore, the operator can invoke the resources of maintenance PMI 413. Such a command is routed from the operator's console 402 through feature PMI 401 and the dual bus structure to maintenance PMI 413. In response to the said command, maintenance PMI 413 selects appropriate tests according to a test procedure in its internal memory and applies them to the system as described above. Having received suspect responses from the system, the maintenance processor 209-1 analyzes the errata to determine the source of the malfunction. It then searches mass storage device 412 by way of mass store control PMI 411 and the dual bus structure for a program designed to deal with the bad component.

Assume, for the sake of illustration, that the processor has failed in PMI 409 and consequently that no connection can be made to half the telephones 410-1 to 410-n in the system. Using the repair program mentioned in the last paragraph, maintenance PMI 413 might isolate defective processor 209-i (see Fig. 2) by instructing memory management module 208-i to pass no data from defective processor 209-i to either bus. Maintenance PMI 413 might then distribute scanning duties among the remaining PMls according to their capacities. The substitute PMls would use the global data bus 213 both to access data from scanner 409's memory 205-i and to command the port circuits 407 via scanner 409's internal input/output port 206-i. Thus, the system would be made temporarily functional although at a slower speed than before.

Because of the high speed of the subject dual bus system, however, the repaired system would run much faster than a similarly repaired distributed system of the previous art.

Having confirmed proper operation of the system, the maintenance PMI 413 would send repair instructions to the operator via the dual bus structure and modules 401 and 402. So programmable maps, privileges, and priorities will have made the temporary repair possible without hardware changes.

If troubleshooting problems cannot be handled within the system, they can be referred to a remote expert. This troubleshooter can connect a terminal or computer to the resources of maintenance module 413 by means of a telephone line to the remote maintenance link 414. The remote maintenance link 414 connects to the system by means of the input/output port 206-1 in the maintenance PMI 413. Thus, all tests and results available to module 413 are available for outside use and module 413 can be programmed from anywhere.

Claims (10)

1. A multiprocessor computer system having n processors, wherein each of said n processors has associated therewith a plurality of resources, wherein said multiprocessor computer system includes: n local bus means associated on a one-to-one basis with said n processors, wherein each of said n local bus means connects said plurality of resources to said associated processor; wherein intercommunication means is connected to all of said n processors, wherein said intercommunication means provides any requesting one of said n processors with direct access to the resources requested by said requesting processor, and wherein said resources requested are associated with another selected one of said n processors.

2. The invention of claim 1, wherein said intercommunication means includes: global bus means connected to all of said n processors for carrying data signals therebetween; priority arbiter means connected to all of said n processors and responsive to the busy/idle status of said global bus means for regulating the access of said requesting processor to said global bus means; and n memory management means associated on a one-to-one basis with each of said n processors, wherein each said memory management means interconnects said associated processor with said global bus means when said associated processor requests access to the resources associated with another selected one of said n processors.

3. The invention of claim 2, wherein each of said n memory management means is responsive to a virtual memory address generated by said associated processor for mapping said virtual memory address into a resource address; and wherein each of said n memory management means is responsive to a resource address which identifies a resource not connected to said associated local bus means for generating a global bus means request and for applying said global bus means request to said priority arbiter means.

4. The invention of claim 3, wherein said priority arbiter means, is responsive to said global bus means request for generating a bus access signal when said global bus means is idle and for applying said bus access signal to said memory management means generating said global bus means request; and wherein said last mentioned memory management means is responsive to said bus access signal for applying said resource address to said global bus means thereby signalling said selected processor of the request.

5. The invention of claim 4, wherein said intercommunication means includes: n bus connect means associated on a one-to-one basis with said n processors for directly connecting said global bus means with said local bus means associated with said selected processor for providing access from said global bus means to said resources associated with said selected processor via said associated local bus means.

6. The invention of claim 5, wherein said intercommunication means includes: n local arbiter means associated on a one-to-one basis with said n processors, wherein each of said local arbiter means is responsive to the application of said resource address to said global bus means by said requesting memory management means for comparing said resource address to the addresses of the resources connected to said associated local bus means and for generating a receive enable signal when said resource address matches the address of one of said plurality of resources connected to said local bus means; and wherein said bus connect means is responsive to said receive enable signal for directly connecting said global bus means to said associated local bus means.

7. A multiprocessor computer system having n processor modules, wherein each of said n processor modules has associated therewith a plurality of resources, which resources are connected to said associated processor by a dedicated local bus means, said multiprocessor computer system including a processor module interconnection system comprising: global bus means connected to all of said n processor modules and providing interproces- sor module access, priority arbiter means connected to all of said n processor modules for regulating access to said global bus means; wherein each of said processor modules includes memory management means responsive to a memory access request by said associated processor for generating either a local bus means access signal or a global bus means access signal determined by the location of the resource addressed by said associated processor; and wherein said priority arbiter means is responsive to said global bus means access signal for enabling said requesting processor to access said global bus means when said global bus means is idle.

8. The invention of claim 7, wherein said n memory management means is responsive to said global bus means enable signal for applying the address of said resource addressed by said associated processor to said global bus means.

9. The invention of claim 8, wherein each of said n processor modules additionally contain local arbiter means responsive to the application of a resource address to said global bus means for comparing said resource address to the addresses of the resources assigned to that processor module and if the two addresses match, generating a module selected signal.

10. The invention of claim 9, wherein each of said n processor modules includes bus connect means responsive to said module selected signal for interconnecting said local bus means to said global bus means, thereby providing said requesting processor with direct access to said resource addressed by said associated processor.