JPS57501653A - - Google Patents
Info
- Publication number
- JPS57501653A JPS57501653A JP50304581A JP50304581A JPS57501653A JP S57501653 A JPS57501653 A JP S57501653A JP 50304581 A JP50304581 A JP 50304581A JP 50304581 A JP50304581 A JP 50304581A JP S57501653 A JPS57501653 A JP S57501653A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54508—Configuration, initialisation
- H04Q3/54533—Configuration data, translation, passwords, databases
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19008580A | 1980-09-23 | 1980-09-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57501653A true JPS57501653A (en) | 1982-09-09 |
Family
ID=22699959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50304581A Pending JPS57501653A (en) | 1980-09-23 | 1981-09-02 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0059731A4 (en) |
| JP (1) | JPS57501653A (en) |
| CA (1) | CA1191920A (en) |
| GB (1) | GB2086624B (en) |
| WO (1) | WO1982001095A1 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3276916D1 (en) * | 1981-09-18 | 1987-09-10 | Rovsing As Christian | Multiprocessor computer system |
| DE3218277A1 (en) * | 1982-05-14 | 1983-11-17 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT ARRANGEMENT FOR TELECOMMUNICATION SWITCHING SYSTEMS, ESPECIALLY TELECOMMUNICATION SWITCHING SYSTEMS, WITH A DEVELOPMENT OF THE SWITCHING SYSTEM PROCESSING MULTIPLE COMPUTER SYSTEMS |
| DD273911A1 (en) * | 1988-07-11 | 1989-11-29 | Zeiss Jena Veb Carl | METHOD AND ARRANGEMENT FOR THE BUS AWARD OF DATA PROCESSING DEVICES |
| DE3917730A1 (en) * | 1989-05-31 | 1990-12-06 | Teldix Gmbh | Decision logic for priority setting and synchronising async. signals - arbitrating access to global resource in multiprocessor system |
| EP0408810B1 (en) * | 1989-07-20 | 1996-03-20 | Kabushiki Kaisha Toshiba | Multi processor computer system |
| WO1994005112A1 (en) | 1992-08-25 | 1994-03-03 | Bell Communications Research, Inc. | System and method for creating, transferring, and monitoring services in a telecommunication system |
| US5442690A (en) | 1992-08-25 | 1995-08-15 | Bell Communications Research, Inc. | Telecommunication service record structure and method of execution |
| JP3098344B2 (en) * | 1992-12-18 | 2000-10-16 | 富士通株式会社 | Data transfer processing method and data transfer processing device |
| US5483656A (en) * | 1993-01-14 | 1996-01-09 | Apple Computer, Inc. | System for managing power consumption of devices coupled to a common bus |
| US5579486A (en) * | 1993-01-14 | 1996-11-26 | Apple Computer, Inc. | Communication node with a first bus configuration for arbitration and a second bus configuration for data transfer |
| US5493657A (en) * | 1993-06-21 | 1996-02-20 | Apple Computer, Inc. | High speed dominant mode bus for differential signals |
| DE4323704B4 (en) * | 1993-07-15 | 2006-06-14 | Tenovis Gmbh & Co. Kg | Circuit arrangement of an interface for interconnected via a parallel bus system controls a switching system |
| DE4331004B4 (en) * | 1993-07-15 | 2009-06-18 | Tenovis Gmbh & Co. Kg | Circuit arrangement of an interface for interconnected via a parallel bus system control of a switching system |
| WO2000064197A1 (en) * | 1999-04-20 | 2000-10-26 | Siemens Aktiengesellschaft | Scalable multi-processor system for real time applications in communications engineering |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4123794A (en) * | 1974-02-15 | 1978-10-31 | Tokyo Shibaura Electric Co., Limited | Multi-computer system |
| US3934232A (en) * | 1974-04-25 | 1976-01-20 | Honeywell Information Systems, Inc. | Interprocessor communication apparatus for a data processing system |
| US4276594A (en) * | 1978-01-27 | 1981-06-30 | Gould Inc. Modicon Division | Digital computer with multi-processor capability utilizing intelligent composite memory and input/output modules and method for performing the same |
| US4253144A (en) * | 1978-12-21 | 1981-02-24 | Burroughs Corporation | Multi-processor communication network |
| US4264954A (en) * | 1979-09-04 | 1981-04-28 | Ncr Corporation | Distributed function communication system for remote devices |
-
1981
- 1981-09-02 WO PCT/US1981/001176 patent/WO1982001095A1/en not_active Application Discontinuation
- 1981-09-02 EP EP19810902530 patent/EP0059731A4/en not_active Withdrawn
- 1981-09-02 JP JP50304581A patent/JPS57501653A/ja active Pending
- 1981-09-11 CA CA000385706A patent/CA1191920A/en not_active Expired
- 1981-09-22 GB GB8128681A patent/GB2086624B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0059731A1 (en) | 1982-09-15 |
| CA1191920A (en) | 1985-08-13 |
| GB2086624A (en) | 1982-05-12 |
| EP0059731A4 (en) | 1985-10-01 |
| WO1982001095A1 (en) | 1982-04-01 |
| GB2086624B (en) | 1984-02-22 |