DD273911A1 - METHOD AND ARRANGEMENT FOR THE BUS AWARD OF DATA PROCESSING DEVICES - Google Patents

Abstract

The invention relates to a method and an arrangement for bus allocation to data processing facilities, which serves to control a priority Busuebernahme by the devices in the bus coupled from single buses Globalbus. The assignment signal for a device and its stored location data are used in a first cycle of the detection of individual buses with the bus and non-buserhaltenden facilities, the bus request signals of the devices are blocked at the individual buses without bus-preserving device in the bus allocation with Einzelbuswechsel. In a second clock period occurs at a single bus change a circuit of the bus-busy signals on the single bus with the bus-receiving device in the inactive and the bus with the bus-emitting device in the active state. All other bus-busy signals are kept active. In a third clock period, in which the bus-busy signal is activated on the single bus of the bus-receiving device, the successful blocking of the request signals is canceled. Fig. 1

Description

Characteristic of the known technical solutions

If several data-processing devices work together in an information-processing system via a shared resource with other resources located on the bus, the activation of a data-processing device takes place. B. a CPU) time shared on the common bus and controlled by bus allocation circuits (Arbiter). When a data processing device is to be connected to the bus to communicate with another resource, it makes a request over there bus, causing a central or decentralized allocation circuit to allocate the bus to the requesting device according to a stored algorithm, so that these, then the bus can be assigned. When multiple devices submit a request, the allocation algorithm, which takes into account, for the most part, priority dependencies on the processing of requests, causes the selection of a bus requesting device. ("The 8086/8088 Book Programming in Assembler and System Architectures, Technik Marketing, Munich, Chapter 9, S19-8] to [9-10], Chapter 10, pp. 10-4 to [10-6]. ) Are known, for example M.7 S.457-561) and circuits according to the daisychain principle In a method for priority-based Eusvergabe in multi-core computer systems (DD 237017 A1) the object is achieved in that in the unoccupied bus channel-wise an allocation signal, which contains the priority information, circulates in a logical circuit.

Each device connected to the bus system monitors channel by channel the Zus'.and of the bus. When sending request, the corresponding device is connected to all available channels. Upon receipt of a Zi'tcilungssignals this is stopped and the registered therein priority compared with the corresponding device. If the entered priority is equal to the priority of the corresponding ready-to-send device, then it receives the bus access.

In an arrangement for controlling a multi-computer system (DD-WP 144691) is used as an arbitration signal a stationary bit pattern, which rotates in an annularly closed shift chain. The bus access takes place according to a given pattern and is priority-dependent.

In DD-WP 238128 A1 an arrangement of a memory-programmed arbiter for resource management is explained, which consists of claim registers, control registers, a memory and an output module and a control unit. With all these technical solutions, a bus access control on a global bus consisting of multimaster-capable single buses by occurring Buslaufzeiteffekte over the bus coupling point only with increased circuit complexity or not feasible.

Object of the invention

The aim of the invention is to realize a fast priority-based bus allocation with low circuit complexity in (bus) -coupled multimaster-enabled buses.

Explanation of the essence of the invention

The invention is based on the object in a spatially separate, multimaster-capable buses coupled together multimaster Globalbus bus to ensure a priority-oriented bus, without bus runtime effects on the bus protocol impact.

To achieve the object according to the invention is a method for bus allocation to data processing facilities, which are connected to coupled to a global bus multimasterfähige single buses, wherein within a central bus clock from channel-wise sent by the facilities request signals, taking into account a preprogrammed assignment rule formed an assignment signal and to the device with the request highest priority request is transmitted, a bus assignment is marked by an active bus busy signal, and the bus can be done with and without a single bus change. With the allocation signal generated within a first clock period of the central bus clock in which the bus busy signal for the single bus of a bus issuing device is inactive and active for the other single buses, and stored location data of the data processing devices are within the same clock period of the Single bus with a bus-holding device and the individual buses determined with non-bus devices and blocks the request signals of the devices to the individual buses without bus-holding device in the bus allocation with Einzelbuswechsel.

In a subsequent second clock period of the bus clock takes place only in the bus allocation with Einzelbuswechsel a circuit of bus-busy signals on the bow with the bus-maintaining device in the inactive and the bus with the bus-emitting device in the active state, all other bus-busy Signals are kept in the active state. If the bus allocation takes place without a single bus change, the blocking of the request signals in the first clock period is interrupted, and in the second clock period the circuit of the bus-busy signals is interrupted.

In a subsequent third clock period in which the bus-busy signal is active on the single bus of the bus-receiving device, the blocking of the request signals of the devices on the individual buses without bus-preserving device, which takes place during bus allocation with a single bus change, is canceled.

The invention further relates to an arrangement for bus allocation to data-processing facilities, which are connected to coupled to a Globalbus, multimaster-capable single buses, each of which is in communication with a central bus clock generator and has an allocation device for the formation of assignment signals from channel-wise sent request signals of Data processing facilities for bus maintenance under consideration of a preprogrammed assignment rule is used, with a bus occupancy is marked by an active bus busy signal.

Each individual bus is a request blocking, the input side is associated with the request channels of the data processing facilities of the associated single bus and the output side to the inputs of the allocators of all individual buses, and assigned a monitoring and control circuit, at the inputs both the outputs

the allocation device, of which the individual bus associated with the Zuorc tion channels of the single bus, as well as the bus-busy signal, the bus clock and a reset channel of the single bus are performed. Of each monitoring and control circuit is the output for the bus-busy signal with the signal bus line of the single bus, the output for a signal to identify a Globalbusübernahme to the inputs of the other monitoring and control circuits and the output door a lock request signal to another Excluded input of the request blocking, wherein in the request blocking, a combination of the request and the barrier request signal takes place, which results in an active lock request signal an inactive logic signal and inactive lock request signal to the original request signal corresponding logic signal.

embodiment

The invention will be explained in more detail below with reference to the schematic drawing. Show it:

Fig. 1: sine arrangement for Busvtrgabe according to the invention

2 shows the structure of the circuit part which monitors the bus of the respective individual bus and controls it. FIG. 3 shows the timing diagram for the arrangement according to FIG. 1

4 shows the timing diagram for the structure of FIG. 2

According to FIG. 1, the arrangement used for carrying out the method according to the invention contains for each ith single bus an allocation and control circuit 11 which has bus request signals AFJI with J = (1... M; 1... N; ... S) and I = (1 ... R), and bus busy signal BbI monitors and controls and also takes over the control of bus assignment signals ZJI. The circuits 11 communicate with each other via global bus acceptance signals GBI and are centered on each of the single buses with respect to the global bus formed by the paired I single buses. Each circuit 11 consists of a request block 21, an assignment rule 31 with an assignment rule stored as an algorithm, and a monitoring and control circuit 4I for the bus-busy signal BbI of the respective single bus I.

The request blocking 21 is connected on the input side to J request channels for the signals AFjI and to an output for a disable request signal SAFI of the monitoring and control circuit 4I. The J outputs of the request blocking 21 are routed to the inputs of the allocators 31 of all individual buses (I = [1 ... 2]). The k outputs Z1I to ZkI with k = (N, ..., M, ... S) and I = (1 ... R) of the allocator 31 are connected to the inputs of the monitoring and control circuit 41, where J Outputs Z11 to ZJI are also connected to assignment channels of the single bus I, wherein J characterizes the corresponding request signal AFJI assignment channel ZJI the l-th bus. Of the circuit 4I is the output for the bus-busy signal with a signal bus line of the single bus I and the output for the global bus acceptance signal GBI to the inputs of the other monitoring and control circuits 4U with U = 1 ... 2 but =! guided. To further inputs of the circuit 41, a reset signal RESET are turned on and applied to the bus busy signal BbI and a central bus clock BT of a bus clock generator, not shown. On the reset line devices not shown can activate a return signal, which sets all devices located on the Globalbus including the assignment and control circuit 11 in the respective initial state.

In the request pad 21, each request signal AFJI is associated with a disable request signal SAFJ, with inactive SAFJ inactive link signals AFJI are formed and with inactive signal SAFI the original request signal AFJI arises as Verk.iüpfungssignal AFJI

 The monitoring and control circuit 4I is made as shown in FIG

a circuit part 5I for determining a detection signal BMI, which in its active state indicates whether a. bus-occupying or maintaining device belongs to the single bus I,

a circuit part 6I for determining a detection signal BHyI, which in its active state indicates whether a bus-keeping device belongs to one of the other R-1 single buses.

The Scht'tungsteile 5I and 6I are thus detection circuits for a bwz vorgesehe. made global bus assignment and include a hardware or software preprogrammed component for determining whether a device on the bus I or to the other R-1 single buses is turned on and a comparator to from the current allocation signal and the preprogrammed position information of the device belonging to the bus bus-preserving or -belegenden device to bus I or to determine the Π-1 single buses. Continue out

logic logic circuits 71, 91, 111, 121, 141, 151, 171, 171,

- a trigger circuit lOlzur Busflankentriggerung

a clock-controlled register S! for the identification of a global bus transfer by the signal GBI

a clock-controlled register 131 for storing the active state dss bus-busy signal BbI in a clock period of the bus clock BT following that for detecting individual buses I with bus-preserving and non-bus-maintaining devices, and

a clock control register 161 for storing the disable request signal SAFJ.

The links generated by the logic gates are given below, where az () represents the active state of ...

and iaz () correspond to the inactive state of.

Circuit 71

az (BWI) = az (BHyI) λaz (GBI ') λaz (BbI) (8-1)

Rs

mitaz (BHyl) = V V azZTP P = 1 T = N

and GBI '= negated GBI

Circuit 9I

az (TFI) = 1 az (BbI) λ az (BT) (8-2)

Circuit 111

az (TSI) = az (TSPIKEI) λ iaz (BbHI) (8-3)

Circuit 121

az (TSRI) = az (TSI) V az (GBUI) (8-4)

Circuit 141

az (BbI) = az (BbHI) V az (GBUI) (8-5)

Circuit 151

az (GBUD = R az (GBI) (8-6)

J = 1

Circuit 171

az (TS) = az (BT) λ iaz (BbHI)

Here Are

BWI a bus change signal

TFI a flip-flop clock signal

TSI a set clock signal

TSRI a set-reset clock signal

GB1 ... GBR, GBI Signals for the identification of a global bus transfer for 1 ... R, I OBUI a sum global bus acceptance signal and

L'bH is a bus busy and stop signal

TSPIKEI a clock signal during bus allocation, its reset in a circuit, not shown by the

logical or active state; of the signal TSPIKEI with the active state of the signal RESET. While to the inputs of the circuit part El, whose output is connected to the data input Di of the register 81, the bus allocation signals Z1IZMI are applied, the bus allocation signals Z1P-ZTP are fed to the inputs of the circuit part 6I, whose output signal BHyI to an input the logic circuit 71 is applied. The following applies:

(P = 1 ... R) a (P * I), T = (N, ... S)

Other inputs of the logic circuit 71 are indirect, i. h., Last- and capacitively decoupled with the bus-busy signal BbI, which is also performed in the same way to an input of the logic circuit 9I, and occupied by the negated signal to identify the global bus occupancy GBI 'of the register 81. The bus clock BT, which is also routed to the clock input of the trigger circuit 101, is also indirectly connected to the other input of the logic circuit. The signal BWI present at the output of the logic circuit 71 is applied to the data inputs of the register 131 and the bus clocked register 161, the clock input of the register 161 being connected to the output of the logic circuit 171, which represents a gate through which the bus clock is indirectly coupled BT is running. The register 131 is connected at its clock input C to the output TSRI of the logic circuit 121 and at its output at which the signal BbHI is present, to the inputs of the logic circuits 141 and 171. The signal BbHI is also fed to an input of the logic circuit 111, at whose other input the signal TSPIKEJ is applied and whose output is connected to an input of the logic circuit 121. The set clock signal TSI runs via this connection.

The other input of the logic circuit 121 is assigned to the signal GBUI, which is formed by the logic circuit 151 and which also applied to the other input of the logic circuit 141.

The reset inputs R of the registers 81, 131, 161 and the trigger circuit 101 are connected to the reset signal RESET, wherein an active state of the RESET signal causes generation of a non-active state. The timing diagrams in FIGS. 3 and 4 reflect the method in its method steps as well as the mode of operation of the arrangement and are shown reduced to R = 2 buses for the sake of clarity. They describe a bus transfer from a bus-issuing device located on bus I = 1 to a bus-receiving device located on bus I = 2 on the basis of the self-adjusting states.

Table 1 shows the definitions of the active states of the signals. These states apply to a global bus consisting of two or more IEEE 796 coupled buses (AMS buses).

For the areas marked A in FIG. 3, the allocation device assumes the switching of the states, for the areas B the bus-maintaining device.

In AFpY, μ: index for the line number of the requirements of Busy γ: bus identifier

Table 1

Signal name active state Switching edge

AFJI LOW High-LOW AFJI LOW BbHI LOW BBI LOW BHI High BHyI High BT BWI High High-LOW GBI LOW LOW-High site gbui LOW LOW-High RESET LOW SAFI LOW TFI High TSI TSRI TSPIKEI ZTP LOW

Claims (2)

1. A method for bus allocation to data processing equipment, which are connected to coupled to a global bus, multimaster-capable single buses, wherein formed within a central bus clock from channel-wise sent by the devices request signals taking into account a preprogrammed assignment rule an assignment signal and to the device with the request signal of the highest priority a bus assignment is marked with an active bus busy signal, and the bus can be done with and without a single bus change, characterized in that with the assignment signal that within a first clock period of the central bus clock in which the bus-occupied Signal for the single bus of a bus-emitting device is inactive and active for the other single buses is generated, and stored location data of the data processing devices within the same clock period of the single bus with a bus-receiving device and the individual buses are determined with non-bus-preserving facilities and the request signals of the devices are blocked at the individual buses without bus-preserving device at the bus allocation with Einzelbuswechsel that in a subsequent second clock period of the bus clock only at the bus allocation with Einzelbuswechsel a circuit of bus-busy signals the bus with the bus-receiving device in the inactive and the bus with the bus-emitting device in the active state, all other bus-busy signals are kept in the active state; and that in a subsequent third clock period in which the bus busy signal! is actively switched on the single bus of the buena-preserving device, which was canceled in the Busergabe with Einzelbuswechoel blocking the request signals of the facilities on the individual buses without bus-preserving device. 2. An arrangement for bus allocation to data processing equipment, which are connected to coupled to a global bus, multimaster-capable single buses, each of which is in communication with a central bus clock generator and has an allocation device for forming assignment signals from channel-wise transmitted request signals of the data processing facilities for a Bus receipt under consideration of a preprogrammed assignment rule is used, wherein a bus occupancy is marked by an active bus busy signal, characterized in that each single bus a request blocking, the input side to the request channels of the data processing facilities of the associated single bus and the output side of the inputs of the allocation of all single buses linked is assigned, and a monitoring and control circuit, at whose inputs both the outputs of the allocation device, of which the single bus associated with the assignment channels of the single bus, and the bus-busy signal, the bus clock and a reset channel of the single bus are guided, and that of each monitoring and control circuit, the output for the bus-busy signal with the signal bus of the Single Buses, the output is connected to a signal to identify a Globalbusübernahme to the inputs of the other monitoring and control circuits and the output for a lock request signal to another input of the request blocking, wherein in the request blocking a combination of the request and lock request signal takes place, the active lock request signal an inactive link signal and in the case of inactive disable request signal results in a link signal corresponding to the original request signal. For this 4 pages drawings Field of application of the invention The invention relates to the field of digital data processing in the multimaster-capable single buses, are connected to the data processing facilities, coupled to a multimaster Globalbus and serves to control a priority Busrestruh 'rch the facilities in the Globalbus.