KR20010030591A - 기판 바이어싱을 이용하는 씨모스 지연 회로 - Google Patents

기판 바이어싱을 이용하는 씨모스 지연 회로 Download PDF

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Publication number
KR20010030591A
KR20010030591A KR1020007002633A KR20007002633A KR20010030591A KR 20010030591 A KR20010030591 A KR 20010030591A KR 1020007002633 A KR1020007002633 A KR 1020007002633A KR 20007002633 A KR20007002633 A KR 20007002633A KR 20010030591 A KR20010030591 A KR 20010030591A
Authority
KR
South Korea
Prior art keywords
delay element
delay
effect transistor
gate
field effect
Prior art date
Application number
KR1020007002633A
Other languages
English (en)
Korean (ko)
Inventor
메스머아드리안
스췔러줘드제이이
Original Assignee
롤페스 요하네스 게라투스 알베르투스
코닌클리즈케 필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 롤페스 요하네스 게라투스 알베르투스, 코닌클리즈케 필립스 일렉트로닉스 엔.브이. filed Critical 롤페스 요하네스 게라투스 알베르투스
Publication of KR20010030591A publication Critical patent/KR20010030591A/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1020007002633A 1998-07-14 1999-07-02 기판 바이어싱을 이용하는 씨모스 지연 회로 KR20010030591A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP98202357.4 1998-07-14
EP98202357 1998-07-14
PCT/EP1999/004708 WO2000004638A1 (en) 1998-07-14 1999-07-02 Cmos delay circuit using substrate biassing

Publications (1)

Publication Number Publication Date
KR20010030591A true KR20010030591A (ko) 2001-04-16

Family

ID=8233925

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020007002633A KR20010030591A (ko) 1998-07-14 1999-07-02 기판 바이어싱을 이용하는 씨모스 지연 회로

Country Status (4)

Country Link
EP (1) EP1016212A1 (ja)
JP (1) JP2002520979A (ja)
KR (1) KR20010030591A (ja)
WO (1) WO2000004638A1 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4757623B2 (ja) * 2005-12-21 2011-08-24 パナソニック株式会社 電源回路
JP4921329B2 (ja) * 2007-11-28 2012-04-25 株式会社デンソー Ａ／ｄ変換回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092548A (en) * 1977-03-15 1978-05-30 International Business Machines Corporation Substrate bias modulation to improve mosfet circuit performance
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
US4988960A (en) * 1988-12-21 1991-01-29 Yamaha Corporation FM demodulation device and FM modulation device employing a CMOS signal delay device
JPH0715313A (ja) * 1993-06-18 1995-01-17 Matsushita Electric Ind Co Ltd Ｃｍｏｓ論理回路
JP2822881B2 (ja) * 1994-03-30 1998-11-11 日本電気株式会社 半導体集積回路装置
JPH0823271A (ja) * 1994-07-08 1996-01-23 Matsushita Electric Ind Co Ltd Ｃｍｏｓ論理回路

Also Published As

Publication number Publication date
WO2000004638A1 (en) 2000-01-27
EP1016212A1 (en) 2000-07-05
JP2002520979A (ja) 2002-07-09

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Legal Events

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WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid