WO2000004638A1 - Cmos delay circuit using substrate biassing - Google Patents
Cmos delay circuit using substrate biassing Download PDFInfo
- Publication number
- WO2000004638A1 WO2000004638A1 PCT/EP1999/004708 EP9904708W WO0004638A1 WO 2000004638 A1 WO2000004638 A1 WO 2000004638A1 EP 9904708 W EP9904708 W EP 9904708W WO 0004638 A1 WO0004638 A1 WO 0004638A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- delay element
- field effect
- effect transistor
- delay
- gate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
Definitions
- the invention relates to a delay element, for delaying a signal which propagates through the delay element by a delay, comprising a field effect transistor having a source, a drain, a gate, and a back-gate.
- Such a delay element is known from the European patent application EP 0 661 809 Al.
- a voltage controlled current source is arranged in series with the source electrode of the field effect transistor.
- a current through the field effect transistor can be varied, which thereby varies the delay of the delay element.
- the voltage controlled current source consumes a part of the supply voltage. Since nowadays there is a need for making electronic circuits which can operate at a low supply voltage, the consumption of part of the supply voltage is disadvantageous.
- the delay element of the type defined in the opening paragraph is characterized in that the back-gate is arranged to receive a control voltage for controlling the delay of the delay element.
- the delay element may further comprise a further field effect transistor having a source, a drain coupled to the drain of the field effect transistor, and a gate coupled to the gate of the field effect transistor.
- the source of the field effect transistor is connected to a first terminal of a voltage supply source for supplying a supply voltage.
- the source of the further transistor is connected to a second terminal of the voltage supply source.
- the invention also relates to an oscillator including the delay element according to the invention as claimed in Claims 1 and 2. Since the oscillation frequency of the oscillator depends on the delay of the delay element, the oscillation frequency can be controlled by the control voltage which controls the delay of the delay element. It appears that the oscillation frequency is virtually linear with respect to the control voltage over a very wide frequency range.
- the invention also relates to a phase-locked loop (PLL) circuit including the afore-mentioned oscillator according to the invention as claimed in Claim 4.
- PLL phase-locked loop
- a low- voltage phase-locked loop circuit is obtained which does not need a d.c./d.c. up-converter for locally increasing the supply voltage.
- This has the advantage that a phase-locked loop circuit according to the invention is simplified.
- Another advantage in case that the phase-locked loop circuit is incorporated in an integrated circuit is that it requires only a relatively small amount of chip area.
- Figure 1 is a circuit diagram of an embodiment of a delay element according to the invention.
- Figure 2 is a circuit diagram of a further embodiment of a delay element according to the invention.
- Figure 3 is a circuit diagram of an oscillator including delay elements according to the invention.
- Figure 1 shows a delay element DL having an input terminal IP, an output terminal OP, and a control terminal CNTRL.
- the delay element DL is powered by a voltage supply source SV having a first supply terminal SVT and a second supply terminal RF.
- the delay element DL comprises a field effect transistor T ⁇ having a source connected to the first supply terminal SVT, a drain connected to the output terminal OP, a gate connected to the input terminal IP, and a back-gate BG connected to the control terminal CNTRL.
- a load impedance Z is connected between the output terminal OP and the second supply terminal RF.
- An input signal Uj which is applied between the input terminal IP and the second supply terminal RF, propagates through the delay element DL and produces an output signal U 0 between the output terminal OP and the second supply terminal RF.
- the delay element DL also delays the input signal Uj.
- the delay inter alia depends on a current flowing through the field effect transistor T
- V cntr ⁇ between the source of the field effect transistor T and the back-gate BG
- the current through the field effect transistor T,, and thus the delay can be varied by varying the control voltage V cntr i.
- the load impedance can, for example, be a resistor, but alternatively other components, like transistors, can be applied.
- FIG. 2 shows a circuit diagram of a further embodiment of a delay element according to the invention.
- the load impedance Z (see Figure 1) is formed by a further field effect transistor T 2 .
- the further field effect transistor T 2 has a drain connected to the output terminal OP, a source connected to the second supply terminal RF, and a gate connected to the input terminal IP.
- the field effect transistor Ti and the further field effect transistor T 2 form together an inverter stage having the special feature that the delay of the inverter (and thus of the delay element) can be varied by the control voltage V cntr ⁇ .
- the control voltage V cntr i can also be applied to a back-gate of the further field effect transistor T 2 .
- both the back-gate BG of the field effect transistor Ti and the back-gate of the further field effect transistor T 2 can be controlled by control voltages. This has the advantage of a larger range of the delay. (However, in many IC CMOS-processes it is not possible to apply control voltages to both PMOSTs and N-MOSTs).
- Figure 3 shows a circuit diagram of an oscillator OSC including delay elements
- each delay element DL is controlled by the control voltage V cntr ⁇ .
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99931253A EP1016212A1 (en) | 1998-07-14 | 1999-07-02 | Cmos delay circuit using substrate biassing |
JP2000560661A JP2002520979A (en) | 1998-07-14 | 1999-07-02 | CMOS delay circuit using substrate bias |
KR1020007002633A KR20010030591A (en) | 1998-07-14 | 1999-07-02 | Cmos delay circuit using substrate biassing |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98202357 | 1998-07-14 | ||
EP98202357.4 | 1998-07-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000004638A1 true WO2000004638A1 (en) | 2000-01-27 |
Family
ID=8233925
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1999/004708 WO2000004638A1 (en) | 1998-07-14 | 1999-07-02 | Cmos delay circuit using substrate biassing |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1016212A1 (en) |
JP (1) | JP2002520979A (en) |
KR (1) | KR20010030591A (en) |
WO (1) | WO2000004638A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7741986B2 (en) | 2007-11-28 | 2010-06-22 | Denso Corporation | Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4757623B2 (en) * | 2005-12-21 | 2011-08-24 | パナソニック株式会社 | Power circuit |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4092548A (en) * | 1977-03-15 | 1978-05-30 | International Business Machines Corporation | Substrate bias modulation to improve mosfet circuit performance |
GB2086681A (en) * | 1980-10-22 | 1982-05-12 | Tokyo Shibaura Electric Co | Temperature compensated semiconductor integrated circuit |
US4988960A (en) * | 1988-12-21 | 1991-01-29 | Yamaha Corporation | FM demodulation device and FM modulation device employing a CMOS signal delay device |
JPH0715313A (en) * | 1993-06-18 | 1995-01-17 | Matsushita Electric Ind Co Ltd | Cmos logic circuit |
JPH0823271A (en) * | 1994-07-08 | 1996-01-23 | Matsushita Electric Ind Co Ltd | Cmos logic circuit |
US5612643A (en) * | 1994-03-30 | 1997-03-18 | Nec Corporation | Semiconductor integrated circuit which prevents malfunctions caused by noise |
-
1999
- 1999-07-02 KR KR1020007002633A patent/KR20010030591A/en not_active Application Discontinuation
- 1999-07-02 WO PCT/EP1999/004708 patent/WO2000004638A1/en not_active Application Discontinuation
- 1999-07-02 JP JP2000560661A patent/JP2002520979A/en not_active Withdrawn
- 1999-07-02 EP EP99931253A patent/EP1016212A1/en not_active Withdrawn
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4092548A (en) * | 1977-03-15 | 1978-05-30 | International Business Machines Corporation | Substrate bias modulation to improve mosfet circuit performance |
GB2086681A (en) * | 1980-10-22 | 1982-05-12 | Tokyo Shibaura Electric Co | Temperature compensated semiconductor integrated circuit |
US4988960A (en) * | 1988-12-21 | 1991-01-29 | Yamaha Corporation | FM demodulation device and FM modulation device employing a CMOS signal delay device |
JPH0715313A (en) * | 1993-06-18 | 1995-01-17 | Matsushita Electric Ind Co Ltd | Cmos logic circuit |
US5612643A (en) * | 1994-03-30 | 1997-03-18 | Nec Corporation | Semiconductor integrated circuit which prevents malfunctions caused by noise |
JPH0823271A (en) * | 1994-07-08 | 1996-01-23 | Matsushita Electric Ind Co Ltd | Cmos logic circuit |
Non-Patent Citations (3)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 17, no. 19 13 January 1993 (1993-01-13) * |
PATENT ABSTRACTS OF JAPAN vol. 199, no. 504 31 May 1995 (1995-05-31) * |
PATENT ABSTRACTS OF JAPAN vol. 199, no. 605 31 May 1996 (1996-05-31) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7741986B2 (en) | 2007-11-28 | 2010-06-22 | Denso Corporation | Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof |
DE102008059120B4 (en) | 2007-11-28 | 2018-06-14 | Denso Corporation | A method for controlling a delay time of a pulse delay circuit and pulse delay circuit for applying such a method |
Also Published As
Publication number | Publication date |
---|---|
JP2002520979A (en) | 2002-07-09 |
KR20010030591A (en) | 2001-04-16 |
EP1016212A1 (en) | 2000-07-05 |
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