KR20010028992A - 반도체 패키지 및 그의 제조 방법 - Google Patents
반도체 패키지 및 그의 제조 방법 Download PDFInfo
- Publication number
- KR20010028992A KR20010028992A KR1019990041559A KR19990041559A KR20010028992A KR 20010028992 A KR20010028992 A KR 20010028992A KR 1019990041559 A KR1019990041559 A KR 1019990041559A KR 19990041559 A KR19990041559 A KR 19990041559A KR 20010028992 A KR20010028992 A KR 20010028992A
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- semiconductor chip
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- semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (7)
- 개구부가 형성된 기판,상기 개구부내에 제 1 내부 연결 수단을 이용하여 부착된 제 1 반도체 칩,상기 기판의 표면에 제 2 내부 연결 수단을 이용하여 부착된 제 2 반도체 칩,상기 기판의 저면에 형성된 솔더 볼을 포함하여 이루어짐을 특징으로 하는 반도체 패키지.
- 제 1 항에 있어서,상기 제 1, 2 내부 연결 수단은 플립칩 범프인것을 특징으로 하는 반도체 패키지.
- 기판의 개구부 표면에 제 1 내부 연결 수단을 형성하는 단계,상기 제 1 내부 연결 수단상에 제 1 반도체 칩을 부착하는 단계,상기 개구부를 제외한 기판의 표면상에 제 2 내부 연결 수단을 형성하는 단계,상기 제 2 내부 연결 수단상에 제 2 반도체 칩을 부착하는 단계,상기 제 2 반도체 칩을 포함한 기판의 소정부분을 봉지하는 단계,상기 기판의 저면에 솔더 볼을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 3 항에 있어서,상기 개구부는 상기 기판의 저면에 형성되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 3 항에 있어서,상기 제 2 반도체 칩은 상기 개구부를 제외한 기판의 표면에 부착되는 것을특징으로 하는 반도체 패키지의 제조 방법.
- 제 3 항에 있어서,상기 제 2 반도체 칩은 상기 개구부가 형성된 기판의 타면에 부착되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
- 제 3 항에 있어서,상기 개구부는 상기 기판의 저면에 상기 제 1 반도체 칩을 포함하여 봉지되는 것을 특징으로 하는 반도체 패키지의 제조 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990041559A KR100351922B1 (ko) | 1999-09-28 | 1999-09-28 | 반도체 패키지 및 그의 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990041559A KR100351922B1 (ko) | 1999-09-28 | 1999-09-28 | 반도체 패키지 및 그의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010028992A true KR20010028992A (ko) | 2001-04-06 |
KR100351922B1 KR100351922B1 (ko) | 2002-09-12 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990041559A KR100351922B1 (ko) | 1999-09-28 | 1999-09-28 | 반도체 패키지 및 그의 제조 방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100351922B1 (ko) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100444175B1 (ko) * | 2001-12-28 | 2004-08-11 | 동부전자 주식회사 | 볼그리드 어레이 적층칩 패키지 |
KR100817091B1 (ko) * | 2007-03-02 | 2008-03-26 | 삼성전자주식회사 | 적층형 반도체 패키지 및 그 제조방법 |
KR101247342B1 (ko) * | 2011-09-30 | 2013-03-26 | 에스티에스반도체통신 주식회사 | 패키지 온 패키지 제조방법 |
WO2013066294A1 (en) * | 2011-10-31 | 2013-05-10 | Intel Corporation | Multi die package structures |
US20160233165A1 (en) * | 2010-07-23 | 2016-08-11 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
-
1999
- 1999-09-28 KR KR1019990041559A patent/KR100351922B1/ko active IP Right Grant
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100444175B1 (ko) * | 2001-12-28 | 2004-08-11 | 동부전자 주식회사 | 볼그리드 어레이 적층칩 패키지 |
KR100817091B1 (ko) * | 2007-03-02 | 2008-03-26 | 삼성전자주식회사 | 적층형 반도체 패키지 및 그 제조방법 |
US20160233165A1 (en) * | 2010-07-23 | 2016-08-11 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
US9859220B2 (en) * | 2010-07-23 | 2018-01-02 | Tessera, Inc. | Laminated chip having microelectronic element embedded therein |
US10262947B2 (en) | 2010-07-23 | 2019-04-16 | Tessera, Inc. | Active chip on carrier or laminated chip having microelectronic element embedded therein |
KR101247342B1 (ko) * | 2011-09-30 | 2013-03-26 | 에스티에스반도체통신 주식회사 | 패키지 온 패키지 제조방법 |
WO2013066294A1 (en) * | 2011-10-31 | 2013-05-10 | Intel Corporation | Multi die package structures |
CN104025285A (zh) * | 2011-10-31 | 2014-09-03 | 英特尔公司 | 多管芯封装结构 |
US9490196B2 (en) | 2011-10-31 | 2016-11-08 | Intel Corporation | Multi die package having a die and a spacer layer in a recess |
US10083936B2 (en) | 2011-10-31 | 2018-09-25 | Intel Corporation | Semiconductor package having spacer layer |
US10636769B2 (en) | 2011-10-31 | 2020-04-28 | Intel Corporation | Semiconductor package having spacer layer |
Also Published As
Publication number | Publication date |
---|---|
KR100351922B1 (ko) | 2002-09-12 |
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