KR20010027014A - Printed Circuit Board for Semiconductor Packages - Google Patents

Abstract

PURPOSE: A printed circuit board for a semiconductor package is provided to prevent damage of a semiconductor chip due to electrostatic discharge during a molding process. CONSTITUTION: The printed circuit board(100) includes a resin base substrate in which a main-strip(4) is formed by a plurality of sub-strips(2) arranged in a row and each sub-strip(2) is formed by a plurality of through holes(8) arranged in a matrix form. On an upper surface of the resin substrate, conductive traces such as bond fingers and ball lands are formed around the through holes(8). On a lower surface of the resin substrate, conductive ground rings(25) of rectangular shapes are formed around the respective through holes(8). The conductive ground rings(25) are electrically connected to at least one conductive trace for grounding and to each other by X-shaped coupling lines(24). The conductive ground rings(25) are also electrically connected to a conductive pads(22) formed on one periphery of the resin substrate. The conductive pads(22) makes contacts with a mold in the molding process to prevent stores of static charges.

Description

Printed Circuit Board for Semiconductor Packages

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board for a semiconductor package, and more particularly, to prevent damage of a semiconductor chip due to a sudden static discharge by preventing the accumulation of static charge during the manufacturing process of the semiconductor package. A static eliminating printed circuit board for a semiconductor package can be effectively prevented.

Recently, electronic devices and home appliances are becoming smaller and higher in accordance with the rapid and high integration and miniaturization of semiconductor chips. Accordingly, the performance of highly integrated and miniaturized and high-performance semiconductor chips can be optimally implemented in semiconductor packages. In order to achieve excellent electrical performance, high heat dissipation, and a large capacity of input / output terminals are required.

In response to these demands, in recent years, ball grid array (BGA) semiconductor packages have been in the spotlight. Such a BGA semiconductor package not only shortens the overall length of the electric circuit by using a printed circuit board, but also easily introduces power or ground bonding areas, thereby facilitating excellent electrical performance and designing the number of input / output terminals. Since QFP (Quad Flat Package) can provide a much larger number of input / output terminals at a more relaxed interval, it has the advantage that the package can be miniaturized.

2A and 2B are a plan view and a bottom view of a conventional printed circuit board 10 'used for manufacturing a BGA semiconductor package as described above, respectively, and the structure thereof will be briefly described.

Typically, the printed circuit board 10 'includes a thermosetting resin substrate (6 in FIG. 3), a plurality of conductive traces 12 forming a predetermined circuit pattern on the upper and lower surfaces of the resin substrate 6, and a resin substrate. (6) A plurality of conductive via holes 13 electrically connecting the semiconductor chip mounting portion 17 of the upper surface center portion, the plurality of conductive traces 12 on the upper and lower surfaces of the resin substrate 6 to each other, and the resin substrate 6. A plurality of solder ball lands 14 respectively formed on the plurality of conductive traces 12 on the lower surface and the conductive metal serving as an inflow path for the molten molding compound from one corner of the upper surface of the resin substrate 6 to the semiconductor chip mounting portion 17. The plurality of conductive traces 12 are coated on all regions except the solder ball lands 14 and the end portions adjacent to the semiconductor chip mounting portions 17 of the plurality of conductive traces 12 and the mold runner gate 15 formed of a thin film. Insulating each other Multiple harmful consists of a non-jeonseongin cover coating 16 for protection from the environment.

Here, the mold runner gate 15 of the printed circuit board 10 ′ is electrically connected to the ground ring 25 formed on the outer circumference of the semiconductor chip mounting portion 17 via a predetermined ground conductive trace 22. All ground parts of the semiconductor chip are electrically connected to the ground ring 25 by a wire. As described above, the ground signal of the semiconductor chip is transmitted to the mold runner gate 15 to determine whether the conductive trace 12 and the semiconductor chip have poor wire bonding by the precise measurement of the voltage drop width or the common ground region. Optimum security of the circuit pattern by the formation of is possible.

In FIG. 2A and FIG. 2B, reference numeral 18 denotes a tooling hole for easily transporting or fixing the strip-shaped printed circuit board 10 ′ in the device, and 19 is singulation in a separate individual semiconductor package. The singulation hole is used as a reference point when the step is taken, and 19 'is a virtual cutting line at the time of singulation.

A typical ball grid array semiconductor package 1 using a general printed circuit board 10 'as described above is shown in FIG. 3, and the structure thereof will be briefly described through the manufacturing method thereof.

A semiconductor chip mounting step of adhering the semiconductor chip 40 to each of the semiconductor chip mounting portions 17 on the printed circuit board 10 ′ having the strip form as described above via an adhesive layer (not shown). Afterwards, the wire bonding step of electrically connecting the inner end of the conductive trace 12, which is not coated with the cover coat 16, and the semiconductor chip 40, the semiconductor chip 40 and the wire 50, etc. A molding step of forming a resin encapsulation part 70 for protection from the soldering step, a solder ball fusion step of fusion welding the solder ball 80 as an external input / output terminal on the solder ball land 14, and a printed circuit board 10 'in the form of a strip. By sequentially performing a singulation step of cutting a plurality of semiconductor packages formed on the substrate to a predetermined size and separating them into individual completed semiconductor packages 1, as shown in FIG. 3. The ball grid array semiconductor package 1 is configured.

In the molding step of manufacturing the semiconductor package 1 as described above, the molten molding resin (not shown) of the high temperature and high pressure is located in the cavity (not shown) printed circuit board 10 Is strongly rubbed against the semiconductor chip 40, the conductive wire 50, and the like. Therefore, due to such strong friction, a phenomenon in which static electricity is induced on the surface of the semiconductor chip 40, the conductive wire 50, the printed circuit board 10 ', and the like, a large amount of static charge is inevitably generated.

As described above, when the driving voltage of the semiconductor chip is high or the allowable error of the driving voltage is large, or when the circuit pattern in the semiconductor chip is not relatively fine, the accumulation of the static charge and the sudden discharge as described above have not affected much. If the driving voltage of the semiconductor chip is considerably low or the tolerance of the driving voltage is very small, and the circuit pattern is very fine, as described above, the sudden discharge due to the accumulation of the static charge as described above leads to immediate damage of the semiconductor chip.

That is, when the semiconductor package in which the static charge accumulated in the semiconductor chip, the conductive wire, or the like is completed is removed from the mold or in contact with the work equipment in another process, the electrostatic charge is temporarily discharged to burn the electrode of the semiconductor chip, or There is a serious problem that the minute circuit pattern in the semiconductor chip burns out, and this problem has emerged as a more important problem in today, which is increasingly required for miniaturization and high performance of the semiconductor chip.

In addition, in order to prevent electrostatic charge output due to friction with the molten resin during resin molding, a plurality of through-holes are arranged in rows and columns so that the semiconductor chips are located at a predetermined distance and arranged in a matrix form in a strip form. The design applied to the substrate has not been developed yet.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional problems as described above. In the matrix type circuit board, one ground ring of the sub-strip and each ground ring adjacent thereto are connected by electrical connection means. The present invention provides an electrostatic elimination type printed circuit board for a semiconductor package which can effectively prevent damage to the semiconductor chip due to sudden electrostatic discharge by preventing the accumulation of static charge during the manufacturing process to the semiconductor package by electrically connecting the same.

Another object of the present invention is to shorten the manufacturing process and improve productivity by electrically connecting one ground ring of the sub-strip and the ground ring of each sub-strip adjacent thereto. To provide a static elimination type printed circuit board that can achieve cost reduction.

1A and 1B are a plan view and a bottom view of a printed circuit board for a semiconductor package according to the present invention.

2A and 2B are plan and bottom views of a conventional printed circuit board, respectively.

3 is a cross-sectional view of a ball grid array semiconductor package to which a conventional printed circuit board is applied.

-Explanation of symbols for the main parts in the drawing-

-Description of the main symbols in the drawings-

100; Substrate 2; Sub-strip

4; Main-strip 6; Resin layer

8; Through hole 12; Bond finger

14; Ball land 16; Cover coat

22; Ground plane 24; Conductive Connection

25; Ground ring 26; Slot

28; Index hole

In order to achieve the above object, a printed circuit board for a semiconductor package according to the present invention is grouped with a plurality of through holes arranged in rows and columns spaced apart by a predetermined distance so that a semiconductor chip is positioned to form one sub-strip. The strip includes: a resin substrate having a plurality of main strips connected to each other by a boundary of a slot through which the strip is formed; A plurality of conductive traces forming a predetermined circuit pattern on the upper and lower surfaces of the resin substrates of each sub-strip and including at least ground traces; A plurality of conductive via holes electrically connecting the circuit patterns on the upper and lower surfaces of the resin substrate of each sub-strip and including at least one ground via hole; A cover coat coated on a circuit pattern of the resin substrate of each sub-strip to insulate and protect the plurality of conductive traces from each other; A plurality of ground rings electrically connected to the ground traces and respectively formed at the outer periphery of the plurality of through holes on the bottom surface of the resin substrate of each sub-strip; Connecting means for electrically connecting the one ground ring and an adjacent ground ring to each other; And a conductive pad electrically connected to the ground ring and positioned at an edge of the resin substrate to avoid accumulation of static charge during the semiconductor manufacturing process.

The connecting means is connected to the ground ring and the ground ring at each corner of the ground ring, the connection form is preferably X-shaped.

According to the electrostatic elimination type printed circuit board according to the present invention as described above, it is provided with connection means for electrically connecting one ground ring and an adjacent ground ring to each other, and electrically connected to the ring of the sub-strip. By providing a conductive pad located at the edge of the resin substrate, various problems such as breakage of a semiconductor chip and breakage of a circuit pattern of a printed circuit board due to temporary discharge of static electricity can be eliminated.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

1A and 1B are a plan view and a bottom view of a printed circuit board 100 for a semiconductor package 200 according to the present invention.

First, using a substantially rectangular resin substrate 6 as a base material, a plurality of through-holes 8 are arranged in rows and columns in a matrix shape so that a semiconductor chip (not shown) is located at a predetermined distance from each other. Clustered to form one sub-strip (2). Again, the sub-strips 2 are connected in the transverse direction with the slots 26 penetrating a predetermined length in the longitudinal direction to form one main strip 4.

On the surface of the resin substrate 6, which is the outer periphery of the through-hole 8 in each of the sub-strips 2, a semiconductor chip (not shown) and connecting means (not shown), for example, gold wire A bond finger 12 is formed to be connected by an electrical connection means such as a wire or an aluminum wire, and the bond finger 12 is fused so that a conductive ball 48, for example, a solder ball, is fused. ) Is connected to the ball land 14 is formed. Here, the bond finger 12 and the ball land 14 and the like are defined as conductive traces.

The surface of the resin substrate 6 and the circuit pattern is coated with a cover coat 16 made of a polymer resin so that the bond finger 12 and the ball land 14 are opened to the outside. 16 not only protects the circuit pattern from the external environment but also secures the rigidity of the entire printed circuit board 100.

On the other hand, a conductive ground ring 25 is formed in a substantially rectangular ring shape on the resin substrate 6, which is the outer periphery of each through hole 8, and the ground ring 25 is electrically connected to at least one ground conductive trace. It is connected to each other, and between each ground ring is electrically connected by the conductive connecting means (24). In more detail, the ground ring 25 is formed on the opposite side of the surface on which the conductive trace including the bond finger 12 and the borland 14 is formed, and a circuit pattern and a via hole (not shown). It is connected to each other, and the ground ring adjacent to the four corners of one ground ring 25 is connected in an X shape by the conductive connecting means 24. Such a plurality of ground rings 25 and a plurality of X-shaped conductive connecting means 24 improves the rigidity of the entire printed circuit board 100 as well as the ground of the semiconductor chip 42. In addition, the ground ring 25 may be coated on the surface of the resin substrate 6 with or without coating the surface of the cover coat 16, but with only an adhesive, which is only a choice of those skilled in the art.

In addition, a conductive APMP (Au Plated Metal Plane) pad 22 having a predetermined area is formed at the edge of the surface of the resin substrate 6 positioned at the edge of the printed circuit board 100. Metal Plane) The pad 22 is opened by a cover coat and is also electrically connected to the ground ring 25 which is electrically connected by a plurality of X-shaped conductive connecting means 24. The Au Plated Metal Plane (APMP) pad 22 may be formed on both surfaces of the resin substrate 6, unlike the ground ring 25. Therefore, the APMP pad is in contact with the mold during the semiconductor manufacturing process, in particular during molding, it is possible to more easily discharge the static electricity to the outside.

Here, the conductive trace, the ground ring 25, the conductive connecting means 24, the APMP (Au Plated Metal Plane) pad 22, etc., including the bond finger 12 and the ball land 14, are copper (Cu) thin films. Although it is preferable to form as, it is not limited only to the above-mentioned materials, and any materials may be used as long as it is a conductive material.

Reference numeral 28 in the drawings is an index hole for loading and fixing the printed circuit board 100 to various manufacturing equipment.

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.

According to the electrostatic elimination type printed circuit board for semiconductor packages according to the present invention as described above, it is provided with connecting means for electrically connecting one ground ring and a ground ring adjacent thereto, and the ring of the sub-strip and By providing a conductive pad positioned at the edge of the resin substrate which is electrically connected, various problems such as breakage of the semiconductor chip and breakage of the circuit pattern of the printed circuit board due to the temporary discharge of static electricity can be eliminated.

Claims (2)

A plurality of through-holes are grouped in a row and a column spaced apart by a predetermined distance so that the semiconductor chip is positioned to form a sub-strip, and the sub-strips are connected to a plurality of slots through a predetermined length of one main main line. A resin substrate forming a strip; A plurality of conductive traces forming a predetermined circuit pattern on the upper and lower surfaces of the resin substrates of each sub-strip and including at least ground traces; A plurality of conductive via holes electrically connecting the circuit patterns on the upper and lower surfaces of the resin substrate of each sub-strip and including at least one ground via hole; A cover coat coated on a circuit pattern of the resin substrate of each sub-strip to insulate and protect the plurality of conductive traces from each other; A plurality of ground rings electrically connected to the ground traces and respectively formed at the outer periphery of the plurality of through holes on the bottom surface of the resin substrate of each sub-strip; Connecting means for electrically connecting the one ground ring and an adjacent ground ring to each other; And a conductive pad electrically connected to the ground ring and positioned at an edge of the resin substrate to avoid accumulation of static charge during the semiconductor manufacturing process. The printed circuit board of claim 1, wherein the connection means connects the ground ring and the ground ring at each corner of the ground ring, and the connection form is X-shaped.