KR100365054B1 - substrate for semiconductor package and manufacturing method of semiconductor package using it - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for semiconductor package and a method for manufacturing a semiconductor package using the same. The present invention can simultaneously implement dozens to hundreds of ultra-thin semiconductor packages in a single substrate, and also wire bonding or molding. In order to minimize the warpage phenomenon during the process and to easily remove the adhesive tape during the manufacturing process, a plurality of through-holes are grouped in a row and a column spaced apart at a certain distance so that the semiconductor chip is positioned, A resin layer forming a strip, wherein the sub-strip is connected to a plurality of slots at a predetermined length to form a main strip; Conductive circuit patterns including bond fingers and ball lands to be connected to semiconductor resins and connecting means later on the resin layers that are outer periphery of the through-holes in the respective sub-strips, and to further weld the conductive balls; Substrate for a semiconductor package and a method for manufacturing a semiconductor package using the same, characterized in that it comprises a cover coat coated to open the bond finger and the ball land on the surface of the resin layer and the circuit pattern.

Description

Substrate for semiconductor package and manufacturing method of semiconductor package using same

The present invention relates to a substrate for a semiconductor package and a method for manufacturing the semiconductor package using the same. More specifically, it is possible to simultaneously implement dozens to hundreds of ultra-thin semiconductor packages in a single substrate, and also to wire bonding. The present invention relates to a semiconductor package substrate and a method for manufacturing a semiconductor package using the same, which minimize warpage during the molding process and can easily remove the adhesive tape during the manufacturing process.

In recent years, according to the trend of miniaturization and miniaturization of semiconductor chips and miniaturization of various electronic devices, semiconductor packages that support the semiconductor chips on the motherboard and mediate input / output signals are also converted into ultra-thin and chip-sized forms. have.

An example of the ultra-thin semiconductor package 200 ′ among these semiconductor packages is illustrated in FIG. 4. The structure of a conventional ultra-thin semiconductor package will be briefly described as follows.

As shown in the drawing, a semiconductor chip 42 'having an input / output pad is formed on one surface thereof, and through-holes are formed at the outer circumference of the semiconductor chip 42' so that the semiconductor chip 42 'can be positioned. 8 ') formed on the substrate 100', and the substrate 100 'has a resin layer 6' as a base layer, and a plurality of bond fingers 12 'and borland 14 are formed on the surface thereof. A circuit pattern made of ') is formed, and the surface of the resin layer 6' and the circuit pattern is coated with a cover coat 16 'such that a bond finger 12' and a ball land 14 'are opened. The input / output pads of the semiconductor chip 42 'and the bond fingers 12' of the substrate 100 'are interconnected by electrical connection means 44' such as conductive wires to be electrically connected. A portion of the semiconductor chip 42 ', the connection means 44', and the substrate 100 'positioned in the through hole 8' of the straight 100 'is enclosed by an encapsulant 46'. One surface of the semiconductor chip 42 'is exposed to the outside of the encapsulant 46'. Finally, a plurality of conductive balls 48 'are fused to the ball land 14' of the substrates 100 'so that they can be mounted on the motherboard later.

A method of manufacturing the semiconductor package as described above is briefly described as follows.

First, a resin layer is used as a base layer, and has a plurality of bond fingers and borland on the surface thereof, and the cover coat is coated with the bond fingers and borland open, thereby providing a substrate having a through hole formed in the center thereof. Here, the substrate is usually formed in one strip with a plurality of units in which independent semiconductor packages are formed.

A semiconductor chip having a plurality of input / output pads on one surface thereof is placed in the through hole of the substrate. At this time, a cover lay tape (not shown) is adhered to one surface of the substrat so as to close the through hole, and a semiconductor chip is adhered to the cover lay tape.

The input / output pads of the semiconductor chip and the bond fingers of the substrate are electrically connected to each other using electrical connection means.

A predetermined region of the semiconductor chip, the connecting means, and the substrate in the through hole is molded with an encapsulant.

A plurality of conductive balls are fused to the ball land formed on the substrate to form a final input / output terminal, and the coverlay tape adhered to the substrate is removed.

Finally, the final semiconductor package is obtained by singulating the semiconductor packages formed in each unit individually in the strip-shaped substrate.

On the other hand, the recent ultra-thin semiconductor package is manufactured in an area of about 5 × 5mm, and the situation is also produced in a thickness of about 1mm. Accordingly, although the requirement to simultaneously implement dozens to hundreds of semiconductor packages on the substrate is satisfied, as described above, a substrate that can simultaneously manufacture tens to hundreds of semiconductor packages has not been manufactured.

Meanwhile, a coverlay tape is attached to one surface of the substrate in order to mold the semiconductor chip during the manufacturing process. The coverlay tape causes various problems because the substrate has a different coefficient of thermal expansion. do.

That is, warpage (warpage) occurs in the substrate due to the difference in thermal expansion coefficient between the substrate and the coverlay tape during the wire bonding process or the molding process requiring high temperature conditions. This will greatly affect the reliability of the semiconductor package.

In addition, in the ultra-thin semiconductor package as described above, semiconductor chips and the like have various problems such as breakage of the semiconductor chip easily or short circuit patterns of the substrate due to the phenomenon that static electricity is accumulated and temporarily discharged during the molding process. The solution is urgent.

In addition, during the manufacturing process of the semiconductor package, the coverlay tape must be removed after adhering to the substrate. There is a risk of the substrate breaking when the coverlay tape is removed.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, and can simultaneously implement dozens to hundreds of ultra-thin semiconductor packages on one substrate, and also minimizes the warpage phenomenon during the wire bonding or molding process, The present invention provides a substrate for a semiconductor package that can easily remove a coverlay tape adhered during a manufacturing process and minimize the influence of static electricity, and a method for manufacturing a semiconductor package using the same.

1A and 1B are a plan view and a bottom view showing a substrate for a semiconductor package according to the present invention.

Figure 2 is a bottom view showing a state in which the tape is bonded to the substrate according to the present invention.

3A to 3H are sequential explanatory diagrams showing a method of manufacturing a semiconductor package according to the present invention.

4 is a cross-sectional view showing a conventional ultra-thin semiconductor package.

-Description of the main symbols in the drawings-

100; Substrate 2; Sub-strip

4; Main-strip 6; Resin layer

8; Through hole 12; Bond finger

14; Ball land 16; Cover coat

18; Ground ring

22; Ground Plane

24; Cover lay tape 26; Slot

28; Index hole 32; Punch

200; Semiconductor package 42; Semiconductor chip

44; Connecting means 46; Encapsulant

48; Conductive ball

In order to achieve the above object, a substrate for a semiconductor package according to the present invention is grouped with a plurality of through holes arranged in rows and columns spaced apart by a predetermined distance so that the semiconductor chip is positioned to form one sub-strip. The resin layer comprises a plurality of resin layers which are connected to a plurality of slots bordered by a predetermined length to form one main strip; A conductive circuit pattern including a bond finger and a ball land so as to be connected to one surface of the resin layer, which is the outer periphery of the through-holes in each of the sub-strips, by a semiconductor chip and a connecting means, and subsequently to bond the conductive balls; And a cover coat coated on the surface of the resin layer and the circuit pattern to open the bond finger and the ball land.

It is preferable to further form a ground ring on the opposite surface of the resin layer on which the circuit pattern is formed. In addition, the ground ring is preferably to be electrically connected to at least one or more circuit patterns.

It is preferable that a ground plan having a predetermined area is formed on the resin layer positioned at each outer periphery of the sub-strip, the ground plan is opened by a cover coat, and the ground plan is electrically connected to the ground ring. .

The coverlay tape may be adhered to one surface of the substrate forming the main strip. The coverlay tapes are preferably glued to each sub-strip individually. In addition, each coverlay tape is preferably bonded so that one side can cover up to a slot formed at the boundary between the sub-strip and the sub-strip.

According to the method of manufacturing a semiconductor package according to the present invention to achieve the above object, a plurality of through-holes are grouped in a row and a column spaced apart by a predetermined distance so that the semiconductor chip is positioned to form one sub-strip, The strip comprises: a resin layer in which a plurality of strips are connected to the slots penetrated at a predetermined length to form one main strip; Conductive circuit patterns including bond fingers and ball lands to be connected to semiconductor resins and connecting means later on the resin layers that are outer periphery of the through-holes in the respective sub-strips, and to further weld the conductive balls; Providing a substrate for a semiconductor package including a cover coat coated on the surface of the resin layer and the circuit pattern to open the bond finger and the ball land; Adhering a coverlay tape to one surface of each sub-strip so as to close all through holes formed in each sub-strip; Placing a semiconductor chip in each of the through holes and bonding the semiconductor chip onto the coverlay tape; Connecting the bond bonds formed at the outer circumference of the semiconductor chip and the through hole with electrical connection means; A molding step of filling the through hole with an encapsulant to protect the semiconductor chip, the connecting means, and the like from an external environment; Removing the coverlay tape from the substrate; Fusing conductive balls to ball lands formed at outer periphery of each through hole; And cutting the outer periphery of each through hole to singulate into a single semiconductor package.

In the step of attaching the coverlay tape, it is preferable to attach independent coverlay tapes to one surface of each sub-strip.

The step of attaching the coverlay tape is preferably bonded so that one side of the coverlay tape covers a slot formed in the boundary region between the sub-strip and the sub-strip.

Removing the coverlay tape may be performed by passing a punch through a slot formed in the boundary area between the sub-strip and the sub-strip so that one side of the coverlay tape is separated from the substrate.

As described above, according to the present invention for the semiconductor package substrate and the method for manufacturing the semiconductor package using the substrate, the substrate is a sub-strip having a plurality of through holes and a main strip having a plurality of sub-strips formed therein. It is possible to simultaneously implement dozens to hundreds of ultra-thin semiconductor packages in a single substrate.

In addition, by adhering independent coverlay tapes to each sub-strip, the warpage phenomenon due to the coefficient of thermal expansion appearing in proportion to the length is minimized to prevent various defects in the manufacturing process of the semiconductor package.

In addition, one end of the coverlay tape is separated by passing a punch between the sub-strip and the slot provided at the boundary area of the sub-strip during the manufacturing process of the semiconductor package, so that the work of removing the coverlay tape becomes easier and Minimize breakage.

In addition, since the ground ring and the ground plan are further formed on the substrates as described above, various problems such as breakage of the semiconductor chip due to temporary discharge of static electricity and breakage of circuit patterns of the substrates can be eliminated.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

1A and 1B are a plan view and a bottom view of a substrate 100 for a semiconductor package 200 according to the present invention, and FIG. 2 is a coverlay tape 24 bonded to one surface of the substrate 100. It is a bottom view which shows the state.

First, using a substantially rectangular resin layer 6 as a base material, a plurality of through holes 8 are arranged in rows and columns in a matrix shape so that a semiconductor chip (not shown) is located at a predetermined distance from each other. Clustered to form one sub-strip (2). Again, the sub-strips 2 are connected in the transverse direction with the slots 26 penetrating a predetermined length in the longitudinal direction to form one main strip 4.

On the surface of the resin layer 6, which is the outer periphery of the through-hole 8 in each sub-strip 2, the semiconductor chip 42 and the connecting means 44, for example, gold wire or aluminum wire are subsequently formed. A bond finger 12 is formed to be connected by an electrical connection means 44 such as a wire, and further connected to the bond finger 12 so that a conductive ball 48, for example, a solder ball, is fused. Borland 14 is formed. Here, the bond finger 12 and the ball land 14 are defined as conductive circuit patterns.

On the surface of the resin layer 6 and the circuit pattern, a cover coat 16 made of a polymer resin is coated so that the bond finger 12 and the ball land 14 are opened to the outside. 16 not only protects the circuit pattern from the external environment but also secures the overall strength of the substrate 100.

In addition, a conductive ground ring 18 having a substantially rectangular ring shape is formed in the resin layer 6, which is the outer circumference of each through hole 8, and the ground ring 18 is electrically connected to at least one circuit pattern. It is. In more detail, the ground ring 18 is formed on the opposite side of the surface on which the circuit pattern including the bond finger 12 and the borland 14 is formed, and the circuit pattern and the via hole (not shown). Is connected. Such a ground ring 18 improves the rigidity of the overall substrate 100 as well as the ground of the semiconductor chip 42. In addition, the ground ring 18 may be coated on the surface of the resin layer 6 with or without coating the surface of the cover coat 16, but it is only a choice of those skilled in the art.

In addition, a conductive ground plan 22 having a predetermined area is formed on the surface of the resin layer 6 positioned at the edge of the substrate 100, and the ground plan 22 is opened by a cover coat. It is also electrically connected to the ground ring 18. Unlike the ground ring 18, the ground plan 22 may be formed on both surfaces of the resin layer 6, and thus, the ground plan 22 may more easily discharge static electricity generated during the manufacturing process to the outside.

Here, the circuit pattern including the bond finger 12 and the borland 14, the ground ring 18 and the ground plan 22 is preferably formed of a copper (Cu) thin film, but limited to only the material Any conductive material may be used as long as it is a conductive material.

On the other hand, each of the sub-strips 2 can be further adhered to the coverlay tape 24 which is adhesive on one surface. That is, as shown in FIG. 2, a single coverlay tape 24 may be further adhered to one surface of each sub-strip 2. The coverlay tape 24 as described above may be attached to the entire surface of the main strip by having the same size as the main strip 4, but separated in order to alleviate the thermal expansion coefficient that increases in proportion to the length. Most preferably, the covered coverlay tape 24 is adhered to one surface of each sub-strip 2.

In addition, each coverlay tape 24 is preferably provided so that one side can cover up to a slot 26 formed at the boundary between the sub-strip 2 and the sub-strip 2. This is to facilitate the removal of the coverlay tape 24 in the semiconductor package 200 manufacturing process to be described later.

In the figure, reference numeral 28 is an index hole for loading and fixing the substrate 100 to various manufacturing equipment.

As described above, the substrate 100 for the semiconductor package 200 according to the present invention includes a sub-strip 2 having a plurality of through holes 8 and a main strip having a plurality of the sub-strips 2 formed therein. 4) it is possible to implement dozens to hundreds of ultra-thin semiconductor packages at the same time in one sub-stretch.

In addition, by adhering independent coverlay tapes 24 to each of the sub-strips 2, the warpage phenomenon due to the thermal expansion coefficient difference that is proportional to the length is minimized.

In addition, the coverlay tape 24 is designed to be easily removed, thereby minimizing the breakage of the substrate 100 during the removal work of the coverlay tape 24, and the ground ring 18 and the ground plan 22. Due to this, the rigidity of the substrate 100 is increased, and the influence of static electricity is minimized.

3A to 3H are sequential explanatory diagrams showing the manufacturing method of the semiconductor package 200 according to the present invention.

First, a plurality of through holes 8 are clustered in a row and a column spaced apart by a predetermined distance so that the semiconductor chip 42 is positioned to form one sub-strip 2, and the sub-strip 2 has a predetermined length. A resin layer 6 which is connected to a plurality of borders of the slots 26 penetrated to form one main strip 4; Bond fingers (10) are connected to the resin layer (6) outer periphery of the through holes (8) in each of the sub-strips (2) by the semiconductor chip (42) and the connecting means (44), and then by the conductive balls (48). 12) and a conductive circuit pattern including the borland 14; It provides a substrate 100 for semiconductor package comprising a cover coat 16 coated to open the bond finger 12 and the ball land 14 on the surface of the resin layer 6 and the circuit pattern. See FIGS. 1A, 1B and 3A)

The coverlay tape 24 is adhered to one surface of each sub-strip 2 of the substrate 100 so as to close all the through holes 8 formed in the sub-strip 2 (FIG. 3B).

Here, the coverlay tape 24 is preferably bonded to the one surface of the sub-strip 2 in an independent form. In other words, the coverlay tapes 24 are attached to each of the plurality of sub-strips 2 so that the coverlay tapes 24 have a predetermined interval. By doing so, the thermal expansion coefficient aberration which increases in proportion to the length is alleviated, thereby suppressing the warpage phenomenon of the substrate 100 during the semiconductor package 200 manufacturing process. In addition, the coverlay tape 24 is preferably bonded so that one side thereof covers the slot 26 formed in the boundary region between the sub-strip 2 and the sub-strip 2.

The semiconductor chip 42 is positioned in each through hole 8 formed in the substrate 100, and one surface thereof is adhered to the coverlay tape 24 (FIG. 3C).

The bond finger 12 formed at the outer circumference of the semiconductor chip 42 and the through hole 8 is connected by electrical connection means 44 such as gold wire or aluminum wire (FIG. 3D).

In order to protect the semiconductor chip 42, the connecting means 44, and the like from the external environment, the through hole 8 is formed of an encapsulant 46 such as an epoxy molding compound or a liquid encapsulant 46. Molding (Fig. 3e)

Conductive balls 48 such as solder balls are welded to the ball lands 14 formed at the outer periphery of the respective through holes 8 (FIG. 3F).

Remove the coverlay tape 24 from the substrate 100 (Fig. 3g).

At this time, the coverlay tape 24 is removed by passing the punch 32 through the slots 26 formed in the boundary area between the sub-strip 2 and the sub-strip 2, and thus, one side of the coverlay tape 24. The substrates 100 are separated and removed. By using the above method, the coverlay tape 24 adhered to one surface of all the sub-strips 2 can be easily removed.

The outer periphery of each through hole 8 is cut and singulated into a single semiconductor package 200 (FIG. 3H).

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.

As described above, according to the present invention for the semiconductor package substrate and the method for manufacturing the semiconductor package using the substrate, the substrate is a sub-strip having a plurality of through holes and a main strip having a plurality of sub-strips formed therein. It is effective to implement up to tens to hundreds of ultra-thin semiconductor packages at the same time in one substrain.

In addition, by adhering independent coverlay tapes to each sub-strip, it is possible to minimize warpage phenomena due to thermal expansion coefficient difference that is proportional to the length, thereby preventing various defects in the manufacturing process of the semiconductor package. There is.

In addition, one end of the coverlay tape is separated by passing a punch between the sub-strip and the slots provided at the boundary region of the sub-strip during the manufacturing process of the semiconductor package, thereby easily removing the coverlay tape. There is an effect that can minimize the damage of the substrate.

In addition, since the ground ring and the ground plan are further formed on the substrates as described above, various problems such as breakage of the semiconductor chip due to temporary discharge of static electricity and breakage of circuit patterns of the substrates can be eliminated.

Claims (11)

A plurality of through-holes are grouped in a row and a column spaced apart by a predetermined distance so that the semiconductor chip is positioned to form a sub-strip, and the sub-strips are connected to a plurality of slots through a predetermined length of one main main line. A resin layer forming a strip; A conductive circuit pattern including a bond finger and a ball land so as to be connected to one surface of the resin layer, which is the outer periphery of the through-holes in each of the sub-strips, by a semiconductor chip and a connecting means, and subsequently to bond the conductive balls; Substrates for semiconductor packages comprising a cover coat coated on the surface of the resin layer and the circuit pattern to open the bond finger and the ball land. 2. The substrate of claim 1, wherein a ground ring is further formed on an opposite surface of the resin layer on which the circuit pattern is formed. The substrate package of claim 2, wherein the ground ring is electrically connected to at least one circuit pattern. 3. The resin layer of claim 2, wherein a ground plan having a predetermined area is formed in the resin layer positioned at each outer periphery of the sub-strip, and the ground plan is opened by a cover coat, and the ground plan is connected to the ground ring. Substrate for a semiconductor package, characterized in that electrically connected. 2. The substrate of claim 1, wherein a coverlay tape is attached to one surface of the substrate forming the main strip. 5. The substrate of claim 4, wherein the coverlay tape is individually bonded to each sub-strip. 7. The substrate of claim 6, wherein each coverlay tape is bonded so that one side can cover a slot formed at a boundary between the sub-strip and the sub-strip. A plurality of through-holes are grouped in a row and a column spaced apart by a predetermined distance so that the semiconductor chip is positioned to form a sub-strip, and the sub-strips are connected to a plurality of slots through a predetermined length of one main main line. A resin layer forming a strip; A conductive circuit pattern including a bond finger and a ball land so as to be connected to one surface of the resin layer, which is the outer periphery of the through-holes in each of the sub-strips, by a semiconductor chip and a connecting means, and subsequently to bond the conductive balls; Providing a substrate for a semiconductor package including a cover coat coated on the surface of the resin layer and the circuit pattern to open the bond finger and the ball land; Adhering a coverlay tape to one surface of each sub-strip so as to close all through holes formed in each sub-strip; Placing a semiconductor chip in each of the through holes and bonding the semiconductor chip onto the coverlay tape; Connecting the bond bonds formed at the outer circumference of the semiconductor chip and the through hole with electrical connection means; A molding step of filling the through hole with an encapsulant to protect the semiconductor chip, the connecting means, and the like from an external environment; Removing the coverlay tape from the substrate; Fusing conductive balls to ball lands formed at outer periphery of each through hole; And cutting the outer periphery of each through hole to singulate the semiconductor package into a single semiconductor package. The method of claim 8, wherein the attaching the coverlay tape to each of the sub-strips comprises attaching independent coverlay tapes to each of the sub-strips. The method of claim 9, wherein the attaching of the coverlay tape comprises bonding one side of the coverlay tape to cover a slot formed in a boundary area between the sub-strip and the sub-strip. 10. The method of claim 8, wherein the coverlay tape removing step includes removing a coverlay tape by separating a side of the coverlay tape by passing a punch through a slot formed in a boundary area between the sub-strip and the sub-strip. Method of manufacturing a semiconductor package.