KR100357884B1 - circuit board for semiconductor package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for a semiconductor package, comprising: a resin layer for easily discharging static electricity accumulated in a semiconductor chip and a circuit board during a semiconductor package manufacturing process toward a corresponding equipment; A chip mounting part formed on the upper surface of the resin layer so that the semiconductor chip can be mounted on the resin layer; A circuit pattern including a plurality of bond fingers formed radially finely on the outer periphery of the chip mounting part and extending to an edge; A plurality of ball lands arranged such that conductive balls are fused later on the bottom surface of the resin layer; Conductive via holes connecting the circuit patterns on the upper surface of the resin layer and the ball lands on the lower surface of the resin layer; It is coated on the upper and lower surfaces of the resin layer to protect the circuit pattern from the external environment, the bond finger and the borland forms a predetermined unit including a cover coat to open to the outside, and the plurality of units are connected In a circuit board forming a strip, one side of the circuit board is formed with a common pattern connecting all the circuit patterns along the edge of each unit, the common pattern of each unit is connected to each other, A grounding means connected to the common pattern is formed in one of the units, and the grounding means is opened by a cover coat.

Description

Circuit board for semiconductor package {circuit board for semiconductor package}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board for a semiconductor package, and more particularly, to a circuit board for a semiconductor package that can easily discharge static electricity accumulated in a semiconductor chip, a circuit board, and the like during a semiconductor package manufacturing process to a corresponding device.

In general, a semiconductor package circuit board mounts a semiconductor chip to support and fix the same on a main board, and mediates a predetermined electrical signal between the semiconductor chip and the main board. In the semiconductor package circuit board, a plurality of units generally form one strip, and are transported and worked on the strip during the semiconductor package manufacturing process. Each circuit board unit has a circuit pattern including a bond finger and a ball land, usually formed on one or both surfaces of the thermosetting resin layer or film, on one or both surfaces thereof, and one or both surfaces thereof are cover coats. It is made of coating.

On the other hand, recently developed semiconductor chips usually have a low driving voltage and a small allowable error of the voltage, and have a fine circuit pattern, thereby assembling the semiconductor chips, for example, wire bonding. In the processes such as wire bonding, sealing, marking, ball bumping, and singulation, the semiconductor is discharged at a temporary time after static electricity is accumulated in the semiconductor chip, conductive wire, or circuit pattern. The problem of easily breaking chips and circuit boards frequently occurs.

Such temporary discharge of static electricity may occur in all processes, but may occur more frequently during the encapsulation process of a circuit board using a mold. That is, the polymer-based encapsulant rubs directly with a cover coat or conductive layer of a circuit board, such as a signal, a ground, an electric power, a semiconductor chip, or a conductive wire during the encapsulation process, thereby causing the circuit board, the semiconductor chip, or the like. Many static electricity is generated and accumulated. Such a circuit board must be removed from the mold to be put into the next process, and when the conductive part of the circuit board comes into contact with the mold or another material or equipment, the semiconductor chip or the circuit board is damaged due to a sudden discharge of static electricity. There is this.

In order to solve this problem, conventionally, a separate grounding means is provided for each circuit board unit.

The structure of the circuit board unit 2 or the strip 100 will be described with reference to FIGS. 3A and 3B as follows. Here, a printed circuit board is usually used as the base material of the resin layer 4 as an example.

First, the chip mounting portion 6 is formed in a substantially rectangular shape on the top surface of the resin layer 4 so that a semiconductor chip can be mounted, and radially fine, dense and bonded around the chip mounting portion 6 is formed. The conductive circuit pattern 12 including the finger 8 is formed. Between the circuit patterns 12, a gate 40, which is a passage through which an encapsulant flows from the edge of each circuit board unit 2 toward the chip mounting portion 6, is formed. The chip mounting portion 6 and the circuit pattern 12 on the upper surface of the resin layer 4 are coated with a cover coat 16, but the circuit pattern 12 electrically connected to the gate 40 and the semiconductor chip thereafter. The bond finger 8 is open without the cover coat 16 being coated. On the other hand, a conductive via hole 24 is formed in a predetermined region of the circuit pattern 12 from the top of the resin layer 4 toward the bottom, and is connected to the via hole 24 on the bottom surface of the resin layer 4. In the future, a plurality of ball lands 14 are formed in such a manner that the conductive balls are fused. In addition, the cover coat 16 is coated on the entire lower surface of the resin layer 4 except for the borland 14.

In the drawing, reference numeral 26 denotes a slot formed through a predetermined length between each circuit board unit 2 and the unit 2, and reference numeral 18 denotes a portion in which the circuit board strip 100 is cut into a single semiconductor package. The reference hole is a singulation hole, and reference numeral 22 is a guide pin hole used to fix or load a circuit board in various equipment.

Meanwhile, as shown in FIG. 3B, a grounding means having a predetermined area is further formed in each unit 2 in which a plurality of ball lands 14 are formed to discharge static electricity generated during a semiconductor package manufacturing process toward external equipment. When the circuit board is loaded into the equipment, the grounding means is grounded to the transport rail or seating part of the equipment.

Of course, the grounding means is connected to any one of the grounding circuit pattern 12 formed on the lower surface of the resin layer (4).

However, such grounding means must be formed for each unit 2 of the circuit board, and the area must be higher than the height of the cover coat 16 for the perfect grounding with the equipment because the area is relatively small. It is inconvenient to use one conductive pad 34a or attach another conductive pad 34a. In addition, when a warpage occurs in the circuit board strip 100, the grounding means formed in the circuit board unit 2 may not be completely grounded with the corresponding equipment. Thus, damage to the circuit board or the semiconductor chip may still occur due to static electricity. There is a problem.

Accordingly, the present invention has been made to solve the above-described problems, and provides a semiconductor package circuit board that can easily discharge the static electricity accumulated in the semiconductor chip and circuit board during the semiconductor package manufacturing process toward the equipment. have.

1A and 1B are a bottom view and a cross-sectional view showing a circuit board for a semiconductor package according to a first embodiment of the present invention.

2A and 2B are a bottom view and a cross-sectional view showing a circuit board for a semiconductor package according to a second embodiment of the present invention.

3A and 3B are a plan view and a bottom view of a circuit board for a conventional semiconductor package.

-Description of the main symbols in the drawings-

100; Circuit board strip 2; Circuit Board Unit

4; Resin layer 6; Chip loading department

8; Bond fingers 12; Circuit pattern

14; Ball land 16; Cover coat

18; Singulation hole

22; Guide pin hole

24; Via hole 26; Slot

32; Common pattern 34a; Conductive pads

34b; Plating layer 40; Gate

In order to achieve the above object, a semiconductor package circuit board according to the present invention comprises a resin layer; A chip mounting part formed on the upper surface of the resin layer so that the semiconductor chip can be mounted on the resin layer; A circuit pattern including a plurality of bond fingers formed radially finely on the outer periphery of the chip mounting part and extending to an edge; A plurality of ball lands arranged such that conductive balls are fused later on the bottom surface of the resin layer; Conductive via holes connecting the circuit patterns on the upper surface of the resin layer and the ball lands on the lower surface of the resin layer; It is coated on the upper and lower surfaces of the resin layer to protect the circuit pattern from the external environment, the bond finger and the borland forms a predetermined unit including a cover coat to open to the outside, and the plurality of units are connected In a circuit board forming a strip, one side of the circuit board is formed with a common pattern connecting all the circuit patterns along the edge of each unit, the common pattern of each unit is interconnected, the plurality of units The grounding means connected to the common pattern is formed in any one of the units, and the grounding means is opened by a cover coat.

The common pattern and the grounding means may be formed on both surfaces of the circuit board, that is, the upper and lower surfaces of the resin layer.

On the outer periphery of the chip mounting portion of the resin layer, a plurality of singulation holes may be formed so as to be a reference when singulating with a single semiconductor package later. In this case, a common pattern and a grounding means are formed outside the singulation hole. desirable.

The grounding means can be achieved by forming a conductive pad on either side of the resin layer.

A plurality of guide pin holes may be formed at each unit edge of the circuit board. In this case, a grounding means may be formed in the guide pin hole of any one of the units. Here, the grounding means is preferably realized by forming a plating layer on the inner wall of the guide pin hole.

As described above, according to the semiconductor package circuit board according to the present invention, a common pattern is formed by connecting all circuit patterns of the circuit board, that is, circuit patterns such as signals, ground, and power, and the common pattern is conductive. By connecting with a grounding means such as a plating layer formed in a pad or a guide pin hole, a grounding means is formed in only one unit of the circuit board without the need for forming a grounding means for each unit as in the conventional art. All of the static electricity induced on the back can be easily released to the equipment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

1A and 1B are a bottom view and a cross-sectional view showing a circuit board for a semiconductor package according to a first embodiment of the present invention.

The chip mounting part 6 is formed on the upper surface of the resin layer 4 so that the semiconductor chip can be mounted on the upper surface of the resin layer 4, and the radially finely formed on the outer periphery of the chip mounting part 6. Thus, a plurality of signal, ground or power circuit patterns 12 extending to the edges are formed. Here, a bond finger 8 is formed in the circuit pattern 12 adjacent to the chip mounting part 6. A plurality of ball lands 14 are formed on the bottom surface of the resin layer 4 so that the conductive balls are fused later, and the circuit patterns 12 on the top surface of the resin layer 4 and the ball lands 14 on the bottom surface of the resin layer 4 are formed. ) Are interconnected by conductive via holes 24. A plurality of circuit patterns 12 are also formed on the bottom surface of the resin layer 4, which is mainly the circuit pattern 12 for grounding. The cover coat 16 is coated on the upper and lower surfaces of the resin layer 4 to protect the circuit pattern 12 from the external environment, and the bond finger 8 and the borland 14 are opened to the outside. A unit 2 is formed, and a plurality of units 2 are connected to form a series of strips 100. In addition, on the outer periphery of the chip mounting portion 6 of each unit 2, a number of singulation holes 18, which are used as a reference when singulating with a single semiconductor package in the future, are formed, and at the edge of each unit 2, A plurality of guide pin holes 22 for loading and fixing the circuit board are formed, and this structure is the same as in the prior art.

Meanwhile, as a gist of the present invention, a common pattern 32 is further formed on one surface of the circuit board to connect all the circuit patterns 12 along the edge of each unit 2. That is, as shown in the drawing, all the ground circuit patterns 12 formed on the bottom surface of the circuit board may be connected by the common pattern 32. Although not shown in the drawing, the common pattern 32 is formed on the top surface of the circuit board. All circuit patterns 12 for signal, ground, and power can be connected.

In addition, the common pattern 32 is formed in all the units 2, and all of the common patterns 32 of the units 2 are connected. In addition, any one unit 2 of the unit 2 is connected to the common pattern 32 is further formed with a grounding means, which is formed on the upper or lower surface of the circuit board, selectively forming one, upper, lower surface It can also be formed in all. In addition, it is natural that the grounding means is opened by the cover coat 16 for easy grounding with the corresponding equipment.

In addition, each circuit board unit 2 may be provided with a singulation hole 18 that becomes a reference when singulating with a single semiconductor package later, in which case the common pattern 32 and the grounding means are singulated. It is preferable to form outside the ration hole 18. Therefore, after singulation into a single semiconductor package, the common pattern 32 and the grounding means are removed from the circuit board, so that all the signal, ground, and power circuit patterns 12 formed on the circuit board are electrically separated. It is not shorted.

Meanwhile, as shown in FIGS. 1A and 1B, the grounding means may be a conductive pad 34a having a predetermined thickness on one side of a circuit board unit 2. The area of the conductive pad 34a may be arbitrarily changed by those skilled in the art and may be formed in a substantially rectangular shape on one side of the planar circuit board unit 2 as shown in the drawing. The thickness of the conductive pad 34a is preferably higher than the thickness of the circuit pattern 12, that is, the height of the cover coat 16. However, the thickness of the conductive pad 34a may be equal to or greater than the thickness of the circuit pattern 12. Even if the height is smaller than 16), there is no problem in contact with the equipment.

In addition, the greatest feature of the present invention has the advantage that the grounding means can always be formed in the same position in common to the circuit board having the same outer size regardless of the type or size of the semiconductor package to be manufactured, if necessary A dummy region for electrical contact may be further formed at one end of the substrate.

In addition, the grounding means, that is, the conductive pad 34a and a means for contacting the conductive pad 34a in the equipment may be formed, for example, a conductive protrusion for perfect grounding of the equipment.

Meanwhile, the grounding means may be formed in the guide pin hole 22 as in the second embodiment of the present invention shown in FIGS. 2A and 2B. That is, the guide pin hole 22 is inserted into and fixed to the metallic fixing pin of the equipment when the circuit board is loaded on the equipment, and the plating layer 34b having a predetermined thickness on the inner wall of the guide pin hole 22. By forming the static electricity is to be released to the equipment through the fixing pin. Of course, the plating layer 34b formed in the guide pin hole 22 is naturally connected to the common pattern 32.

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention. That is, in the embodiment of the present invention, the resin layer as the center layer, the circuit pattern is formed on both sides, the cover coat is coated on both sides as an example, but the circuit pattern is formed only on one side with the film as the center layer It may also be applicable to circuit films coated with a cover coat on only one side.

Thus, according to the semiconductor package circuit board according to the present invention, a common pattern is formed by connecting all circuit patterns of the circuit board, that is, circuit patterns such as signals, ground, and power, and the common pattern is a conductive pad. Or by connecting to a ground means such as a plated layer formed in the guide pin hole, there is no need to form a ground means for each unit of the circuit board as in the prior art, all the circuits in the circuit board strip through the ground means formed in any one of the unit There is an effect that the static electricity that can be accumulated in the substrate unit is easily released toward the equipment.

Claims (6)

A resin layer; A chip mounting part formed on the upper surface of the resin layer so that the semiconductor chip can be mounted on the resin layer; A circuit pattern including a plurality of bond fingers formed radially finely on the outer periphery of the chip mounting part and extending to an edge; A plurality of ball lands arranged such that conductive balls are fused later on the bottom surface of the resin layer; Conductive via holes connecting the circuit patterns on the upper surface of the resin layer and the ball lands on the lower surface of the resin layer; It is coated on the upper and lower surfaces of the resin layer to protect the circuit pattern from the external environment, the bond finger and the borland forms a predetermined unit including a cover coat to open to the outside, and the plurality of units are connected In a circuit board forming a strip, One side of the circuit board is formed with a common pattern connecting all the circuit patterns along the edge of each unit, the common pattern of each unit is interconnected, the common pattern to any one of the plurality of units The connected grounding means is formed, and the grounding means is a circuit board for a semiconductor package, characterized in that open by the cover coat. The semiconductor package circuit board of claim 1, wherein the common pattern and the grounding means are formed on both surfaces of the resin layer. According to claim 1 or claim 2, wherein the outer periphery of the chip mounting portion of the resin layer is formed with a plurality of singulation holes as a reference when the singulation in a single semiconductor package later, a common pattern on the outside of the singulation hole And a grounding means formed thereon. The semiconductor package circuit board according to claim 1 or 2, wherein the grounding means is a conductive pad formed on one surface of the resin layer. The semiconductor package according to claim 1 or 2, wherein a plurality of guide pin holes are formed at each unit edge of the circuit board, and a grounding means is formed in the guide pin hole of any one of the units. Circuit board. The semiconductor package circuit board of claim 5, wherein the grounding means is a plating layer formed on an inner wall of the guide pin hole.