KR100400673B1 - printed circuit board for semiconductor package - Google Patents
printed circuit board for semiconductor package Download PDFInfo
- Publication number
- KR100400673B1 KR100400673B1 KR10-1999-0037924A KR19990037924A KR100400673B1 KR 100400673 B1 KR100400673 B1 KR 100400673B1 KR 19990037924 A KR19990037924 A KR 19990037924A KR 100400673 B1 KR100400673 B1 KR 100400673B1
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- resin layer
- circuit board
- printed circuit
- chip mounting
- mounting portion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
이 발명은 반도체패키지용 인쇄회로기판에 관한 것으로, 제조 공정중 인쇄회로기판, 반도체칩 및 도전성와이어 등에 발생하는 정전기를 금형쪽으로 용이하게 방출하도록 수지층과; 상기한 수지층의 상면에 차후 반도체칩이 탑재될 수 있도록 형성된 칩탑재부와; 상기한 칩탑재부의 외주연에 방사상으로 미세하게 형성되어 가장자리까지 연장된 다수의 회로패턴과; 상기한 수지층의 하면에 차후 도전성볼이 융착되도록 어레이(array) 되어 형성된 다수의 볼랜드와; 상기한 수지층 상면의 회로패턴과 수지층 하면의 볼랜드를 연결하는 도전성 비아홀과; 상기 수지층의 상,하면에 코팅되어 회로패턴을 외부환경으로부터 보호하고, 볼랜드는 외부로 오픈되도록 하는 솔더마스크로 이루어진 인쇄회로기판에 있어서, 상기 칩탑재부와 대향하는 수지층의 저면에는 봉지 공정중 금형과 접지가능하게 솔더마스크에 의해 오픈된 접지수단이 더 형성된 것을 특징으로 함.The present invention relates to a printed circuit board for a semiconductor package, comprising: a resin layer so as to easily discharge static electricity generated in a printed circuit board, a semiconductor chip, conductive wire, etc. to a mold during a manufacturing process; A chip mounting portion formed on the upper surface of the resin layer so that the semiconductor chip can be mounted on the resin layer; A plurality of circuit patterns formed radially finely on the outer periphery of the chip mounting part and extending to an edge; A plurality of ball lands formed to be arrayed so that conductive balls are fused to the lower surface of the resin layer; Conductive via holes connecting the circuit patterns on the upper surface of the resin layer and the ball lands on the lower surface of the resin layer; A printed circuit board comprising a solder mask coated on upper and lower surfaces of the resin layer to protect a circuit pattern from an external environment and open to a borland, wherein the bottom surface of the resin layer facing the chip mounting part is encapsulated. A grounding means opened by a solder mask to be grounded with a mold is further formed.
Description
본 발명은 반도체패키지용 인쇄회로기판에 관한 것으로, 더욱 상세하게 설명하면 제조 공정중 인쇄회로기판, 반도체칩 및 도전성와이어 등에 발생하는 정전기를 금형쪽으로 용이하게 방출할 수 있는 반도체패키지용 인쇄회로기판에 관한 것이다.The present invention relates to a printed circuit board for a semiconductor package, and more particularly, to a printed circuit board for a semiconductor package that can easily discharge static electricity generated in a printed circuit board, a semiconductor chip, and conductive wires to a mold during the manufacturing process. It is about.
통상 반도체패키지용 인쇄회로기판은 반도체칩을 탑재하여 마더보드상에 지지 및 고정하고, 그 반도체칩과 마더보드 사이에서 소정의 전기적 신호를 매개해주는 역할을 한다. 이러한 반도체패키지용 인쇄회로기판은 통상 다수의 유닛이 하나의 스트립을 이루며, 반도체패키지 제조 공정 중에는 상기 스트립채로 이송 및 작업된다. 상기 각각의 인쇄회로기판 유닛은 통상 열경화성 수지층을 중심으로 그 양면에 구리박막으로 된 도전성 회로패턴 및 볼랜드 등이 형성되어 있고, 양표면은 솔더마스크 등으로 코팅되어 이루어져 있다.In general, a printed circuit board for a semiconductor package includes a semiconductor chip, which is supported and fixed on a motherboard, and serves to mediate a predetermined electrical signal between the semiconductor chip and the motherboard. Such a printed circuit board for a semiconductor package usually includes a plurality of units in one strip, and is transported and worked on the strip during the semiconductor package manufacturing process. Each of the printed circuit board units is usually formed with a conductive circuit pattern made of a copper thin film, a borland, and the like on both sides of a thermosetting resin layer, and both surfaces are coated with a solder mask or the like.
도5는 통상적인 반도체패키지용 인쇄회로기판을 도시한 평면도이고, 도6a 내지 도7b는 통상적인 반도체패키지용 인쇄회로기판의 저면도 및 요부 단면도로서, 이를 이용하여 그 구조를 설명하면 다음과 같다.FIG. 5 is a plan view showing a conventional printed circuit board for semiconductor packages, and FIGS. 6A to 7B are bottom and main cross-sectional views of a conventional printed circuit board for semiconductor packages, and the structure thereof will be described below. .
먼저 수지층(3)을 중심으로, 그 상면에는 반도체칩이 실장될 수 있도록 대략 사각판 모양으로 칩탑재부(8)가 형성되어 있고, 상기 칩탑재부(8)의 주변에는 방사상으로 미세하고 촘촘한 도전성 회로패턴(10)이 형성되어 있다. 상기 회로패턴(10) 사이에는 상기 칩탑재부(8) 또는 회로패턴(10)중 접지용 회로패턴과 연결된 동시에 각 인쇄회로기판 유닛(2)의 가장자리에서부터 칩탑재부(8)를 향하여 봉지재가 흘러 들어가는 통로인 골드게이트(40)가 형성되어 있다. 상기 수지층(3) 상면의 칩탑재부(8) 및 회로패턴(10)은 솔더마스크(6)로 코팅되어 있되, 상기 골드게이트(40) 및 차후 반도체칩과 전기적으로 접속되는 회로패턴(10)의 단부는 솔더마스크(6)가 코팅되지 않고 오픈(open)되어 있다. 한편, 상기 회로패턴(10)중 일정영역에는 수지층(3)의 상부에서 하부를 향하여 도전성 비아홀(12)이 형성되어 있고, 상기 비아홀(12)에 연결된 채 상기 수지층(3)의 하면에는 차후 도전성볼이 융착되도록 다수의 볼랜드(14)가 형성되어 있다. 또한 상기 칩탑재부(8) 저면에도 도전성 비아홀(12)과 연결된 도전성 더미플레이트(5)가 형성되어 있으며, 볼랜드(14)를 제외한수지층 하면 전체 즉, 상기 더미플레이트(5)를 포함하는 저면 전체는 솔더마스크(6)로 코팅되어 있다.First, the chip mounting portion 8 is formed in a substantially square plate shape so that the semiconductor chip can be mounted on the upper surface of the resin layer 3, and the radially fine and dense conductivity is formed around the chip mounting portion 8. The circuit pattern 10 is formed. The encapsulant flows toward the chip mounting portion 8 from the edge of each printed circuit board unit 2 while being connected to the chip mounting portion 8 or the circuit pattern 10 among the circuit patterns 10 between the circuit patterns 10. The gold gate 40 which is a passage is formed. The chip mounting portion 8 and the circuit pattern 10 on the upper surface of the resin layer 3 are coated with a solder mask 6, but the circuit pattern 10 is electrically connected to the gold gate 40 and the semiconductor chip. The ends of the solder mask 6 are open without being coated. The conductive via hole 12 is formed in a predetermined region of the circuit pattern 10 from the top of the resin layer 3 toward the bottom thereof, and is connected to the via hole 12 on the bottom surface of the resin layer 3. Afterwards, a plurality of ball lands 14 are formed to weld the conductive balls. In addition, a conductive dummy plate 5 connected to the conductive via hole 12 is formed on the bottom surface of the chip mounting part 8, and the entire bottom surface of the resin layer except for the borland 14, that is, the entire bottom surface including the dummy plate 5. Is coated with a solder mask (6).
한편, 도7a 및 도7b에 도시된 바와 같이 상기 인쇄회로기판에는 더미플레이트 대신 그라운드용 볼랜드(14a)가 다수 형성될 수도 있다. 이때 마찬가지로 상기 그라운드용 볼랜드(14a)는 칩탑재부(8) 또는 신호용 회로패턴(10)과 도전성비아홀(12) 등에 의해 연결되어 있다.As shown in FIGS. 7A and 7B, a plurality of ground ball lands 14a may be formed on the printed circuit board instead of the dummy plate. At this time, the ground borland 14a is connected to the chip mounting portion 8 or the signal circuit pattern 10 and the conductive via hole 12.
도면중 미설명 부호 22는 각 인쇄회로기판 유닛(2)과 유닛(2) 사이에 일정 길이로 관통되어 형성된 슬롯이고, 미설명 부호 18은 상기 인쇄회로기판 스트립(100)이 낱개의 반도체패키지로 절단될 때 기준이 되는 싱귤레이션홀이며, 부호 16은 각종 장비에 인쇄회로기판을 고정시키거나 로딩시킬때 이용되는 인덱스홀이다.In the drawing, reference numeral 22 denotes a slot formed to penetrate through each printed circuit board unit 2 and the unit 2 with a predetermined length, and reference numeral 18 denotes the printed circuit board strip 100 as a single semiconductor package. It is a singulation hole that becomes a reference when cutting, and reference numeral 16 is an index hole used when fixing or loading a printed circuit board to various equipment.
한편, 최근에 개발되는 반도체칩은 통상 구동 전압이 낮고 또한 허용되는 전압의 오차가 작으며, 회로패턴이 미세하게 형성되어 있음으로써, 반도체칩을 어셈블링(assembling)하는 공정 예를 들면, 와이어 본딩(wire bonding), 봉지(molding), 마킹(marking), 볼 범핑(ball bumping), 싱귤레이션(singulation)과 같은 공정에서 반도체칩이나 인쇄회로기판에 정전기가 축적된 후 일시에 방전되어 반도체칩 및 인쇄회로기판을 쉽게 파손시키는 문제가 빈번히 발생하고 있다.On the other hand, recently developed semiconductor chips usually have a low driving voltage and a small allowable error of the voltage, and have a fine circuit pattern, thereby assembling the semiconductor chips, for example, wire bonding. in the process of wire bonding, molding, marking, ball bumping, singulation, etc. The problem of easily breaking a printed circuit board frequently occurs.
이러한 대용량의 정전기 방전 현상은 모든 공정에서 발생 가능하지만, 특히 금형을 이용한 인쇄회로기판의 봉지 공정중 더욱 빈번히 발생한다. 즉, 폴리머 계열인 봉지재가 봉지 공정중 인쇄회로기판의 솔더마스크나 도전층(예를 들면, 신호용, 접지용 및 파워용 등의 회로패턴), 반도체칩 또는 도전성와이어와 직접 마찰하게 됨으로써, 상기 인쇄회로기판이나 반도체칩 등에 정전기가 발생 및 축적된다. 이러한 인쇄회로기판은 다음 공정에 투입하기 위해 금형에서 빼내어야 하는데, 이때 상기 금형이나 다른 자재에 그 인쇄회로기판의 도전성 부분이 접촉하게 되면 갑작스런 정전기의 방전으로 반도체칩이나 인쇄회로기판이 파손되는 문제점이 있다.Such a large amount of electrostatic discharge may occur in all processes, but especially more frequently during the encapsulation process of a printed circuit board using a mold. That is, the polymer-based encapsulant rubs directly with a solder mask or a conductive layer (for example, a circuit pattern such as a signal, a ground, and a power), a semiconductor chip, or a conductive wire of the printed circuit board during the encapsulation process, thereby printing Static electricity is generated and accumulated in circuit boards and semiconductor chips. Such a printed circuit board should be removed from the mold to be put into the next process. At this time, if the conductive part of the printed circuit board comes into contact with the mold or another material, the semiconductor chip or the printed circuit board will be damaged by the sudden discharge of static electricity. There is this.
따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 봉지 작업시 인쇄회로기판, 반도체칩 및 도전성와이어 등에 발생하는 정전기를 금형쪽으로 용이하게 방출할 수 있는 반도체패키지용 인쇄회로기판을 제공하는데 있다.Accordingly, the present invention has been made to solve the conventional problems as described above, a semiconductor package printed circuit board that can easily discharge the static electricity generated in the printed circuit board, semiconductor chip and conductive wire to the mold during the sealing operation To provide.
도1a 및 도1b는 본 발명의 제1실시예인 반도체패키지용 인쇄회로기판을 도시한 저면도 및 요부 단면도이다.1A and 1B are a bottom view and a sectional view showing main parts of a printed circuit board for a semiconductor package according to a first embodiment of the present invention.
도2a 및 도2b는 본 발명의 제2실시예인 반도체패키지용 인쇄회로기판을 도시한 저면도 및 요부 단면도이다.2A and 2B are bottom and main cross-sectional views showing a printed circuit board for a semiconductor package according to a second embodiment of the present invention.
도3은 본 발명에 의한 인쇄회로기판을 사용한 반도체패키지 자재가 금형에 접지되는 상태를 도시한 상태도이다.3 is a state diagram showing a state in which a semiconductor package material using a printed circuit board according to the present invention is grounded to a mold.
도4는 본 발명에 의한 인쇄회로기판을 사용한 반도체패키지가 마더보드에 실장되는 한 예를 도시한 단면도이다.4 is a cross-sectional view showing an example in which a semiconductor package using a printed circuit board according to the present invention is mounted on a motherboard.
도5는 통상적인 반도체패키지용 인쇄회로기판을 도시한 평면도이다.5 is a plan view showing a conventional printed circuit board for a semiconductor package.
도6a 내지 도7b는 통상적인 반도체패키지용 인쇄회로기판의 저면도 및 요부 단면도이다.6A to 7B are bottom and main cross-sectional views of a conventional printed circuit board for a semiconductor package.
- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-
100; 인쇄회로기판 2; 인쇄회로기판 유닛(unit)100; Printed circuit board 2; Printed Circuit Board Unit
3; 수지층 5; 더미플레이트(dummy plate)3; Resin layer 5; Dummy plate
6; 솔더마스크(solder mask) 8; 칩탑재부6; Solder mask 8; Chip loading department
10; 회로패턴 12; 비아홀(via hole)10; Circuit pattern 12; Via hole
14,14a; 볼랜드(ball land)14,14a; Ball land
16; 인덱스홀(index hole)16; Index hole
18; 싱귤레이션홀(singulation hole) 22; 슬롯(slot)18; Singulation hole 22; Slot
36; 싱귤레이션라인(singulation line) 40; 골드게이트(gold gate)36; Singulation line 40; Gold gate
51; 도전성볼(ball) 52; 솔더(solder)51; Conductive ball 52; Solder
53; 반도체칩 54; 도전성와이어(wire)53; Semiconductor chip 54; Conductive Wire
55; 봉지재 71; 접지용 플레이트(plate)55; Encapsulant 71; Ground Plate
72; 접지용 링(ring) M; 금형72; Ground ring M; mold
MB; 마더보드(mother board)MB; Motherboard
상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지용 인쇄회로기판은 수지층과; 상기한 수지층의 상면에 차후 반도체칩이 탑재될 수 있도록 형성된 칩탑재부와; 상기한 칩탑재부의 외주연에 방사상으로 미세하게 형성되어 가장자리까지 연장된 다수의 회로패턴과; 상기한 수지층의 하면에 차후 도전성볼이 융착되도록 어레이(array)되어 형성된 다수의 볼랜드와; 상기한 수지층 상면의 회로패턴과 수지층 하면의 볼랜드를 연결하는 도전성 비아홀과; 상기 수지층의 상, 하면에 코팅되어 회로패턴을 외부환경으로부터 보호하고, 볼랜드는 외부로 오픈되도록 하는 솔더마스크로 이루어진 인쇄회로기판에 있어서, 상기 칩탑재부와 대향하는 수지층의 저면에는 봉지 공정중 금형과 접지가능하게 솔더마스크에 의해 오픈된 접지수단이 더 형성된 것을 특징으로 한다.In order to achieve the above object, a printed circuit board for a semiconductor package according to the present invention comprises a resin layer; A chip mounting portion formed on the upper surface of the resin layer so that the semiconductor chip can be mounted on the resin layer; A plurality of circuit patterns formed radially finely on the outer periphery of the chip mounting part and extending to an edge; A plurality of ball lands formed by being arrayed so that conductive balls are fused to the bottom surface of the resin layer; Conductive via holes connecting the circuit patterns on the upper surface of the resin layer and the ball lands on the lower surface of the resin layer; A printed circuit board comprising a solder mask coated on upper and lower surfaces of the resin layer to protect a circuit pattern from an external environment and opening a borland to the outside, wherein the bottom surface of the resin layer facing the chip mounting part is encapsulated. A grounding means opened by a solder mask to be grounded with a mold is further formed.
여기서, 상기 접지수단은 대략 사각판 모양의 접지용 플레이트로 할 수 있고, 상기 접지용 플레이트는 대략 칩탑재부와 같은 면적을 갖도록 형성함이 바람직하다. 여기서, 상기 수지층을 중심으로 그 상면에는 칩탑재부가 그 하면에는 접지용 플레이트가 비슷한 면적으로 형성됨으로써 결국 인쇄회로기판이 어느 한쪽으로 휘어지는 워페이지 현상을 억제하게 된다.Here, the grounding means may be a grounding plate in a substantially rectangular plate shape, the grounding plate is preferably formed to have an area substantially the same as the chip mounting portion. Here, the chip mounting portion is formed on the upper surface of the resin layer, and the grounding plate is formed on the lower surface of the lower surface, thereby suppressing the warpage phenomenon in which the printed circuit board is bent to either side.
상기 접지수단은 대략 사각링 형상을 하는 접지용 링으로 할 수도 있고, 상기 접지용 링은 대략 칩탑재부의 내주연을 따라 이루는 링 형상으로 함이 바람직하다.The grounding means may be a grounding ring having a substantially rectangular ring shape, and the grounding ring is preferably a ring shape formed along an inner circumference of the chip mounting part.
상기 접지수단은 적어도 솔더마스크와 동일평면이거나 더 돌출되도록 형성함이 바람직하다.Preferably, the grounding means is formed to be at least coplanar with the solder mask or to protrude further.
상기와 같이 하여 본 발명에 의한 반도체패키지용 인쇄회로기판에 의하면 칩탑재부와 대응하는 수지층 저면에 솔더마스크에 의해 오픈된 접지수단이 더 형성됨으로써, 봉지 공정중 자연스럽게 금형과 접촉되고 따라서 인쇄회로기판이나 반도체칩 등에 발생되는 정전기가 금형쪽으로 모두 방출됨으로써, 제조 공정중 인쇄회로기판이나 반도체칩 등의 파손을 미연에 방지할 수 있게 된다.As described above, according to the printed circuit board for a semiconductor package according to the present invention, the grounding means opened by the solder mask is further formed on the bottom surface of the resin layer corresponding to the chip mounting portion, thereby naturally contacting the mold during the encapsulation process and thus the printed circuit board. Since all the static electricity generated in the semiconductor chip or the like is released to the mold, damage to the printed circuit board or the semiconductor chip can be prevented in advance during the manufacturing process.
이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.
도1a 및 도1b는 본 발명의 제1실시예인 반도체패키지용 인쇄회로기판(100)을도시한 저면도 및 요부 단면도이고, 도2a 및 도2b는 본 발명의 제2실시예인 반도체패키지용 인쇄회로기판(100)을 도시한 저면도 및 요부 단면도이다.1A and 1B are a bottom view and a cross-sectional view of a main portion of a printed circuit board 100 for a semiconductor package according to a first embodiment of the present invention, and FIGS. 2A and 2B are printed circuits for a semiconductor package according to a second embodiment of the present invention. It is a bottom view and main part cross section which show the board | substrate 100.
종래와 같이 수지층(3)을 기본층으로 그 상면에는 차후 반도체칩이 탑재될 수 있도록 칩탑재부(8)가 형성되어 있고, 상기 칩탑재부(8)의 외주연으로는 방사상의 회로패턴(10)이 형성되어 있다. 상기한 수지층(3)의 하면에는 차후 도전성볼(51)이 융착되도록 다수의 도전성 볼랜드(14)가 형성되어 있고, 상기 수지층(3) 상면의 회로패턴(10)과 수지층(3) 하면의 볼랜드(14)는 도전성 비아홀(12)로 연결되어 있다. 또한, 상기 수지층(3)의 상, 하면에 코팅되어 회로패턴(10)을 외부 환경으로부터 보호하고 볼랜드(14)는 외부로 오픈되도록 솔더마스크(6)가 코팅되어 있으며, 이와 같은 구조는 종래와 동일하다.As in the prior art, a chip mounting portion 8 is formed on the upper surface of the resin layer 3 to form a semiconductor chip on the upper surface thereof. A radial circuit pattern 10 is formed on the outer circumference of the chip mounting portion 8. ) Is formed. A plurality of conductive borland 14 is formed on the bottom surface of the resin layer 3 so that the conductive balls 51 are fused later, and the circuit pattern 10 and the resin layer 3 on the top surface of the resin layer 3 are formed. Borland 14 on the bottom surface is connected to conductive via hole 12. In addition, the solder layer 6 is coated on the upper and lower surfaces of the resin layer 3 to protect the circuit pattern 10 from the external environment and the borland 14 is opened to the outside. Is the same as
한편, 본 발명은 상기 칩탑재부(8)와 대향하는 수지층(3)의 저면에 봉지 공정중 금형(M)과 접지 및 접촉 가능하게 솔더마스크(6)에 의해 오픈된 접지수단이 더 형성되어 있다. 상기 접지수단은 칩탑재부(8)와 비아홀(12)에 의해 연결되어 있으며, 도시되지 않은 신호용 또는 접지용 회로패턴과도 연결되어 있음은 물론이다.On the other hand, the present invention is further formed on the bottom surface of the resin layer (3) facing the chip mounting portion 8 is further formed with a grounding means opened by the solder mask 6 to the ground and contact with the mold (M) during the sealing process have. The grounding means is connected by the chip mounting portion 8 and the via hole 12, and is also connected to the signal or ground circuit pattern not shown.
상기 접지수단은 도1a 및 도1b에 도시된 바와 같이 대략 사각판 모양을 하는 접지용 플레이트(71)로 구비할 수 있다. 이때 상기 접지용 플레이트(71)의 두께는 칩탑재부(8)와 같거나 더 두껍게 형성하고, 또한 면적은 대략 비슷하게 형성함이 바람직하다. 여기서 상기 접지용 플레이트(71)의 두께는 도금을 몇 회에 걸쳐 실시했는가에 따라서 결정된다.The grounding means may be provided as a grounding plate 71 having a substantially square plate shape as shown in FIGS. 1A and 1B. At this time, the thickness of the grounding plate 71 is the same as or thicker than the chip mounting portion 8, and the area is preferably formed to be approximately similar. The thickness of the grounding plate 71 is determined by how many times the plating is performed.
또한, 상기 접지용 플레이트(71)는 솔더마스크(6)와 동일평면을 이루도록 할수 있으나, 금형(M)과의 접촉성을 향상시키기 위해 상기 솔더마스크(6)보다 약간 더 돌출되도록 형성함이 바람직하다.In addition, the grounding plate 71 may be formed on the same plane as the solder mask 6, but may be formed to protrude slightly more than the solder mask 6 in order to improve contact with the mold M. Do.
도2a 및 도2b에 도시된 바와 같이 상기 접지수단은 대략 사각링 형상을 하는 접지용 링(72)으로 구비할 수도 있다. 이때, 상기 접지용 링(72)은 대략 칩탑재부(8)의 내주연을 따라 이루는 사각링 형상으로 함이 바람직하다. 또한 상기 접지용 링(72)의 두께는 칩탑재부(8)의 두께와 같게 하거나 또는 더 두껍게 할 수 있다. 더불어 금형(M)과의 접촉성이 양호하도록 솔더마스크(6)와 동일평면을 이루도록 하거나 또는 더 돌출되도록 형성함이 바람직하다.As shown in Figures 2a and 2b, the grounding means may be provided as a grounding ring 72 having a substantially rectangular ring shape. At this time, the ground ring 72 is preferably in the shape of a rectangular ring formed along the inner circumference of the chip mounting portion (8). In addition, the thickness of the ground ring 72 may be equal to or thicker than the thickness of the chip mounting portion 8. In addition, it is preferable to form the same plane as the solder mask 6 or to further protrude so that contact with the mold M is good.
도3은 본 발명에 의한 인쇄회로기판(100)을 사용한 반도체패키지 자재가 금형(M)에 접지 및 접촉되는 상태를 도시한 상태도이다. 도시된 바와 같이 인쇄회로기판(100)의 칩탑재부(8)와 대응하는 수지층(3)의 저면에는 솔더마스크(6)와 동일평면을 이루거나 더 돌출된 접지수단이 형성됨으로써, 이 접지수단이 금형(M)에 밀착됨을 알 수 있다. 따라서 봉지 공정중 봉지재(55)와 반도체칩, 인쇄회로기판 등과의 마찰로 발생하는 정전기가 상기 접지수단을 통하여 금형(M)으로 용이하게 방출된다.3 is a state diagram showing a state in which the semiconductor package material using the printed circuit board 100 according to the present invention is grounded and in contact with the mold (M). As shown, a grounding means is formed on the bottom surface of the chip mounting portion 8 of the printed circuit board 100 and the resin layer 3 corresponding to the solder mask 6 to form the same plane or protrude more. It turns out that it contacts with this metal mold | die M. Therefore, the static electricity generated by the friction between the encapsulant 55, the semiconductor chip, and the printed circuit board during the encapsulation process is easily discharged to the mold M through the grounding means.
한편, 도4는 본 발명에 의한 인쇄회로기판(100)을 사용한 반도체패키지가 마더보드(MB)에 실장되는 한 예를 도시한 단면도이다. 도시된 바와 같이 반도체패키지를 마더보드(MB)에 실장시에는 인쇄회로기판(100)에 형성된 접지수단과 마더보드(MB) 사이에 솔더(52)를 형성함으로써, 반도체패키지의 열적 성능을 보다 향상시킬 수 있게 된다. 즉, 상기 솔더(52)를 통하여 반도체패키지에서 발생하는열이 마더보드(MB)로 전달되지 때문이다.4 is a cross-sectional view showing an example in which a semiconductor package using a printed circuit board 100 according to the present invention is mounted on a motherboard MB. As shown in the drawing, when the semiconductor package is mounted on the motherboard MB, solder 52 is formed between the grounding means formed on the printed circuit board 100 and the motherboard MB, thereby further improving the thermal performance of the semiconductor package. You can do it. That is, heat generated in the semiconductor package is transferred to the motherboard MB through the solder 52.
도면중 미설명 부호 53은 반도체칩, 54는 도전성와이어, 51은 도전성볼, 55는 봉지재이다.In the figure, reference numeral 53 is a semiconductor chip, 54 is a conductive wire, 51 is a conductive ball, and 55 is an encapsulant.
이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.
따라서 본 발명에 의한 반도체패키지용 인쇄회로기판에 의하면, 칩탑재부와 대응하는 수지층 저면에 솔더마스크에 의해 오픈된 접지수단이 더 형성됨으로써, 봉지 공정중 자연스럽게 금형과 접촉되고 따라서 인쇄회로기판이나 반도체칩 등에 발생되는 정전기가 금형쪽으로 모두 방출됨으로써, 제조 공정중 인쇄회로기판이나 반도체칩 등의 파손을 미연에 방지할 수 있는 효과가 있다.Therefore, according to the printed circuit board for a semiconductor package according to the present invention, the ground means opened by the solder mask is further formed on the bottom surface of the resin layer corresponding to the chip mounting portion, thereby naturally contacting the mold during the encapsulation process, and thus the printed circuit board or the semiconductor. Since all the static electricity generated in the chip or the like is released to the mold, damage to the printed circuit board or the semiconductor chip during the manufacturing process can be prevented in advance.
더불어, 상기 인쇄회로기판을 이용한 반도체패키지는 마더보드에 실장시 솔더를 통하여 대량의 열이 마더보드쪽으로 흐르도록 함으로써 열적 성능이 향상되는 효과도 있다.In addition, the semiconductor package using the printed circuit board has an effect of improving the thermal performance by allowing a large amount of heat to flow to the motherboard through the solder when mounted on the motherboard.
Claims (5)
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| US10032706B2 (en) | 2015-09-11 | 2018-07-24 | Samsung Electronics Co., Ltd. | Package substrates |
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| JPH10214928A (en) * | 1996-02-27 | 1998-08-11 | Ibiden Co Ltd | Printed wiring board |
| KR19980044243A (en) * | 1996-12-06 | 1998-09-05 | 황인길 | Printed Circuit Board Strips for Semiconductor Packages |
| JPH1168006A (en) * | 1997-08-19 | 1999-03-09 | Mitsubishi Electric Corp | Lead frame, semiconductor device provided therewith, and manufacture of them |
-
1999
- 1999-09-07 KR KR10-1999-0037924A patent/KR100400673B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08172158A (en) * | 1994-12-20 | 1996-07-02 | Toppan Printing Co Ltd | Printed wiring board |
| JPH10214928A (en) * | 1996-02-27 | 1998-08-11 | Ibiden Co Ltd | Printed wiring board |
| KR19980044243A (en) * | 1996-12-06 | 1998-09-05 | 황인길 | Printed Circuit Board Strips for Semiconductor Packages |
| JPH1168006A (en) * | 1997-08-19 | 1999-03-09 | Mitsubishi Electric Corp | Lead frame, semiconductor device provided therewith, and manufacture of them |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10032706B2 (en) | 2015-09-11 | 2018-07-24 | Samsung Electronics Co., Ltd. | Package substrates |
| US10256181B2 (en) | 2015-09-11 | 2019-04-09 | Samsung Electronics Co., Ltd. | Package substrates |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010026561A (en) | 2001-04-06 |
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