KR20000043213A - Method for forming transistor of semiconductor device - Google Patents
Method for forming transistor of semiconductor device Download PDFInfo
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- KR20000043213A KR20000043213A KR1019980059563A KR19980059563A KR20000043213A KR 20000043213 A KR20000043213 A KR 20000043213A KR 1019980059563 A KR1019980059563 A KR 1019980059563A KR 19980059563 A KR19980059563 A KR 19980059563A KR 20000043213 A KR20000043213 A KR 20000043213A
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- Prior art keywords
- forming
- gate electrode
- trench
- semiconductor device
- transistor
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000010354 integration Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체소자의 트랜지스터 형성방법에 관한 것으로, 특히 초저접합 ( shallow junction ) 을 구현하기 위한 소오스/드레인 형성시, 선택적인 에피택셜 성장 ( selective epitaxial growth, 이하에서 SEG라 함 ) 방법을 이용하지 않고 게이트지역을 약간 식각하여 용이하게 엘리베이티드된 소오스/드레인( elevated source/drain ) 접합영역을 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and in particular, does not use a selective epitaxial growth (SEG) method when forming a source / drain for implementing a shallow junction. And etching the gate region slightly to form an elevated source / drain junction region.
반도체 메모리 소자가 고집적화됨에따라 더 얇은 깊이의 초저접합을 요구하게 되었다.As semiconductor memory devices become more integrated, ultra-low junctions of thinner depths are required.
그러나, 낮은 에너지를 이용한 이온주입공정과 RTP 방법으로는 그 한계가 있다.However, there are limitations in the ion implantation process and the RTP method using low energy.
이러한 문제점을 해결하기 위하여, SEG 기술 개발을 서두르고 있으나, 상기 SEG 기술은 아직도 완전히 개발되지않았을 정도로 그 공정이 까다롭고, 기술개발이 완성되었다 하더라도 고가의 장비를 도입해야 하며 SEG 성장을 필요로 하는 부분을 제외한 다른 부분의 실리콘을 제거한 다음 실시하여야 하는 공정상의 문제점이 있다.In order to solve this problem, the development of SEG technology is rushing, but the process is so difficult that the SEG technology is still not fully developed, and even if the technology development is completed, expensive equipment must be introduced and the part requiring SEG growth. There is a problem in the process to be carried out after removing the silicon of the other parts except.
그리하여, SEG 기술이 완성되었어도 실제 소자나 제품에 적용하기에는 많은 시간이 걸릴 것으로 생각되어 반도체소자의 고집적화를 어렵게 하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키기 못하는 문제점이 있다.Therefore, even if the SEG technology is completed, it is considered to take a long time to apply to the actual device or product, there is a problem that it is difficult to high integration of the semiconductor device and thereby improve the characteristics and reliability of the semiconductor device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 게이트전극이 형성되는 부분의 반도체기판을 식각하여 트렌치를 형성하고 그 상부에 게이트전극을 형성함으로써 소오스/드레인 접합영역이 엘리베이트된 형상의 트랜지스터를 형성하여 반도체소자의 고집적화를 가능하게 하는 반도체소자의 트랜지스터 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, a transistor having a source / drain junction region is elevated by etching a semiconductor substrate in a portion where a gate electrode is formed to form a trench and forming a gate electrode thereon. It is an object of the present invention to provide a method for forming a transistor of a semiconductor device which can be formed to enable high integration of the semiconductor device.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도.1A to 1D are cross-sectional views showing a transistor forming method of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 소자분리막1: semiconductor substrate 2 device isolation film
3 : 희생산화막 4 : 게이트산화막3: sacrificial oxide film 4: gate oxide film
5 : 게이트전극용 도전체 6 : 저농도의 불순물 접합영역5: conductor for gate electrode 6: low concentration impurity junction region
7 : 스페이서 8 : 고농도의 불순물 접합영역7 spacer 8 high concentration impurity junction region
10 : 감광막패턴 20 : 트렌치10 photosensitive film pattern 20 trench
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 트랜지스터 형성방법은,In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
소자분리막이 형성된 반도체기판 상부에 게이트전극이 형성될 부분을 노출시키는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the semiconductor substrate on which the device isolation film is formed to expose a portion where the gate electrode is to be formed;
상기 감광막패턴을 마스크로하여 상기 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the semiconductor substrate using the photoresist pattern as a mask;
상기 감광막패턴을 제거하는 공정과,Removing the photoresist pattern;
상기 트렌치의 중앙부에 게이트절연막과 게이트전극용 도전체의 적층구조로 패터닝된 게이트전극을 형성하는 공정과,Forming a gate electrode patterned with a stacked structure of a gate insulating film and a conductor for a gate electrode in a central portion of the trench;
상기 게이트전극을 마스크로 하는 이온주입공정으로 저농도의 불순물 접합영역을 형성하는 공정과,Forming a low concentration impurity junction region by an ion implantation process using the gate electrode as a mask;
상기 게이트전극 측벽에 스페이서를 형성하는 공정과,Forming a spacer on sidewalls of the gate electrode;
상기 게이트전극과 스페이서를 마스크로 하는 이온주입공정으로 고농도의 불순물 접합영역을 형성함으로써 LDD 구조를 가지며 엘리베이트된 소오스/드레인 접합영역이 구비되는 트랜지스터를 형성하는 공정을 포함하는 것과,Forming a transistor having an LDD structure and having an elevated source / drain junction region by forming an impurity junction region having a high concentration by an ion implantation process using the gate electrode and the spacer as a mask;
상기 감광막패턴은 게이트전극의 100 - 200 퍼센트 넓이로 구비되는 것과,The photoresist pattern may be provided with a width of 100 to 200 percent of the gate electrode,
상기 트렌치는 습식식각이나 플라즈마를 이용한 건식식각공정으로 형성되는 것과,The trench is formed by a dry etching process using wet etching or plasma,
상기 트렌치는 1 - 2000 Å 깊이로 형성되는 것과,The trench is formed to a depth of 1-2000 mm 3,
상기 스페이서는 200 - 1000 Å 의 산화막이나 질화막으로 형성하는 것을 특징으로 한다.The spacer is formed of an oxide film or a nitride film of 200-1000 Å.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는,On the other hand, the principle of the present invention for achieving the above object,
게이트전극이 형성될 지역에 트렌치를 형성하여 게이트전극이 형성될 부분을 낮게 함으로써 자연적으로 엘리베이트된 소오스/드레인 접합영역을 형성하고, 반도체기판의 손상을 최소화하기 위하여 상기 트렌치를 습식식각공정으로 형성하거나 희생산화막 공정으로 식각후 손상된 층을 제거하는 공정으로 반도체소자의 고집적화에 필요한 트랜지스터를 형성하는 것이다.By forming a trench in the region where the gate electrode is to be formed to lower the portion where the gate electrode is to be formed, a naturally-elevated source / drain junction region is formed, and the trench is formed by a wet etching process to minimize damage to the semiconductor substrate. A process of removing a damaged layer after etching by using a sacrificial oxide process is to form a transistor necessary for high integration of a semiconductor device.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 는 본 발명의 실시예에 따른 반도체소자의 트랜지스터 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a transistor forming method of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(1)의 비활성영역에 트렌치형 소자분리막(2)을 형성한다.First, a trench type isolation layer 2 is formed in an inactive region of the semiconductor substrate 1.
그리고, 상기 반도체기판(1) 상부에 게이트전극에 형성된 부분을 노출시키는 감광막패턴(3)을 형성한다.A photoresist pattern 3 is formed on the semiconductor substrate 1 to expose a portion formed on the gate electrode.
이때, 상기 감광막패턴(10)은 후속공정으로 형성될 게이트전극의 100 - 200 퍼센트 넓이로 디자인된 노광마스크를 이용하여 노광 및 현상하여 형성한다. (도 1a)In this case, the photoresist pattern 10 is formed by exposure and development using an exposure mask designed to be 100-200 percent wide of the gate electrode to be formed in a subsequent process. (FIG. 1A)
그 다음에, 상기 감광막패턴(10)을 마스크로하여 상기 반도체기판(1)의 활성영역을 식각하여 트렌치(20)를 형성한다.Next, the trench 20 is formed by etching the active region of the semiconductor substrate 1 using the photoresist pattern 10 as a mask.
이때, 상기 트렌치(20)는 습식식각이나 플라즈마를 이용한 건식식각으로 1 - 2000 Å 깊이를 갖도록 형성한다.In this case, the trench 20 is formed to have a depth of 1 to 2000 μs by wet etching or dry etching using plasma.
그 다음, 상기 감광막패턴(10)을 제거하고, 상기 트렌치(20)을 포함한 반도체기판(1) 표면에 희생산화막(3)을 열산화공정으로 형성한다. (도 1b)Next, the photoresist pattern 10 is removed and a sacrificial oxide film 3 is formed on the surface of the semiconductor substrate 1 including the trench 20 by a thermal oxidation process. (FIG. 1B)
그리고, 상기 희생산화막(3)을 제거하여 반도체기판(1)의 표면 손상을 최소화된 상태로 형성한다.The sacrificial oxide film 3 is removed to minimize surface damage of the semiconductor substrate 1.
그 다음에, 상기 트렌치(20)를 포함한 전체표면상부에 게이트산화막(4)과 게이트전극용 도전체(5)를 각각 일정두께 형성한다.Next, a gate oxide film 4 and a gate electrode conductor 5 are formed to a predetermined thickness on the entire surface including the trench 20, respectively.
그리고, 게이트전극마스크(도시안됨)를 이용한 식각공정으로 상기 게이트전극용 도전체(5)와 게이트산화막(4)을 식각하여 상기 트렌치(20)의 중앙부에 게이트전극을 형성한다.In addition, the gate electrode conductor 5 and the gate oxide film 4 are etched by an etching process using a gate electrode mask (not shown) to form a gate electrode in the center of the trench 20.
그리고, 상기 게이트전극을 마스크로하여 상기 반도체기판(1)에 저농도의 불순물이온을 주입하여 저농도의 불순물 접합영역(6)을 형성한다. (도 1c)A low concentration of impurity junction regions 6 are formed by implanting a low concentration of impurity ions into the semiconductor substrate 1 using the gate electrode as a mask. (FIG. 1C)
그 다음에, 전체표면상부에 스페이서용 절연막을 증착하고 이를 이방성식각하여 상기 게이트전극 측벽에 스페이서(7)를 형성한다. 이때, 상기 스페이서(7)는 200 - 1000 Å 의 산화막이나 질화막으로 형성한다.Next, an insulating film for a spacer is deposited on the entire surface and anisotropically etched to form a spacer 7 on the sidewall of the gate electrode. At this time, the spacer 7 is formed of an oxide film or a nitride film of 200-1000 Å.
그리고, 상기 게이트전극과 그 측벽에 형성된 스페이서(7)를 마스크로 하여 상기 반도체기판(1)에 고농도의 불순물 이온을 이온주입하여 고농도의 불순물 접합영역(8)을 형성함으로써 LDD 구조의 소오스/드레인 접합영역(6,8)이 엘리베이트된 형상의 트랜지스터가 형성된다. (도 1d)A high concentration of impurity junction regions 8 are formed by ion implanting high concentrations of impurity ions into the semiconductor substrate 1 using the spacers 7 formed on the gate electrode and sidewalls as masks to form a source / drain of LDD structure. Transistors having a shape in which the junction regions 6 and 8 are elevated are formed. (FIG. 1D)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 트랜지스터 형성방법은, 게이트전극이 형성될 부분의 활성영역을 식각하여 트렌치를 형성하고 여기에 게이트전극을 형성함으로써 기판 표면에 형성된 불순물 접합영역이 엘리베이트된 형상을 가지게 되어 반도체소자의 고집적화에 충분한 트랜지스터를 형성할 수 있는 효과가 있다.As described above, in the method of forming a transistor of the semiconductor device according to the present invention, the trench is formed by etching the active region of the portion where the gate electrode is to be formed, and the impurity junction region formed on the surface of the substrate is elevated by forming the gate electrode. It has an effect that can form a transistor sufficient for high integration of the semiconductor device.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980059563A KR100327659B1 (en) | 1998-12-28 | 1998-12-28 | Transistor Formation Method of Semiconductor Device |
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| KR1019980059563A KR100327659B1 (en) | 1998-12-28 | 1998-12-28 | Transistor Formation Method of Semiconductor Device |
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| KR100327659B1 KR100327659B1 (en) | 2002-08-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040025071A (en) * | 2002-09-18 | 2004-03-24 | 아남반도체 주식회사 | Mosfet of semiconductor device and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248135A (en) * | 1987-04-03 | 1988-10-14 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0456279A (en) * | 1990-06-25 | 1992-02-24 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH0818042A (en) * | 1994-06-30 | 1996-01-19 | Sony Corp | Method for manufacturing mos transistor |
| JPH0837196A (en) * | 1994-07-21 | 1996-02-06 | Murata Mfg Co Ltd | Semiconductor device |
| JPH10173072A (en) * | 1996-12-09 | 1998-06-26 | Sony Corp | Semiconductor device and manufacture thereof |
| JPH11297987A (en) * | 1998-04-10 | 1999-10-29 | Sony Corp | Semiconductor device and manufacture thereof |
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1998
- 1998-12-28 KR KR1019980059563A patent/KR100327659B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040025071A (en) * | 2002-09-18 | 2004-03-24 | 아남반도체 주식회사 | Mosfet of semiconductor device and manufacturing method thereof |
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| Publication number | Publication date |
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| KR100327659B1 (en) | 2002-08-21 |
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