KR20000020840A - Lcd with plane driving method - Google Patents

Abstract

PURPOSE: An LCD with plane driving method is provided to prevent a short of a wire by forming a first to a third data wires. CONSTITUTION: A gate line(20) is horizontally formed on a transparent insulating substrate(100). A gate pad(22) is formed at end side of the a gate. A common electrode(10) is horizontally formed with the gate line(20). A plurality of common electrodes(11,12) are vertically formed for receiving a common signal from the common electrode(10). A gate insulating film(30) is covered with gate wires(20,21,22) and common electrodes(10,11,12). A semiconductor layer(40) is formed on the gate insulating film(30). Resistor contacting layers(51,52) are formed on the semiconductor layer(40) on the axis of the gate electrode(21). A source electrode(61) and a drain electrode(62) are formed on resistor contacting layers. The source electrode(61) is vertically formed on the gate insulating film(30) and connected to a first data line(60). The drain electrode(62) is connected to a pixel electrode(65).

Description

Flat Drive Liquid Crystal Display

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device of a planar driving method and a manufacturing method thereof.

A liquid crystal display device mainly used at present is a twisted nematic (TN) type liquid crystal display device. In the twisted nematic method, electrodes are installed on two substrates, the liquid crystal directors are arranged to be twisted by 90 °, and a voltage is applied to the electrodes to drive the liquid crystal directors. However, such a liquid crystal display device has a problem that the viewing angle is narrow, and an in-plane switching (IPS) type liquid crystal display device has been developed to replace the liquid crystal display device. This prior art is shown in US Pat. No. 5,598,285.

However, the liquid crystal display device disclosed in US Pat. No. 5,598,285 has the following problems.

Due to the difference between the two electrodes for applying the horizontal electric field, that is, the common electrode and the pixel electrode, rubbing of the alignment layer formed on the electrode is nonuniform, resulting in a light leakage phenomenon in this portion, resulting in a low contrast ratio.

In addition, an unwanted potential difference is generated between the pixel electrode and the data line applying a voltage to the pixel electrode, so that light leaks in this portion, and the light is directly visible from the side, which is a side effect of cross talk. Cause. As a method of removing such a phenomenon, a method of widening a black matrix formed to block light leaking at a boundary of a pixel region or narrowing a gap between a common electrode and a data line has been proposed. However, it is difficult to completely block leakage of light, and when the black matrix is formed wide, the aperture ratio decreases, and when the gap between the common electrode and the data line is narrowed, the two wirings are frequently shorted.

In addition, at the end of the wiring, there is a pad portion exposed to the outside to receive a signal. When the wiring is formed of low-resistance aluminum, the exposed aluminum is easily oxidized, and electrical contact is poor at this portion. .

In addition, it is difficult to repair in the event of disconnection of the wiring, and there is no repairable method.

An object of the present invention is to eliminate the light leakage phenomenon in a flat drive type liquid crystal display device.

Another object of the present invention is to reduce the disconnection of the wiring and to prevent the short circuit of the data line and the common electrode.

Another object of the present invention is to improve the aperture ratio and to reduce the defect of the pad portion.

1 is a layout view illustrating a liquid crystal display device of a planar driving method according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1,

3 is a cross-sectional view taken along line III-III of the thin film transistor unit of FIG. 1;

4 and 5 are cross-sectional views of the gate pad portion IV-IV and the data pad portion V-V line in FIG. 1, respectively.

In the liquid crystal display device substrate according to the present invention for solving this problem, a gate line is formed on a transparent insulating substrate, and first, second, and third data lines insulated and intersected through the gate line and the first insulating film are formed. It is. In this case, the first and second data lines are formed side by side with the second insulating film interposed therebetween, and they are connected to each other through the first contact hole formed in the second insulating film. In addition, a common electrode and a pixel electrode are formed in the pixel area defined by the intersection of the gate line and the data line at regular intervals, and the common electrode adjacent to the second data line has the second data with the first and second insulating layers interposed therebetween. It overlaps the line.

In this structure, the second data line is preferably an opaque metal. Since the second data line overlaps the common electrode adjacent to each other and blocks light passing through the portion, the second data line and the common electrode replace the black matrix.

In addition, first and second insulating layers are formed between the common electrode and the second data line overlapping each other, so that short circuits thereof are reduced, and short circuits thereof are formed by forming the first, second and third data lines.

In addition, an auxiliary gate line which is separated from the second and third data lines and overlaps with the gate line and the first or second insulating layer therebetween is further formed. The auxiliary gate line may be shorted with the gate line when the disconnection occurs in the gate line to repair the disconnected gate line.

In the liquid crystal display according to the present invention, a gate electrode connected to the gate line, a source electrode connected to the first or second data line, and a pixel electrode are connected to a portion where the gate line and the first and second data lines cross each other. A thin film transistor formed of a drain electrode is formed. The first and second data pads connected to the ends of the first and second data lines, respectively, are connected through a second contact hole formed in the second insulating layer, and the third and second data pads are connected to the gate pad connected to the gate line. The auxiliary gate pad is connected through the contact hole.

In this case, the pads formed on the upper side among the first, second, and third data pads, the gate pads, and the auxiliary gate pads may be formed of chromium, molybdenum, molybdenum alloy, or ITO in order to secure electrical contact reliability. In addition, the gate line and the first and second data lines are preferably formed of aluminum, aluminum alloy, molybdenum, molybdenum alloy, etc., which are low-resistance metals, and the third data line is formed of chromium, molybdenum, molybdenum alloy, or ITO having high fire resistance. It is good to form.

Next, embodiments of the planar driving type liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

1 is a layout view of a liquid crystal display device of a planar driving method according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and FIG. 3 is a thin film transistor unit of FIG. 1. It is sectional drawing along the III-III line. 4 and 5 are cross-sectional views of the gate pad portion IV-IV and the data pad portion V-V line in FIG. 1, respectively.

1 to 5, the gate line 20 is formed in the horizontal direction on the lower transparent insulating substrate 100, and the gate pad 22 is formed at the end of the gate line 20. Part of the gate line 20 becomes the gate electrode 21. The common electrode line 10 is formed in parallel with the gate line 20, and a plurality of common electrodes 11 are connected to the common electrode line 10 in the pixel area to receive a common signal from the common electrode line 10. , 12) is formed in the longitudinal direction. Here, various conductive materials may be used as the metals for the gate wirings 20, 21, 22 and the common wirings 10, 11, and 12, and chromium, aluminum, aluminum alloys, molybdenum, molybdenum alloys, or the like. It is also possible to form a double layer combining these metals.

The gate insulating film 30 made of silicon nitride or the like is covered on the gate wirings 20, 21, 22 and the common wirings 10, 11, 12.

The semiconductor layer 40 of the thin film transistor made of amorphous silicon is formed on the gate insulating layer 30 on the gate electrode 21 in an island shape, and the amorphous silicon layer 40 is heavily doped with phosphorus (P) on the amorphous silicon layer 40. The ohmic contacts 51 and 52 made of silicon are formed on both sides of the gate electrode 21.

A source electrode 61 and a drain electrode 62 made of metal are formed on the ohmic contact layers 51 and 52, respectively, and the source electrode 61 is formed on the gate insulating layer 30 in the vertical direction. The drain electrode 62 is connected to the pixel electrode 65 which is linearly formed alternately with the common electrode 11 in the pixel area. A data pad 63 for receiving an image signal from the outside is formed at the end of the first data line 60. As shown in FIGS. 1 and 2, the first data line 60 has a common electrode 12 adjacent thereto. It is formed inside.

In this case, the first data wires 60, 61, 62, 63, and 65 may be formed of a metal layer such as chromium or an aluminum alloy, molybdenum, or molybdenum alloy, and may be thinly formed to a thickness of about 1,000 kPa or less. . This is because the light leakage phenomenon can be reduced by reducing the step difference between the layers due to the pixel electrode 65 to suppress the unevenness of the alignment generated in the rubbing process.

The gate electrode 21, the gate insulating layer 30, the amorphous silicon layer 40, the ohmic contact layers 51 and 52, the source and drain electrodes 61 and 62 form a thin film transistor, and the thin film transistor and the remaining first The protective film 70 covering the data wires 60, 61, 62, 63, 65 is made of silicon nitride or the like.

In the passivation layer 70, contact holes 71 and 73 exposing portions of the first data line 60 and the data pad 63 are formed, respectively, and the gate insulating layer 30 and the passivation layer 70 are provided with gate pads. The contact hole 72 which exposes a part of 22 is formed.

On the passivation layer 70, second data wires 80 and 83 having a metal pattern in the same shape as the first data wires 60 and 63 and made of an opaque metal are formed, and the second data wires 80 and 83 are formed on the passivation layer 70. The first data wires 60 and 63 are connected to each other through the contact holes 71 and 73 formed in the protective film 70. In addition, an auxiliary gate pad 82 connected to the gate pad 22 is formed on the gate pad 22 through the contact hole 72 formed in the passivation layer 70 and the gate insulating layer 30. The auxiliary gate line 81 is formed on the passivation layer 70 on the gate line 20 and is separated from the second data line 80. As shown in FIG. 2, both edge portions of the second data line 80 overlap with the two common electrodes 12 adjacent thereto. Accordingly, the second data line 80 and the common electrode 12 adjacent to the second data line 80 block light leaking from the portion adjacent to the second data line 80 and replace the black data. In addition, as shown in FIG. 2, since the passivation layer 70 and the gate insulating layer 30 are formed between the second data line 80 and the common electrode 12 adjacent thereto, a short circuit occurring between them is significantly reduced. . In addition, when disconnection occurs in the gate line 20 overlapping the auxiliary gate line 81, the disconnected gate line 20 may be repaired by connecting the auxiliary gate line 81 and the gate line 20. In addition, contact holes may be added to the passivation layer 70 and the gate insulating layer 70 to directly connect them. In this case, the second data lines 80, 81, 82, and 83 may be formed of a single layer or a multilayer of aluminum, molybdenum, molybdenum alloy, or aluminum alloy having low resistance, and may be added with chromium in the case of forming a multilayer. have. In this case, in consideration of the second data pad 83 and the auxiliary gate pad 82, it is preferable to form chromium, molybdenum, molybdenum alloy, etc., which can have reliability as the pad part, as an upper layer. In addition, since the second data wirings 80, 81, and 82 83 are formed in portions other than the pixel region, the thickness of the second data wirings 80, 81, and 82 is less than that of the pixel electrode 65 layer. It is lowered and made to be suitable for a fixed tax and a big screen.

Here, the pixel area is an area defined by the intersection of the gate line 20 and the first and second data lines 60 and 80.

Further, third data wires 90, 92, and 93 are formed on the second data wires 80, 82, and 83. Of course, another auxiliary gate line formed on the same layer as the third data line may be added on the auxiliary gate line 81, or only one of the two may be selectively formed. Here, although the third data wires 90, 92, and 93 cover the second data lines 80, 82, and 83, the third data wires 90, 92, and 93 may pass through the second data wires 80, 82, and 93. 83). Here, the reason for further forming the third data wires 90, 92, and 93 is as follows. As the screen of the liquid crystal display grows larger, wiring has to use a material having a lower resistance to reduce signal delay. Therefore, the second data line 80 is formed of aluminum, aluminum alloy, molybdenum or molybdenum alloy which is a low resistance metal material. At this time, the second data lines 82 and 83 of the pad portion are also formed of such a metal material. However, when the pad is formed of molybdenum or molybdenum alloy, the molybdenum or molybdenum alloy is easily corroded when reacted with moisture, thereby lowering the process yield. In addition, when the pad is formed of aluminum or an aluminum alloy, the metal itself is fragile, and disconnection and damage frequently occur. Therefore, the third data wires 90, 92 and 93 are preferably formed of a single film of chromium or ITO having excellent fire resistance or multiple films thereof, and more preferably using ITO as the upper film. At this time, the stacking order of the second data wires 80, 82, 83 and the third data wires 90, 92, 93 may be changed. In this case, the upper portion of the pad portion is preferably formed of chromium or ITO, and may be formed of a double layer having ITO as an upper layer.

Meanwhile, the black matrix 900 is formed in the horizontal direction on the upper transparent insulating substrate 200. Here, both edge portions of the black matrix 900 are formed to overlap the common electrode line 10 of the lower substrate 100.

In this case, in the liquid crystal display according to the present invention, the black matrix in the vertical direction does not need to be formed, so that the opening in the horizontal direction increases in the pixel area, thereby improving the aperture ratio.

In the embodiment of the present invention, the second data line 80 is used to block the light leaking with the common electrode 12 and the first data line 60 is stepped at a portion crossing the gate line 20. However, disconnection may be prevented, but such a function may be provided to the first data line by forming the first data line wider than the second data line.

In addition, unlike the above-described embodiment, the pixel electrode and the source / drain electrode may be formed when the second and third data lines are formed. In this case, it is advantageous to form the thickness of the pixel electrode at about 1,000 GPa or less in terms of preventing light leakage. On the other hand, in this case, since the metal forming the pixel electrode forms a pad portion, it is formed of a single film made of chromium, ITO, etc., which can be reliable as the pad portion, or aluminum, aluminum alloy having low resistance on these single films. , A metal film made of molybdenum or molybdenum alloy may be added.

As in the embodiment of the present invention, the wirings can be prevented from being disconnected by forming the first, second, and third data wirings, and it can be repaired when the gate lines are disconnected by adding the auxiliary gate lines. . In addition, by using the second data line and the common electrode adjacent thereto as the second data line and the light blocking film, light leakage may be eliminated, and the aperture ratio may be improved, and the pad portion may be improved with a refractory metal. In addition, short circuits between the data line and the common electrode can be prevented, and by adding a third data wire, a low resistance of the wire and a large liquid crystal display device can be fabricated, and process yield can be improved through reliability of the pad part.

Claims (26)

A plurality of gate lines formed parallel to each other on a transparent substrate, First and second data lines which are insulated from and cross the gate line, are formed side by side with a first insulating film interposed therebetween, and are connected to each other through a first contact hole of the first insulating film; A third data line connected to the second data line and formed in the same pattern as the second data line; A common electrode formed in a plurality of pixel areas defined by intersections of the gate line and the first, second and third data lines; A pixel electrode formed to face the common electrode at a predetermined interval in the pixel area; And a thin film transistor having a gate electrode, a source electrode, and a drain electrode connected to the gate line, the first, second or third data line, and the pixel electrode. In claim 1, And a liquid crystal display in which the first, second or third data line and the common electrode overlap each other at a boundary of the pixel region. In claim 2, A first data pad formed of the same metal layer as the first data line and connected to the first data line, a second data pad formed of the same metal layer as the second data line and connected to the second data line, and the third data pad; And a third data pad formed of the same metal layer as the data line and connected to the third data line. The first data pad and the second data pad are connected to each other through a second contact hole of the first insulating layer, and the second data pad and the third data pad are in contact with each other. In claim 3, And a layer formed on the upper side of the first, second and third data pads made of chromium or ITO. In claim 4, The liquid crystal display of claim 1, further comprising a layer made of ITO on an upper portion of the first, second, and third data pads. In claim 1, A gate pad formed at an end of the gate line, and And an auxiliary gate pad formed of the same metal layer as the first, second or third data line and connected to the gate pad through a third contact hole formed in the first insulating layer. In claim 6, The auxiliary gate pad is made of chromium or ITO. In claim 7, And a layer made of ITO on the auxiliary gate pad. In claim 1, And at least one of the first, second or third data lines is formed in the same layer as the pixel electrode. In claim 9, The pixel electrode has a thickness of 1,000 mW or less. In claim 1, And a second insulating layer between the common electrode and the second and third data lines. In claim 11, And the first and second insulating layers are formed between the common electrode and the second and third data lines. In claim 1, The common electrode and the gate line are formed of the same metal layer. In claim 1, And an auxiliary gate line separated from the first, second and third data lines and overlapping the gate line. The method of claim 14, A second insulating film is further included between the gate line and the auxiliary gate line. And a third contact hole formed in the first and second insulating films. In claim 1, And a common electrode line formed in parallel with the gate line and commonly connecting the plurality of common electrodes. The method of claim 16, And a black matrix overlapping the gate line and the common electrode line. Board, A gate line formed on the substrate and a gate electrode connected to the gate line; A linear common electrode formed separately from the gate line on the substrate, A gate insulating film covering the gate line, the gate electrode, and the common electrode, An amorphous silicon layer formed on the gate insulating film on the gate electrode, An ohmic contact layer formed on both sides of the gate electrode on the amorphous silicon layer; Source and drain electrodes respectively formed on the ohmic contact layer; A first data line formed on the gate insulating layer and connected to the source electrode; A linear pixel electrode alternately formed with the common electrode on the gate insulating layer of the pixel region defined by the intersection of the gate line and the data line, and connected to the drain electrode; A passivation layer covering the source and drain electrodes, the data line, and the pixel electrode and having a first contact hole exposing the data line; A second data line formed on the passivation layer and electrically connected to the data line through the first contact hole and overlapping the common electrode on both adjacent sides; A third data line formed on the second data line; And at least one pixel electrode and at least one common electrode in each pixel area. The method of claim 18, A first data pad formed at an end of the first data line; A second data pad formed at an end of the second data line, and A third data pad formed at an end of the third data line; The passivation layer has a second contact hole such that the first data pad and the second data pad are electrically connected to each other through the second contact hole, and the third data pad is connected to the second data pad. Liquid crystal display. The method of claim 19, The third data pad includes a layer made of chromium or ITO. The method of claim 20, And the second data line is formed of aluminum, an aluminum alloy, molybdenum, or molybdenum alloy. The method of claim 21, A gate pad formed at an end of the gate line, Further comprising an auxiliary gate pad made of a metal layer, such as the second or third data line, And the gate insulating layer and the passivation layer have a third contact hole for exposing the gate pad so that the gate pad and the auxiliary gate pad are electrically connected through the third contact hole. The method of claim 22, The auxiliary gate pad includes a layer made of ITO. The method of claim 23, And an auxiliary gate line formed on an upper portion of the passivation layer and separated from a second or third data line and overlapping the gate line. The method of claim 24, And the gate insulating layer and the passivation layer have a fourth contact hole exposing the gate line, and the gate line and the auxiliary gate line are connected through the fourth contact hole. The method of claim 25, The pixel electrode has a thickness of 1,000 mW or less.