KR100299687B1 - LCD Display - Google Patents

Abstract

First and second gate lines parallel to each other are formed in the horizontal direction on the substrate, and the data lines are formed in the vertical direction with the first and second gate lines and the insulating layer interposed therebetween. A connection portion connecting the first and second gate lines is formed along the data line on the substrate under an arbitrary data line, and an auxiliary line is formed below the adjacent data line to prepare for disconnection of the data line. In this case, the auxiliary line is formed to be separated from the first and second gate lines between the first and second gate lines, and both ends thereof are deflected at a predetermined angle. A semiconductor layer is formed on the first gate line, and a source electrode and a drain electrode connected to the data line overlap each other with the semiconductor layer. A transparent pixel electrode connected to the drain electrode is formed on the passivation layer covering the data line and the source and drain electrodes, and a transparent connection pattern connecting the auxiliary line and the data line or the auxiliary line and the auxiliary line of the adjacent pixel is formed on the passivation layer. .

Description

Liquid crystal display

The present invention relates to a thin film transistor liquid crystal display device having a double gate line structure, and more particularly, to a structure in which the auxiliary line does not exist in a predetermined pixel unit.

In a liquid crystal display device having a structure in which a gate line is formed in double for one pixel and a double gate line is connected to the gate line connection part, a part of the double gate line overlaps the edge of the pixel electrode and the pixel electrode is sheared. The storage capacitor is formed by using a gate line portion overlapping the pixel electrode by connecting to the drain electrode of the pixel. Therefore, there is no need to make a separate storage capacitor line and there is an advantage that the disconnection of the gate line can be prevented. If necessary, an auxiliary repair line is provided with a gate metal under the data line and connected to the data line through the data line and the contact hole, thereby preventing disconnection of the data line.

However, there is a disadvantage that the aperture ratio is reduced because the gate line connection part is in the pixel. Further, since the auxiliary repair line is formed on the same layer of the same metal as the gate line connection part, there is a possibility that a short circuit occurs between the auxiliary repair line and the gate line connection part, that is, the gate electrode and the drain electrode.

An object of the present invention is to implement a wiring structure that prevents disconnection of gate lines and data lines.

Another object of the present invention is to prevent the reduction of the aperture ratio.

1 is a wiring diagram of a thin film transistor substrate according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3 is a cross-sectional view taken along the line III-III 'of FIG. 1,

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 1;

5 is a plan view schematically illustrating a gate wiring and a pixel area of a thin film transistor substrate according to an exemplary embodiment of the present invention.

In the liquid crystal display according to the present invention for solving this problem, the gate connection part is formed under the data line, so that the aperture ratio is not reduced.

In the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of pairs of gate lines of double lines are formed on the substrate in parallel with each other, and the gate connection part connects the double gate lines. The gate insulating film is covered thereon, and a plurality of data lines crossing the gate line are formed on the insulating film. At this time, the gate line connection part is formed in parallel with the data line under any data line of the plurality of data lines.

An auxiliary line may be formed under the remaining data line that does not overlap the gate connection part, and the auxiliary line is preferably separated from the double gate line and electrically connected to the data line.

Connection means for connecting the auxiliary lines on both sides of the gate line to the data line at the same time, the connection means may be formed of a transparent conductive film.

Preferably, the gate connection portion is formed at a smaller ratio than the auxiliary line. That is, the ratio of the data line overlapping the gate connection part and the data line overlapping the auxiliary line is preferably 1:10.

As such, since the gate connection part is disposed under the data line, disconnection of the gate and the data line can be prevented without reducing the aperture ratio.

Next, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art may easily implement the present invention.

1 is a wiring diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, FIG. 3 is a cross-sectional view taken along the line III-III 'of FIG. 1, and FIG. 4. Is a cross-sectional view taken along the line IV-IV 'of FIG.

1 to 4, a first gate line 101 and a second gate line 102 parallel to each other are formed in a horizontal direction on the transparent insulating substrate 10, and the first and second gates are formed in a horizontal direction. The connection part 103 which connects the lines 101 and 102 is formed in arbitrary parts. In addition, the auxiliary line 104 in preparation for disconnection of the data line is formed in the vertical direction. In this case, the auxiliary line 104 is formed to be separated from the first and second gate lines 101 and 102 between the first and second gate lines 101 and 102, and both ends thereof are deflected at a predetermined angle. have.

The gate insulating layer 200 covers the first and second gate lines 101 and 102, the gate line connecting unit 103, and the auxiliary line 104, and the semiconductor layer 300 is formed on the first gate line 101. Formed. On the semiconductor layer 300, an ohmic contact layer 301 is formed on both sides of the first gate line 101 to improve electrical contact characteristics, and a source electrode S and a drain electrode D are disposed thereon. Each is formed. In addition, the data line 400 is formed on the gate insulating layer 200 in the vertical direction on the gate line connecting unit 103 and the auxiliary line 104, and the data line 400 is connected to the source electrode S. FIG. .

The semiconductor layer 300, the data line 400, the source and drain electrodes S and D are covered with a protective insulating film 500, and data of a portion where the data line 400 and the first gate line 101 cross each other. Contact holes C3 and C4 exposing portions of the line 400 and the drain electrode D are respectively drilled through the protective insulating film 500. In addition, contact holes C1 and C2 exposing both ends of the auxiliary line 104 are formed in the protective insulating film 500 and the gate insulating film 200.

A transparent pixel electrode 600 is formed in the pixel area partitioned by the double gate lines 101 and 102 and the data line 400 on the passivation insulating layer 500. The drain electrode of the front end pixel is formed through the contact hole C4. It is connected with (D).

The intersection of the gate lines 101 and 102 and the data line 400 overlaps the first gate line 101 and the second gate line 102 of the front end pixel, and an end portion thereof is deflected at an angle. A transparent connection pattern 620 overlapping the end of the auxiliary line 104 is formed. An end portion of the transparent connection pattern 620 is connected to the auxiliary line 104 through the contact holes C1 and C2 and is also connected to the data line 400 through the contact hole C3 bored through the protective insulating film 500. Connected. That is, the auxiliary line 104 is electrically connected to the data line 400 through the transparent connection pattern 620.

On the other hand, when all of the adjacent pixel areas have the auxiliary line 104, the transparent connection pattern 620 simultaneously stores the auxiliary line 104 of the first gate line 101 and the second gate line 102 of the previous stage. To line 400.

As described above, in the embodiment of the present invention, since the gate line connecting portion 103 is formed below the data line 400, the aperture ratio does not decrease. In addition, since the gate line connecting portion 103 and the auxiliary line 104 are not adjacent to each other, a defect due to a short circuit between the gate and the drain does not occur.

In an embodiment of the present invention, the gate line connecting portion and the auxiliary line exist at a constant ratio, which will be further described with reference to FIG. 5.

FIG. 5 is a plan view schematically illustrating a gate line and a pixel area of a thin film transistor substrate according to an exemplary embodiment of the present invention. FIG. 5 illustrates only a double gate line, a gate line, and a pixel area, not a thin film transistor or a substrate line.

As shown in FIG. 5, a plurality of pixels P are arranged in a matrix form on a substrate, and two gate lines 101 and 102 are formed for each pixel row. The two gate lines 101 and 102 are connected to one at the left edge of the substrate to receive the same scan signal, and thus have a double gate line structure.

A gate line connecting part 103 is formed outside one of the plurality of pixels P arranged in a matrix form to connect the double gate lines 101 and 102 in the vertical direction. In order to make the load capacitance applied to the data lines of the entire substrate uniform, the gate line connecting portions 103 are sequentially connected to the pixels P. FIG.

For example, when the gate connection unit 103 is connected to the gate lines 101 and 102 corresponding to the first pixel in the pixel P connected to one data line (not shown), the remaining nine pixels in succession For the gate connection 103 is not formed.

The number of pixels to which the gate line connection unit 103 corresponds is smaller than the number of pixels to which the gate line connection unit 103 does not correspond. Usually, since the probability of disconnection of the gate line or the data line is less than 10%, the gate connection unit ( The ratio of the pixels to which the 103 is connected and the pixels not to be connected may be about 1:10.

On the other hand, in the pixel P to which the gate line connection unit 103 is not connected, an auxiliary line 104 is formed between the two gate lines 101 and 102 to prevent disconnection of the data line (not shown).

As described above, when the positions of the gate line connecting unit 103 and the auxiliary line 104 are sequentially changed, the load capacitance of the wiring can be uniformly formed in the substrate.

As described above, since the gate line connecting portion is positioned below the data line, the aperture ratio is not reduced. In addition, since the gate line connecting portion and the auxiliary line are selectively and sequentially formed for each pixel, it is possible to prevent a defect due to a short circuit between the connecting portion and the auxiliary line, and to bring the load capacity of the wiring uniformly to the entire substrate.

Claims (8)

Insulation board, A first gate line formed on the substrate, A second gate line formed in parallel with the first gate line, A gate line connection part connecting the first and second gate lines; A first insulating layer covering the first and second gate lines and the gate line connection part, A plurality of data lines formed on the first insulating layer and intersecting the first and second gate lines; And the gate line connection part is formed under the at least one data line of the plurality of data lines in parallel. In claim 1, At least one auxiliary line overlapping at least one of the remaining data lines except for the data line having the gate line connection part formed under the plurality of data lines, and separated by the first and second gate lines Liquid crystal display further comprising. In claim 2, And a connecting means positioned on both of the first and second gate lines to connect the auxiliary line and the data line. In claim 1, A liquid crystal further includes an auxiliary line formed to overlap a portion of a data line positioned in another pixel except a pixel in which the gate line connection portion is formed, among a plurality of pixels defined by the data line formed under the gate line connection portion. Display device. The method according to claim 1 or 2, And a second insulating layer covering the plurality of data lines, wherein the connecting means is formed of a transparent conductive film on the second insulating layer. In claim 5, The connecting means is connected to the auxiliary line and the data line through the second insulating layer, the first contact hole formed in the first insulating layer, and the second contact hole formed in the second insulating layer, respectively. . In claim 2, And the gate line connecting portion is formed at a smaller number than the auxiliary line. In claim 2, And a plurality of pixels in which the plurality of data lines and the first and second gate lines cross each other, wherein the gate connection part is formed such that positions of the corresponding pixels are sequentially changed.