KR20000015578A - Method of wire bonding for semiconductor package fabrication - Google Patents

Method of wire bonding for semiconductor package fabrication Download PDF

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Publication number
KR20000015578A
KR20000015578A KR1019980035604A KR19980035604A KR20000015578A KR 20000015578 A KR20000015578 A KR 20000015578A KR 1019980035604 A KR1019980035604 A KR 1019980035604A KR 19980035604 A KR19980035604 A KR 19980035604A KR 20000015578 A KR20000015578 A KR 20000015578A
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South Korea
Prior art keywords
wire bonding
materials
loaded
semiconductor package
tray
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KR1019980035604A
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Korean (ko)
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윤주훈
강대병
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김규현
아남반도체 주식회사
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Priority to KR1019980035604A priority Critical patent/KR20000015578A/en
Publication of KR20000015578A publication Critical patent/KR20000015578A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Abstract

PURPOSE: The method improves the productivity by shortening the material transportation time, by performing wire bonding to all units formed in the material in the state that a plurality of materials for wire bonding are loaded. CONSTITUTION: The method shortens the material transportation time by; loading a plurality of materials(6) for wire bonding such as a lead frame, a printed circuit board and a circuit tape to a wire bonding part(4); wire bonding to all units where the loaded materials are formed; and then unloading the above materials. A tray(8) where the above materials are placed is loaded to the wire bonding part. To load the tray, a guide rail(2) is formed, and the tray is loaded to the guide rail. The wire bonding to all units is possible because all units can be positioned within the operation area of the wire bonding part and the semiconductor chip is compact.

Description

반도체패키지 제조용 와이어본딩방법Wire Bonding Method for Semiconductor Package Manufacturing

본 발명은 반도체패키지 제조용 와이어본딩방법에 관한 것으로써, 더욱 상세하게는 와이어본딩을 위한 자재(리드프레임, 인쇄회로기판, 회로가 형성된 써킷테이프 등)를 복수개 로딩시킨 상태에서 모든 유니트에 와이어본딩을 함으로써, 생산성을 향상시킬 수 있도록 된 반도체패키지 제조용 와이어본딩방법에 관한 것이다.The present invention relates to a wire bonding method for manufacturing a semiconductor package, and more particularly, wire bonding to all units in a state in which a plurality of materials (lead frames, printed circuit boards, circuit tapes having circuits, etc.) for wire bonding are loaded. It is related with the wire bonding method for semiconductor package manufacture which can improve productivity.

일반적으로 반도체 패키지는 여러 단계의 공정(원자재검사, 소잉공정, 다이본딩공정, 와이어본딩공정, 몰딩공정, 마킹공정 등)을 거쳐 반도체 패키지의 제품으로 완성된다.In general, the semiconductor package is completed as a product of the semiconductor package through a multi-step process (material inspection, sawing process, die bonding process, wire bonding process, molding process, marking process, etc.).

상기에 있어서, 와이어본딩공정은 전자회로가 집적되어 있는 반도체칩에서 신호를 인출하기 위하여 자재(리드프레임, 인쇄회로기판, 회로가 형성되어 있는 써킷테이프 등)에 와이어로 연결하는 공정이다.In the above, the wire bonding step is a process of connecting wires to materials (lead frames, printed circuit boards, circuit tapes on which circuits are formed, etc.) in order to extract signals from semiconductor chips in which electronic circuits are integrated.

이와 같이 와이어본딩을 하기 위한 일반적인 와이어본딩장비는, 도 1에 도시된 바와 같이 자재를 순차적으로 공급하는 로딩부(1)와, 상기한 로딩부(1)에서 공급된 자재를 이송시키는 안내레일(2)과, 상기한 안내레일(2)에 의해 이송되는 자재를 정지시키는 스톱퍼(3)와, 상기한 스톱퍼(3)에 의해 정지된 자재의 유니트에 와이어로 본딩하는 와이어본딩부(4)와, 상기한 와이어본딩부(4)에서 와이어본딩된 자재를 배출하는 언로딩부(5)로 크게 구성된다.As described above, a general wire bonding apparatus for wire bonding includes a loading unit 1 for sequentially supplying materials as shown in FIG. 1, and a guide rail for transporting materials supplied from the loading unit 1 ( 2), a stopper (3) for stopping the material conveyed by the guide rail (2), a wire bonding portion (4) for bonding wires to the unit of the material stopped by the stopper (3); In addition, the wire bonding unit 4 is largely composed of an unloading unit 5 for discharging the wire-bonded material.

상기한 와이어본딩장비를 이용하여 와이어를 본딩하기 위한 종래의 방법은, 도 2에 도시된 바와 같이 하나의 자재(6)만을 로딩하여 한 유니트(7) 단위로 이송시키면서 와이어본딩을 하였다.In the conventional method for bonding wires using the wire bonding equipment, wire bonding is performed while only one material 6 is loaded and transferred to one unit 7 unit as shown in FIG. 2.

즉, 와이어본딩을 위한 자재(6)에는 다수개의 유니트(7)가 형성되어 있고, 상기 다수개의 유니트(7)에 와이어본딩을 하기 위한 와이어본딩부(4)의 영역은 한정되어 있음으로써, 상기 와이어본딩부(4)에 위치되는 유니트(7)에만 와이어본딩을 하였다.That is, a plurality of units 7 are formed in the material 6 for wire bonding, and the area of the wire bonding portion 4 for wire bonding to the plurality of units 7 is limited. Wire bonding was performed only to the unit 7 located in the wire bonding portion 4.

이와 같이 자재(6)를 한 유니트(7) 단위로 이송시키면서 하나의 유니트(7)에만 와이어본딩을 할 수밖에 없었던 것은, 종래의 반도체패키지는 그 크기가 비교적 크기 때문에, 와이어본딩부(4)의 와이어본딩영역을 무한대로 크게 만들 수 없었기 때문이다.As described above, the wire bonding unit 4 was inevitably wire-bonded to only one unit 7 while the material 6 was transferred to one unit 7 unit. This is because the wire bonding area could not be made infinitely large.

따라서, 자재(6)를 한 유니트 단위로 이송시키면서 하나의 유니트(7)에만 와이어를 본딩함으로서, 상기한 자재(6)를 이송시키기 위한 시간이 필요하게 되어 생산성이 떨어지는 단점이 있었던 것이다.Therefore, by bonding the wires to only one unit 7 while transferring the material 6 in one unit unit, the time required for transferring the material 6 is required, resulting in a decrease in productivity.

본 발명의 목적은 이와같은 문제점을 해소하기 위하여 발명된 것으로서, 와이어본딩을 위한 자재를 복수개 로딩한 상태에서 자재에 형성되어 있는 모든 유니트에 전부 와이어본딩을 함으로써, 자재의 이송에 의한 시간을 단축하여 생산성을 향상시킬 수 있도록 된 반도체패키지 제조용 와이어본딩방법을 제공함에 있다.An object of the present invention is to invent such a problem, by wire-bonding all the units formed in the material in a state in which a plurality of materials for wire bonding is loaded, thereby reducing the time by material transfer The present invention provides a wire bonding method for manufacturing a semiconductor package that can improve productivity.

도 1은 일반적인 와이어본딩장비의 구성을 나타낸 개략도1 is a schematic view showing the configuration of a general wire bonding equipment

도 2는 일반적인 반도체패키지 제조용 와이어본딩방법을 나타낸 도면2 is a view showing a wire bonding method for manufacturing a general semiconductor package

도 3은 본 발명의 제1 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 나타낸 도면3 is a view showing a wire bonding method for manufacturing a semiconductor package according to a first embodiment of the present invention;

도 4a와 도 4b는 본 발명의 제2 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 타나낸 도면4A and 4B illustrate a wire bonding method for manufacturing a semiconductor package according to a second embodiment of the present invention.

도 5는 본 발명의 제3 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 타나낸 도면5 is a view showing a wire bonding method for manufacturing a semiconductor package according to a third embodiment of the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

1 - 로딩부 2 - 안내레일1-Loading part 2-Guide rail

3 - 스톱퍼 4 - 와이어본딩부3-Stopper 4-Wire Bonding Section

5 - 언로딩부 6 - 자재5-Unloading section 6-Materials

7 - 유니트 8 - 트레이7-Unit 8-Tray

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명의 제1 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 나타낸 도면으로써, 와이어본딩을 위한 자재(리드프레임, 인쇄회로기판, 회로가 형성된 써킷테이프)를 와이어본딩부(4)에 복수개 로딩하고, 로딩된 복수개의 자재(6)에 형성되어 있는 모든 유니트(7)에 와이어본딩을 한 다음, 상기한 자재(6)를 언로딩시키는 것이다.3 is a view illustrating a wire bonding method for manufacturing a semiconductor package according to a first embodiment of the present invention, wherein a material (lead frame, printed circuit board, circuit tape on which a circuit is formed) for wire bonding is attached to the wire bonding unit 4. A plurality of loads are loaded, wire-bonded to all the units 7 formed in the plurality of loaded materials 6, and then the material 6 is unloaded.

여기서, 상기한 복수개의 자재(6)를 와이어본딩부(4)에 로딩하기 위해서는 복수개의 안내레일(2)이 형성되어 있고, 상기 복수개의 안내레일(2)에 각각 자재(6)를 로딩하는 것에 의해 복수개의 자재(6)를 모두 로딩할 수 있다.In this case, in order to load the plurality of materials 6 into the wire bonding unit 4, a plurality of guide rails 2 are formed, and each of the materials 6 is loaded into the plurality of guide rails 2. In this way, all of the plurality of materials 6 can be loaded.

상기와 같이 복수개의 자재(6)를 로딩하여 모든 유니트(7)에 와이어본딩을 할 수 있는 것은, 최근에 개발되는 반도체패키지(마이크로비지에이반도체패키지, 칩사이즈반도체패키지)는 매우 소형화되어 있음으로써, 종래의 와이어본딩장비에서 와이어본딩부의 작동영역내에 모든 유니트(7)가 위치될 수 있기 때문에 가능하다.As described above, a plurality of materials 6 can be loaded and wire-bonded to all the units 7. The semiconductor packages (micro-BI A semiconductor packages and chip size semiconductor packages) that have been recently developed are very small. In the conventional wire bonding equipment, it is possible because all units 7 can be located in the operating area of the wire bonding portion.

따라서, 이와 같은 방법으로 와이어본딩을 하게되면, 자재 이송에 따른 시간을 단축시킬 수 있어 반도체패키지의 생산성을 향상시킬 수 있는 장점이 있다.Therefore, when wire bonding in this manner, there is an advantage that can shorten the time according to the material transfer to improve the productivity of the semiconductor package.

도 4a는 본 발명의 제2 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 나타낸 도면으로써, 와이어본딩을 위한 자재(리드프레임, 인쇄회로기판, 회로가 형성된 써킷테이프)가 복수개 안착되어 있는 트레이(8)를 와이어본딩부(4)에 로딩하고, 로딩된 복수개의 자재(6)에 형성되어 있는 모든 유니트(7)에 와이어본딩을 한 다음, 상기한 트레이(8)를 언로딩시켜 복수개의 자재(6)를 배출하는 것이다.4A is a view illustrating a wire bonding method for manufacturing a semiconductor package according to a second embodiment of the present invention, and includes a tray 8 in which a plurality of materials (lead frame, printed circuit board, circuit tape on which circuits are formed) are mounted. ) Is loaded into the wire bonding unit 4, wire bonding is performed on all the units 7 formed in the plurality of loaded materials 6, and then the tray 8 is unloaded to remove the plurality of materials ( 6) to discharge.

여기서, 상기한 트레이(8)를 로딩하기 위해서는 하나의 안내레일(2)이 형성되어 있고, 이 안내레일(2)에 복수개의 자재(6)가 안착되어 있는 트레이(8)를 로딩하는 것에 의해 복수개의 자재(6)를 동시에 로딩할 수 있다.Here, in order to load the tray 8 described above, one guide rail 2 is formed, and the guide rail 2 is loaded with a tray 8 on which a plurality of materials 6 are seated. A plurality of materials 6 can be loaded at the same time.

상기에 있어서, 도 4a에서는 와이어 본딩을 위한 자재가 3개 만이 트레이(8)에 안착된 상태를 도시하였으나, 반도체칩(C)의 크기가 매우 소형인 경우에는 도 4b에 도시된 바와 같이 상기한 트레이(8)에 많은 반도체칩(C)을 안착시킨 상태로 와이어 본딩을 행할 수 있다.4A illustrates a state in which only three materials for wire bonding are seated on the tray 8, but in the case where the size of the semiconductor chip C is very small, as shown in FIG. 4B. Wire bonding can be performed in a state where many semiconductor chips C are seated in the tray 8.

상기와 같이 복수개의 자재(6)를 하나의 트레이(8)에 안착시킨 상태로 상기한 트레이(8)를 로딩하여 와이어본딩을 하게되면, 자재의 이송에 따른 시간을 단축시킬 수 있어 반도체패키지의 생산성을 향상시킬 수 있는 장점이 있다. 또한, 본 발명의 제2 실시예는 복수개의 자재(6)가 하나의 트레이(8)에 안착된 상태로 상기한 트레이(8) 만을 이송시키면 되므로, 복수개의 안내레일(2)이 필요 없어 장비의 구성을 간단하게 할 수 있는 장점도 있다.When wire bonding is performed by loading the tray 8 in a state where the plurality of materials 6 are seated on one tray 8 as described above, the time required for the transfer of materials can be shortened. There is an advantage to improve productivity. Further, in the second embodiment of the present invention, since only the tray 8 is transported with the plurality of materials 6 seated on one tray 8, the plurality of guide rails 2 are not necessary. There is also an advantage that can simplify the configuration.

도 5는 본 발명의 제3 실시예에 따른 반도체패키지 제조용 와이어본딩방법을 나타낸 도면으로써, 웨이퍼(W) 상에서 직접 와이어본딩을 하기 위하여 상기한 웨이퍼(W)를 로딩하고, 로딩된 웨이퍼(W) 상의 모든 반도체칩(C)에 와이어본딩을 한 다음, 상기한 웨이퍼(W)를 언로딩시키는 방법으로 와이어본딩을 하도록 된 것이다.FIG. 5 is a diagram illustrating a wire bonding method for manufacturing a semiconductor package according to a third embodiment of the present invention. The wafer W is loaded for direct wire bonding on the wafer W, and the loaded wafer W is loaded. After wire bonding to all the semiconductor chips (C) on the wire, the wire bonding is performed by unloading the wafer (W).

이와 같은 본 발명의 제3 실시예는, 다수의 반도체칩이 형성되어 있는 웨이퍼상에 회로패턴이 형성되어 있는 써킷테이프를 접착시킨 채, 웨이퍼상에서 와이어본딩, 인캡슐레이션 및 솔더볼 융착을 마친 후, 마지막 단계에서 상기한 웨이퍼를 각각의 반도체칩으로 절단하여 독립된 반도체 패키지를 제조하도록 된 반도체 패키지에서 이용 가능하다.In the third embodiment of the present invention, after the circuit tape on which the circuit pattern is formed on the wafer on which the semiconductor chips are formed, the wire bonding, encapsulation, and solder ball fusion are completed on the wafer. In the last step, the wafer can be cut into individual semiconductor chips and used in a semiconductor package adapted to produce an independent semiconductor package.

이상의 설명에서 알 수 있듯이 본 발명의 반도체패키지 제조용 와이어 본딩방법에 의하면, 와이어본딩을 위한 복수개의 자재를 한번 로딩한 상태에서 자재에 형성되어 있는 모든 유니트에 전부 와이어본딩을 함으로써, 자재의 이송에 의한 시간을 단축하여 생산성을 향상시킬 수 있는 효과가 있다.As can be seen from the above description, according to the wire bonding method for manufacturing a semiconductor package of the present invention, all the units formed in the material are wire-bonded in a state in which a plurality of materials for wire bonding are loaded once, thereby resulting in material transfer. There is an effect that can improve productivity by reducing the time.

Claims (3)

와이어본딩을 위한 자재를 와이어본딩부에 복수개 로딩하고, 로딩된 복수개의 자재에 형성되어 있는 모든 유니트에 와이어본딩을 한 다음, 상기한 자재를 언로딩시키는 방법으로 와이어본딩을 하도록 된 것을 특징으로 하는 반도체패키지 제조용 와이어본딩방법.Loading a plurality of materials for wire bonding to the wire bonding, wire bonding to all the units formed in the plurality of loaded materials, and then wire bonding by unloading the material described above Wire bonding method for manufacturing semiconductor package. 와이어본딩을 위한 자재가 복수개 안착되어 있는 트레이를 와이어본딩부에 로딩하고, 로딩된 복수개의 자재에 형성되어 있는 모든 유니트에 와이어본딩을 한 다음, 상기한 트레이를 언로딩시켜 복수개의 자재를 배출하는 방법에 의해 와이어본딩을 하도록 된 것을 특징으로 하는 반도체패키지 제조용 와이어본딩방법.Loading a tray having a plurality of materials for wire bonding to the wire bonding unit, wire bonding to all units formed in the plurality of loaded materials, and then unloading the trays to discharge the plurality of materials. Wire bonding method for manufacturing a semiconductor package, characterized in that the wire bonding by the method. 웨이퍼 상에서 직접 와이어본딩을 하기 위하여 상기한 웨이퍼를 로딩하고, 로딩된 웨이퍼상의 모든 반도체칩에 와이어본딩을 한 다음, 상기한 웨이퍼를 언로딩시키는 방법으로 와이어본딩을 하도록 된 것을 특징으로 하는 반도체패키지 제조용 와이어본딩방법.Loading a wafer for direct wire bonding on a wafer, wire bonding all the semiconductor chips on the loaded wafer, and then wire bonding by unloading the wafer. Wire bonding method.
KR1019980035604A 1998-08-31 1998-08-31 Method of wire bonding for semiconductor package fabrication KR20000015578A (en)

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US10641501B2 (en) 2015-11-30 2020-05-05 Nam Hoon Kim Smoke exhaust hood apparatus having heater for cooking food

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JPS56164538A (en) * 1980-05-21 1981-12-17 Sony Corp Assembling device for semicondutor element
JPH06163627A (en) * 1992-11-18 1994-06-10 Sony Corp Wire bonding system
KR970030542A (en) * 1995-11-30 1997-06-26 김광호 Wire bonding device having a plurality of chip seats and bonding windows
KR19980013455U (en) * 1996-08-30 1998-06-05 김주용 Lead Frame Automatic Feeding Conveyor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164538A (en) * 1980-05-21 1981-12-17 Sony Corp Assembling device for semicondutor element
JPH06163627A (en) * 1992-11-18 1994-06-10 Sony Corp Wire bonding system
KR970030542A (en) * 1995-11-30 1997-06-26 김광호 Wire bonding device having a plurality of chip seats and bonding windows
KR19980013455U (en) * 1996-08-30 1998-06-05 김주용 Lead Frame Automatic Feeding Conveyor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10641501B2 (en) 2015-11-30 2020-05-05 Nam Hoon Kim Smoke exhaust hood apparatus having heater for cooking food

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