KR20000003178A - Etch stopper forming method of thin film transistor - Google Patents
Etch stopper forming method of thin film transistor Download PDFInfo
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- KR20000003178A KR20000003178A KR1019980024344A KR19980024344A KR20000003178A KR 20000003178 A KR20000003178 A KR 20000003178A KR 1019980024344 A KR1019980024344 A KR 1019980024344A KR 19980024344 A KR19980024344 A KR 19980024344A KR 20000003178 A KR20000003178 A KR 20000003178A
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 53
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000010408 film Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000011521 glass Substances 0.000 claims abstract description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 9
- 230000008569 process Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
Description
본 발명은 박막 트랜지스터 액정표시소자에 관한 것으로, 보다 상세하게는, 식각 프로파일을 개선시킬 수 있는 박막 트랜지스터의 에치 스톱퍼 형성방법에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a method of forming an etch stopper for a thin film transistor capable of improving an etching profile.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 각 화소의 구동을 독립적으로 제어하기 위한 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD equipped with a thin film transistor (TFT) as a switching element for independently controlling the driving of each pixel is comparable to a CRT because of its advantages of high-speed response characteristics and its suitability for high pixel numbers. It is greatly contributing to realizing high screen quality, large size, and color.
도 1은 종래 TFT를 도시한 도면으로서, 도시된 바와 같이, 유리 기판(1) 상에 게이트 전극(2)이 형성되어 있으며, 상기 게이트 전극(2)은 유리 기판(1) 전면에 형성된 게이트 절연막(3)에 의해 피복되어 있다.1 is a view showing a conventional TFT, as shown, a gate electrode 2 is formed on a glass substrate 1, the gate electrode 2 is a gate insulating film formed on the entire glass substrate 1 It is covered by (3).
또한, 게이트 절연막(3) 상에는 패턴의 형태로 반도체층(4)이 형성되어 있으며, 이러한 반도체층(4)의 중심부 상에는 소오스/드레인 전극의 형성시에 상기 반도체층(4)이 손상되는 것을 방지하기 위한 에치 스톱퍼(5)가 형성되어 있고, 이러한 에치 스톱퍼(5)는 통상 실리콘 질화막으로 형성한다.In addition, the semiconductor layer 4 is formed on the gate insulating film 3 in the form of a pattern, and the semiconductor layer 4 is prevented from being damaged when the source / drain electrodes are formed on the center of the semiconductor layer 4. An etch stopper 5 is provided, and this etch stopper 5 is usually formed of a silicon nitride film.
그리고, 에치 스톱퍼(5)의 일측 및 타측 상부면과 반도체층(4) 상에는 오믹층(6)이 형성되어 있으며, 이러한 오믹층(6) 상에 소오스/드레인 전극(7a, 7b)이 형성되어 있다.The ohmic layer 6 is formed on one side and the other upper surface of the etch stopper 5 and the semiconductor layer 4, and the source / drain electrodes 7a and 7b are formed on the ohmic layer 6. have.
그러나, 상기와 같은 종래 TFT는 에치 스톱퍼의 형성하기 위한 실리콘 질화막의 식각시에 식각 프로파일(profile)이 불량하기 때문에 후속 공정에서 상기 에치 스톱퍼 상에 형성되는 막들의 스텝 커버리지가 불량해지며, 심한 경우에는 단선과 같은 결함이 발생되는 문제점이 있었다.However, such a conventional TFT has a poor etching profile during etching of the silicon nitride film for forming the etch stopper, resulting in poor step coverage of the films formed on the etch stopper in a subsequent process. There was a problem that a defect such as disconnection occurred.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 실리콘 질화막의 식각 프로파일을 개선할 수 있는 TFT의 에치 스톱퍼 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming an etch stopper of a TFT capable of improving an etching profile of a silicon nitride film.
도 1은 종래 박막 트랜지스터를 설명하기 위한 단면도.1 is a cross-sectional view illustrating a conventional thin film transistor.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 박막 트랜지스터의 에치 스톱퍼 형성방법을 설명하기 위한 일련의 공정 단면도.2A to 2C are cross-sectional views of a series of steps for explaining a method of forming an etch stopper for a thin film transistor according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 게이트 절연막 14 : 비정실리콘막13 gate insulating film 14 amorphous silicon film
15 : 실리콘 질화막 15a : 제1실리콘 질화막층15 silicon nitride film 15a first silicon nitride film layer
15b : 제2실리콘 질화막층 15c : 제3실리콘 질화막층15b: second silicon nitride film layer 15c: third silicon nitride film layer
16 : 에치 스톱퍼16: etch stopper
상기와 같은 목적을 달성하기 위한 본 발명의 TFT의 에치 스톱퍼 형성방법은, 게이트 전극이 형성되며, 상기 게이트 전극이 덮혀지도록 전면 상에 게이트 절연막이 형성된 유리기판을 제공하는 단계; 상기 게이트 절연막 상에 비정질실리콘층을 형성하는 단계; 상기 비정질실리콘층 상에 실리콘 질화막을 형성하는 단계; 및 상기 실리콘 질화막을 식각하여 에치 스톱퍼를 형성하는 단계를 포함하며, 상기 실리콘 질화막은 적어도 3층 이상이 적층된 다층 구조로 형성하되, 하층에 형성되는 실리콘 질화막층이 상층에 형성되는 실리콘 질화막층 보다 상대적으로 느린 식각 속도를 갖도록 형성하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of forming an etch stopper of a TFT, the method including: providing a glass substrate having a gate electrode formed thereon and having a gate insulating film formed on its entire surface to cover the gate electrode; Forming an amorphous silicon layer on the gate insulating film; Forming a silicon nitride film on the amorphous silicon layer; And etching the silicon nitride film to form an etch stopper, wherein the silicon nitride film is formed in a multi-layered structure having at least three or more layers stacked therein, wherein the silicon nitride film layer formed under the silicon nitride film is formed on the upper layer. It is characterized in that it is formed to have a relatively slow etching rate.
본 발명에 따르면, 에치 스톱퍼의 재질인 실리콘 질화막을 다층 구조로 구성하되, 하층에 위치된 실리콘 질화막층의 식각 속도가 상층에 위치된 실리콘 질화막층의 식각 속도 보다 느리게 함으로써, 다층 구조로된 실리콘 질화막의 식각시에 식각 프로파일을 개선시킬 수 있으며, 이에 따라, 후속 공정에서 단선이 발생되는 것을 방지할 수 있다.According to the present invention, the silicon nitride film, which is a material of the etch stopper, is formed in a multilayer structure, and the etching speed of the silicon nitride film layer located in the lower layer is lower than the etching rate of the silicon nitride film layer located in the upper layer, whereby the silicon nitride film has a multilayer structure. It is possible to improve the etching profile at the time of etching, thereby preventing the occurrence of disconnection in the subsequent process.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 TFT의 에치 스톱퍼 형성방법을 설명하기 위한 공정 단면도로서, 우선, 도 2a에 도시된 바와 같이, 유리기판(11) 상에 게이트 전극(12)을 형성하고, 상기 게이트 전극(12)이 덮혀지도록 유리기판(11) 전면에 게이트 절연막(13)을 형성한 후, 게이트 절연막(13) 상에 반도체층을 형성하기 위한 비정질실리콘층(14)을 형성한다.2A to 2C are cross-sectional views illustrating a method of forming an etch stopper of a TFT according to an exemplary embodiment of the present invention. First, as shown in FIG. 2A, a gate electrode 12 is formed on a glass substrate 11. After the gate insulating film 13 is formed on the entire surface of the glass substrate 11 so that the gate electrode 12 is covered, the amorphous silicon layer 14 for forming the semiconductor layer is formed on the gate insulating film 13. do.
그런 다음, 도 2b에 도시된 바와 같이, 비정질실리콘층(14) 상에 에치 스톱퍼를 형성하기 위한 실리콘 질화막(15)을 형성한다. 여기서, 실리콘 질화막(15)은 적어도 3층 이상이 적층된 다층 구조로 형성하며, 이때, 각 실리콘 질화막층들은 서로 다른 식각 속도를 갖도록 형성한다.Then, as shown in FIG. 2B, a silicon nitride film 15 for forming an etch stopper is formed on the amorphous silicon layer 14. Here, the silicon nitride film 15 is formed in a multi-layered structure in which at least three layers are stacked. At this time, each silicon nitride film layer is formed to have a different etching rate.
예를 들어, 도시된 바와 같이 3층 구조로 형성하는 경우에는 비정질실리콘층(14)과 콘택되는 제1실리콘 질화막층(15a)은 그 상부에 형성되는 제2실리콘 질화막층(15b) 보다 상대적으로 느린 식각 속도를 갖도록 형성하며, 마찬가지로, 제2실리콘 질화막층(15b) 상에 형성되는 제3실리콘 질화막층(15c)은 상기 제2실리콘 질화막층(15b) 보다 상대적으로 느린 식각 속도를 갖도록 형성한다.For example, in the case of forming a three-layer structure as shown, the first silicon nitride film layer 15a in contact with the amorphous silicon layer 14 is relatively larger than the second silicon nitride film layer 15b formed thereon. Similarly, the third silicon nitride layer 15c formed on the second silicon nitride layer 15b is formed to have a slower etching rate than the second silicon nitride layer 15b. .
한편, 상기와 같이 실리콘 질화막층들(15a, 15b, 15c)의 식각 속도를 서로 다르게 하기 위해서는 상기 실리콘 질화막층들(15a, 15b, 15c)의 증착 공정시에 증착 조건, 예를 들어, 증착 시간, RF 파워, 챔버내의 압력, RF 파워가 공급되는 전극과 유리기판이 안착되는 써셉터(susceptor)간의 간격, 및 SiH4, N2, NH3가스의 유량 등을 조절하면 된다.Meanwhile, in order to change the etching rates of the silicon nitride layer layers 15a, 15b, and 15c as described above, deposition conditions, for example, deposition time, may be used during the deposition process of the silicon nitride layer layers 15a, 15b, and 15c. , The RF power, the pressure in the chamber, the interval between the electrode supplied with the RF power and the susceptor on which the glass substrate is seated, and the flow rate of SiH 4 , N 2 , NH 3 gas, and the like.
본 발명의 실시예에서는 표 1에 나타낸 바와 같이, RF 파워, 압력 및 가스들의 유량은 고정시킨 상태에서 증착 시간 및 RF 파워가 공급되는 전극과 유리기판이 안착되는 써셉터(susceptor)간의 간격을 조절하여 제1, 제2 및 제3실리콘 질화막층들(15a, 15b, 15c)의 식각 속도가 상이하게 되도록 만든다.In the embodiment of the present invention, as shown in Table 1, the RF power, the pressure and the flow rate of the gas is fixed while adjusting the deposition time and the interval between the electrode to which the RF power is supplied and the susceptor (sceptor) to which the glass substrate is seated. As a result, the etching rates of the first, second, and third silicon nitride layers 15a, 15b, and 15c are different.
계속해서, 도 2c에 도시된 바와 같이, 다층 구조로된 실리콘 질화막을 식각하여 비정질실리콘층(14) 상에 에치 스톱퍼(16)를 형성한다. 이때, 실리콘 질화막은 다층 구조로 이루어져 있고, 하층에 위치된 실리콘 질화막층이 상층에 위치된 실리콘 질화막층의 식각 속도 보다 느리기 때문에 이러한 다층 구조로된 실리콘 질화막을 동시에 식각하게 되면, 도시된 바와 같이, 에치 스톱퍼(16)의 측면 식각 프로파일을 사선의 형태로 됨과 아울러 그 면은 평탄하게 된다.Subsequently, as shown in FIG. 2C, the silicon nitride film having a multi-layer structure is etched to form an etch stopper 16 on the amorphous silicon layer 14. At this time, since the silicon nitride film has a multilayer structure and the silicon nitride film layer located at the lower layer is slower than the etching rate of the silicon nitride film layer located at the upper layer, when the silicon nitride film having the multilayer structure is simultaneously etched, as shown, The side etch profile of the etch stopper 16 is oblique and the surface is flat.
따라서, 후속 공정에서 이러한 에치 스톱퍼(16) 층에 형성되는 막들의 스텝 커버리지를 개선할 수 있게 되며, 이에 따라, 후속 공정에서 소오스/드레인 전극의 단선을 방지할 수 있게 된다.Thus, it is possible to improve the step coverage of the films formed in this etch stopper 16 layer in a subsequent process, thereby preventing the disconnection of the source / drain electrodes in the subsequent process.
이상에서와 같이, 본 발명은 에치 스톱퍼의 재질인 실리콘 질화막을 적어도 3층 이상이 적층된 다층 구조로 형성함과 아울러, 하층에 배치되는 실리콘 질화막층이 상층에 배치되는 실리콘 질화막층 보다는 상태적으로 느린 식각 속도를 갖도록 형성시킴으로서, 식각 공정시에 다층 구조로된 실리콘 질화막의 측면 식각 프로파일을 평탄하게 만들 수 있으며, 이에 따라, 단선과 같은 결함 발생을 방지할 수 있기 때문에 결과적으로는 TFT LCD의 제조 수율을 향상시킬 수 있게 된다.As described above, the present invention forms a silicon nitride film, which is a material of an etch stopper, in a multi-layer structure in which at least three or more layers are stacked, and the silicon nitride film layer disposed below the silicon nitride film layer disposed on the upper layer is in a more state-like state. By forming to have a slow etching rate, it is possible to make the side etching profile of the silicon nitride film having a multi-layer structure during the etching process flat, thereby preventing the occurrence of defects such as disconnection, resulting in the manufacture of TFT LCDs. The yield can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (5)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100359022B1 (en) * | 2000-12-20 | 2002-10-31 | 엘지.필립스 엘시디 주식회사 | Method for Fabricating Poly Silicon Of Thin Film Transistor |
| US7541288B2 (en) | 2007-03-08 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques |
| US8710503B2 (en) | 2009-12-16 | 2014-04-29 | Samsung Display Co., Ltd. | Organic light-emitting display and method of manufacturing the same |
| US10014172B2 (en) | 2014-03-06 | 2018-07-03 | Samsung Display Co., Ltd. | Thin film transistor, thin film transistor substrate, display apparatus and method of manufacturing thin film transistor |
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1998
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100359022B1 (en) * | 2000-12-20 | 2002-10-31 | 엘지.필립스 엘시디 주식회사 | Method for Fabricating Poly Silicon Of Thin Film Transistor |
| US7541288B2 (en) | 2007-03-08 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques |
| US8710503B2 (en) | 2009-12-16 | 2014-04-29 | Samsung Display Co., Ltd. | Organic light-emitting display and method of manufacturing the same |
| US10014172B2 (en) | 2014-03-06 | 2018-07-03 | Samsung Display Co., Ltd. | Thin film transistor, thin film transistor substrate, display apparatus and method of manufacturing thin film transistor |
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