KR20000015171A - Method of manufacturing a gate insulation layer of a thin film transistor liquid crystal display - Google Patents
Method of manufacturing a gate insulation layer of a thin film transistor liquid crystal display Download PDFInfo
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- KR20000015171A KR20000015171A KR1019980034937A KR19980034937A KR20000015171A KR 20000015171 A KR20000015171 A KR 20000015171A KR 1019980034937 A KR1019980034937 A KR 1019980034937A KR 19980034937 A KR19980034937 A KR 19980034937A KR 20000015171 A KR20000015171 A KR 20000015171A
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- insulating film
- liquid crystal
- crystal display
- gate
- thin film
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 11
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 238000009413 insulation Methods 0.000 title abstract 4
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000010408 film Substances 0.000 claims description 35
- 238000004140 cleaning Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 9
- 239000011521 glass Substances 0.000 abstract description 7
- 239000002245 particle Substances 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
Abstract
Description
본 발명은 박막 트랜지스터 액정표시소자의 제조방법에 관한 것으로, 특히, 게이트 라인과 데이터 라인간의 쇼트를 방지하기 위한 게이트 절연막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to a method of forming a gate insulating film for preventing a short between a gate line and a data line.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다. 특히, 매트릭스 형태로 배열된 각 화소에 스위칭 소자로서 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 높은 화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 표시 화면의 고화질화 및 대형화, 컬러화 등을 실현하는데 크게 기여하고 있다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, a TFT LCD having a thin film transistor (TFT) as a switching element in each pixel arranged in a matrix form is comparable to a CRT because of the advantages of having high-speed response characteristics and suitable for high pixel count. It is greatly contributing to realizing high screen quality, large size, and color.
도 1은 종래 기술에 따른 TFT LCD의 하부기판을 도시한 단면도로서, 이를 설명하면 다음과 같다. 도시된 바와 같이, 유리기판(1) 상에 게이트 전극(2)이 형성되며, 상기 게이트 전극(2)이 덮혀지도록 유리기판(1) 전면에는 게이트 절연막(3)이 도포된다.1 is a cross-sectional view illustrating a lower substrate of a TFT LCD according to the prior art, which will be described below. As shown, a gate electrode 2 is formed on the glass substrate 1, and a gate insulating film 3 is coated on the entire surface of the glass substrate 1 so that the gate electrode 2 is covered.
그리고, 게이트 절연막(3) 상에는 공지된 방법에 의해 패턴의 형태로 반도체층(4)이 형성되며, 상기 반도체층(4)의 중심부 상에는 에치 스톱퍼(5)가 형성된다.The semiconductor layer 4 is formed on the gate insulating film 3 in the form of a pattern by a known method, and the etch stopper 5 is formed on the central portion of the semiconductor layer 4.
또한, 에치 스톱퍼(5)의 일측 및 타측 상부와 이에 인접된 반도체층(4) 상에는 오믹층(6)이 형성되며, 상기 오믹층(6) 상에는 소오스/드레인 전극(7a, 7b)이 형성되어 TFT(10)가 완성된다.In addition, an ohmic layer 6 is formed on one side and the other side of the etch stopper 5 and an adjacent semiconductor layer 4, and source / drain electrodes 7a and 7b are formed on the ohmic layer 6. TFT 10 is completed.
한편, 화소영역에 해당하는 게이트 절연막(3) 부분 상에는 ITO 금속으로된 화소전극(8)이 형성되며, 이때, 상기 화소전극(8)은 TFT(10)의 소오스 전극(7a)과 콘택된다.On the other hand, a pixel electrode 8 made of ITO metal is formed on a portion of the gate insulating film 3 corresponding to the pixel region, wherein the pixel electrode 8 is in contact with the source electrode 7a of the TFT 10.
그러나, 상기와 같은 종래 TFT LCD의 제조 공정에서는 통상 게이트 절연막을 단일층으로 형성하고 있는데, 이때, 게이트 전극 및 유리기판의 표면에 존재하는 파티클(Particle)에 의해, 도 2에 도시된 바와 같이, 게이트 절연막(3) 내에 핀홀(Pinhole : P)이 발생하게 되고, 이러한 핀홀(P)은 후속의 열공정에 의해 더욱 성장되어, 결국, 게이트 전극과 소오스/드레인 전극간의 쇼트, 즉, 게이트 라인과 데이터 라인간의 쇼트를 유발시키게 되는 문제점이 있었다.However, in the manufacturing process of the conventional TFT LCD as described above, a gate insulating film is usually formed as a single layer. In this case, as shown in FIG. 2 by particles present on the surface of the gate electrode and the glass substrate, A pinhole (P) is generated in the gate insulating film 3, and the pinhole P is further grown by a subsequent thermal process, resulting in a short between the gate electrode and the source / drain electrode, that is, the gate line and the like. There was a problem that caused a short between data lines.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 게이트 절연막을 2층 이상의 다층으로 구성함으로써, 핀홀에 의한 게이트 라인과 데이터 라인간의 쇼트를 방지할 수 있는 TFT LCD의 게이트 절연막 형성방법을 제공하는데, 그 목적이 있다.Accordingly, the present invention devised to solve the above problems is to provide a gate insulating film forming method of a TFT LCD which can prevent the short between the gate line and the data line by the pinhole by configuring the gate insulating film in two or more layers. To provide, the purpose is.
도 1은 종래 박막 트랜지스터 액정표시소자의 하부기판을 도시한 단면도.1 is a cross-sectional view showing a lower substrate of a conventional thin film transistor liquid crystal display device.
도 2는 종래 문제점을 설명하기 위한 도면.2 is a view for explaining a conventional problem.
도 3은 본 발명의 실시예에 따른 박막 트랜지스터 액정표시소자의 게이트 절연막 형성방법을 설명하기 위한 도면.3 is a view for explaining a gate insulating film forming method of a thin film transistor liquid crystal display device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 제1절연막 14 : 제2절연막13: first insulating film 14: second insulating film
P1 : 제1핀홀 P2 : 제2핀홀P1: first pin hole P2: second pin hole
상기와 같은 목적을 달성하기 위한 본 발명의 TFT LCD의 게이트 절연막 형성방법은, 게이트 라인과 데이터 라인간의 쇼트를 방지하기 위하여 상기 게이트 라인 및 데이트 라인 사이에 개재시키는 TFT LCD의 게이트 절연막 형성방법으로서, 상기 게이트 절연막은 적어도 2층 이상의 다층으로 구성하는 것을 특징으로 한다.The gate insulating film forming method of the TFT LCD of the present invention for achieving the above object is a gate insulating film forming method of the TFT LCD interposed between the gate line and the data line in order to prevent a short between the gate line and the data line, The gate insulating film is characterized by consisting of at least two or more multilayers.
본 발명에 따르면, 게이트 절연막을 적어도 2층 이상으로 구성하여 각 층에서 발생되는 핀홀들의 위치가 상이하게 되도록 하기 때문에 핀홀에 의한 게이트 라인과 데이터 라인간의 쇼트를 방지할 수 있다.According to the present invention, since the gate insulating film is composed of at least two layers so that the positions of the pinholes generated in each layer are different, shorting between the gate line and the data line due to the pinholes can be prevented.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명의 실시예에 따른 TFT LCD의 게이트 절연막 형성방법을 설명하기 위한 단면도로서, 이를 설명하면 다음과 같다.3 is a cross-sectional view illustrating a method of forming a gate insulating film of a TFT LCD according to an exemplary embodiment of the present invention.
우선, 유리기판(11) 상에 공지된 방법으로 게이트 전극(12)을 형성한 상태에서, 상기 게이트 전극(12)이 덮혀지도록 제1절연막(13)을 증착한다. 이때, 제1절연막(13)은 SiON막으로 형성하며, 그 두께는 통상의 게이트 절연막 두께의 절반인 1,500 내지 1,750Å 정도로 한다.First, in a state in which the gate electrode 12 is formed on the glass substrate 11 by a known method, the first insulating layer 13 is deposited to cover the gate electrode 12. At this time, the first insulating film 13 is formed of a SiON film, and the thickness thereof is about 1,500 to 1,750 kPa, which is half the thickness of the normal gate insulating film.
여기서, 도시된 바와 같이, 제1절연막(13) 내에는 상기 게이트 전극(12) 및 유리기판(11)의 표면에 존재하는 파티클에 의해 제1핀홀들(P1)이 발생하게 된다.Here, as illustrated, the first pin holes P1 are generated by particles present on the surfaces of the gate electrode 12 and the glass substrate 11 in the first insulating layer 13.
다음으로, 제1절연막(13) 표면에 존재하는 파티클을 제거하기 위하여 클리닝 공정을 실시하고, 이어서, 클리닝 공정이 실시된 제1절연막(13) 상에 제2절연막(14)을 증착한다. 이때, 제2절연막(14)은 상기 제1절연막(13)과 동일 물질 및 동일 두께로 형성한다.Next, a cleaning process is performed to remove particles existing on the surface of the first insulating film 13, and then a second insulating film 14 is deposited on the first insulating film 13 subjected to the cleaning process. In this case, the second insulating layer 14 is formed of the same material and the same thickness as the first insulating layer 13.
여기서, 도시된 바와 같이, 제2절연막(14)의 내부에도 앞서와 마찬가지로 제2핀홀들(P2)이 발생되지만, 그 위치는 제1절연막(13)에 발생된 제1핀홀들(P1)과는 상이하게 된다.Here, as shown in the drawing, second pin holes P2 are generated in the second insulating layer 14, as well as the first pin holes P1 generated in the first insulating layer 13. Will be different.
즉, 제1절연막(13)에 대한 클리닝 공정을 실시하기 때문에 제2절연막(14)에 제2핀홀들(P2)이 발생되어도 제1절연막(13)에 발생된 제1핀홀들(P1)과 상기 제2절연막(14)에 발생된 제2핀홀들(P2)간의 위치는 서로 다르게 된다.That is, since the cleaning process is performed on the first insulating layer 13, even if the second pin holes P2 are generated in the second insulating layer 14, the first pin holes P1 generated in the first insulating layer 13 Positions between the second pin holes P2 generated in the second insulating layer 14 are different from each other.
따라서, 제1절연막(13)과 제2절연막(14)간의 상호 보완으로 인하여 핀홀들에 의해 게이트 전극(12)은 노출되지 않으며, 이에 따라, 핀홀에 의한 게이트 라인과 데이터 라인간의 쇼트를 방지할 수 있게 된다.Accordingly, the gate electrode 12 is not exposed by the pinholes because of the complementary between the first insulating layer 13 and the second insulating layer 14, thereby preventing a short between the gate line and the data line due to the pinhole. It becomes possible.
이상에서와 같이, 본 발명은 게이트 절연막을 2층 이상의 다층으로 구성하기 때문에 핀홀에 의해 게이트 라인이 노출되는 것을 방지할 수 있으며, 이에 따라, 게이트 라인과 데이터 라인간의 쇼트를 방지할 수 있게 되어 TFT LCD의 신뢰성을 향상시킬 수 있다.As described above, the present invention can prevent the gate line from being exposed by the pinhole because the gate insulating film is composed of a multilayer of two or more layers. Accordingly, the short between the gate line and the data line can be prevented. The reliability of the LCD can be improved.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980034937A KR20000015171A (en) | 1998-08-27 | 1998-08-27 | Method of manufacturing a gate insulation layer of a thin film transistor liquid crystal display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980034937A KR20000015171A (en) | 1998-08-27 | 1998-08-27 | Method of manufacturing a gate insulation layer of a thin film transistor liquid crystal display |
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| Publication Number | Publication Date |
|---|---|
| KR20000015171A true KR20000015171A (en) | 2000-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980034937A KR20000015171A (en) | 1998-08-27 | 1998-08-27 | Method of manufacturing a gate insulation layer of a thin film transistor liquid crystal display |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170027264A (en) * | 2015-08-26 | 2017-03-09 | 엘지디스플레이 주식회사 | Thin film transistor and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950013797A (en) * | 1993-11-09 | 1995-06-15 | 석진철 | Car Transmitter Control |
| KR19980023386A (en) * | 1996-09-30 | 1998-07-06 | 구자홍 | Thin film transistor including double gate insulating film |
| KR0124385Y1 (en) * | 1992-03-23 | 1998-10-15 | 강진구 | Liquid crystal display element of poly silicone thin film transistor |
| KR100290918B1 (en) * | 1992-12-29 | 2001-10-24 | 구본준, 론 위라하디락사 | Method for manufacturing thin film transistor |
-
1998
- 1998-08-27 KR KR1019980034937A patent/KR20000015171A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0124385Y1 (en) * | 1992-03-23 | 1998-10-15 | 강진구 | Liquid crystal display element of poly silicone thin film transistor |
| KR100290918B1 (en) * | 1992-12-29 | 2001-10-24 | 구본준, 론 위라하디락사 | Method for manufacturing thin film transistor |
| KR950013797A (en) * | 1993-11-09 | 1995-06-15 | 석진철 | Car Transmitter Control |
| KR19980023386A (en) * | 1996-09-30 | 1998-07-06 | 구자홍 | Thin film transistor including double gate insulating film |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20170027264A (en) * | 2015-08-26 | 2017-03-09 | 엘지디스플레이 주식회사 | Thin film transistor and display device |
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