JPH03105325A - Active matrix display device - Google Patents
Active matrix display deviceInfo
- Publication number
- JPH03105325A JPH03105325A JP1243869A JP24386989A JPH03105325A JP H03105325 A JPH03105325 A JP H03105325A JP 1243869 A JP1243869 A JP 1243869A JP 24386989 A JP24386989 A JP 24386989A JP H03105325 A JPH03105325 A JP H03105325A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bus wiring
- gate bus
- gate
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000000758 substrate Substances 0.000 claims description 33
- 239000010408 film Substances 0.000 description 30
- 239000010407 anodic oxide Substances 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 102000013462 Interleukin-12 Human genes 0.000 description 1
- 108010065805 Interleukin-12 Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、低抵抗の走査線を有する大型のアクティブマ
トリクス表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a large active matrix display device having low resistance scanning lines.
（従来の技術）
絶縁性基板上に絵素電極をマトリクス状に形成し、スイ
ッチング素子を介して絵素電極を駆動するアクティブマ
トリクス．方式は、液晶等を表示媒体として用いた表示
装置に用いられている。アクティブマトリクス方式は、
特に大型で高密度の表示を行う表示装置に用いられ、反
射型及び透過型の何れの表示装置にも用いることができ
るという利点を有している。(Prior art) An active matrix in which picture element electrodes are formed in a matrix on an insulating substrate, and the picture element electrodes are driven through switching elements. This method is used in display devices that use liquid crystal or the like as a display medium. The active matrix method is
It is particularly used for large-sized display devices that perform high-density display, and has the advantage that it can be used for both reflective and transmissive display devices.
アクティブマトリクス表示装置には、スイッチング素子
として薄膜トランジスタ（以下では「ＴＦＴＪと称する
）が多用されている。ＴＰＴにはアモルファスシリコン
（以下ではｒａ−ＳｊＪと称する）或いは多結晶シリコ
ンが、半導体材料として用いられる。第５図に従来の表
示装置に用いられるアクティブマトリクス基板のＴＦＴ
４０の部分の平面図を示す。尚、第５図では重畳形或さ
れた膜の周囲のみに斜線を施し、内部には斜線を施して
いない。第６図に第５図のＶｌ−ＶＩ線に沿った断面図
を示す。In active matrix display devices, thin film transistors (hereinafter referred to as "TFTJ") are often used as switching elements.Amorphous silicon (hereinafter referred to as RA-SjJ) or polycrystalline silicon is used as a semiconductor material for TPT. Figure 5 shows a TFT on an active matrix substrate used in a conventional display device.
A plan view of a section 40 is shown. In FIG. 5, only the periphery of the overlapping film is shaded, and the inside thereof is not shaded. FIG. 6 shows a sectional view taken along the line Vl-VI in FIG. 5.
このアクティブマトリクス基板は以下のようにして作製
される。ガラス基板２１上にスバッタリング法により、
層厚ａｏｏｏ〜４０００λのＴａ金属が堆積され、フォ
トリングラフィ法及びエッチングにより、ゲートバス配
線２３がパターン形成される。ＴＦＴ４０のゲート電極
２２はゲートバス配線２３の一部として形成され、ゲー
トバス配線２３より幅が大きくされている。ゲート電極
２２及びゲートバス配線２３の表面が陽極酸化され、ゲ
ート絶縁膜として機能する陽極酸化膜２４が形戊される
。This active matrix substrate is manufactured as follows. By sputtering method on the glass substrate 21,
A Ta metal having a layer thickness of aooo to 4000λ is deposited, and the gate bus wiring 23 is patterned by photolithography and etching. The gate electrode 22 of the TFT 40 is formed as a part of the gate bus wiring 23, and is made wider than the gate bus wiring 23. The surfaces of the gate electrode 22 and gate bus wiring 23 are anodized to form an anodic oxide film 24 that functions as a gate insulating film.
次に、基板２ｌの全面にプラズマＣＶＤ法により、層厚
２０００〜４０００Ａの窒化シリコン（以下ではｒＳＩ
ＮｘＪと称する）から或るゲート絶縁膜２５が形成され
る。更に基板全面に、後に半導体層２６となるａ−Ｓｆ
（ｉ）層（層厚１００〜３０００入）、及び後に絶縁
層２７となるＳＩＮＸ層（層厚２００ｏ〜３ｏｏｏＡ）
が順次堆積される。次に、上記ＳＩＮＸ層が所定の形状
にパターニングされ、ゲート電極２２の上方のみを残し
て絶縁層２７が形成される。Next, the entire surface of the substrate 2l is coated with silicon nitride (hereinafter rSI
A certain gate insulating film 25 is formed from NxJ). Furthermore, a-Sf, which will later become the semiconductor layer 26, is applied to the entire surface of the substrate.
(i) layer (layer thickness 100 to 3000), and SINX layer (layer thickness 200 to 300A), which will later become the insulating layer 27
are deposited sequentially. Next, the SINX layer is patterned into a predetermined shape, and an insulating layer 27 is formed leaving only the upper part of the gate electrode 22.
絶縁層２７を覆って全面に、後にコンタクト層２８とな
るＰ（リン）をドーブしたａ−ＳＪ（ｎ＋）層（層厚３
００ 〜２０００Ａ）が、ブラズ７ＣＶＤ法により堆積
される。次に、上述のａ−３１（１）層及びａ−Ｓｉ（
ｎ”）層が同時に所定の形状にパターニングされ、半導
体層２６及びコンタクト層２８が形成される。この時点
ではコンタクト層２８は、絶縁層２７上で連続している
。Covering the insulating layer 27 and covering the entire surface, a P (phosphorus) doped a-SJ(n+) layer (layer thickness 3
00 to 2000 A) are deposited by Blaz 7 CVD method. Next, the above-mentioned a-31(1) layer and a-Si(
n'') layer is simultaneously patterned into a predetermined shape to form a semiconductor layer 26 and a contact layer 28. At this point, the contact layer 28 is continuous on the insulating layer 27.
この基板の全面にＭｏＳ Ｔｉ．．Ａ１等の金属が２０
００〜１００００大の厚さに堆積され、この金属層がエ
ッチングによりパターニングされて、ソース電極２９、
及びドレイン電極３ｌが形或される。このとき、絶縁層
２７上ではコンタクト層２８も同時にエッチング除去さ
れ、ソース電極２９の下方の部分と、ドレイン電極３１
の下方の部分とに分割される。以上のようにしてＴＦＴ
４０が形或される。次に、スパッタリングにより基板全
面に、ＩＴＯ膜が堆積される。このＩＴＯ膜が所定の形
状にパターニングされ、絵素電極３２が形成される。MoS Ti. ．． 20 metals such as A1
The metal layer is deposited to a thickness of 0.00 to 10000, and this metal layer is patterned by etching to form the source electrode 29,
and a drain electrode 3l are formed. At this time, the contact layer 28 on the insulating layer 27 is also etched away at the same time, and the lower part of the source electrode 29 and the drain electrode 31 are etched away.
The lower part of the In the above manner, TFT
40 is formed. Next, an ITO film is deposited on the entire surface of the substrate by sputtering. This ITO film is patterned into a predetermined shape to form a picture element electrode 32.
多数のこのようなＴＦＴ４ ０が、ゲートバス配線２３
上に形成され、アクティブマトリクス基板が構或されて
いる。ソースバス配線３０はゲートバス配線２３に直交
して設けられ、ゲートバス配線２３の方向に対して直角
方向に並ぶそれぞれのＴＦＴ４０のソース電極２９に接
続されている。A large number of such TFTs 40 are connected to the gate bus wiring 23.
An active matrix substrate is formed thereon. The source bus wiring 30 is provided perpendicularly to the gate bus wiring 23 and is connected to the source electrodes 29 of the respective TFTs 40 arranged in a direction perpendicular to the direction of the gate bus wiring 23 .
第７図に第５図の基板を用いたアクティブマトリクス表
示装置の断面図を示す。第７図では簡単のために、ＴＦ
Ｔ４０を構成している膜、電極等の一部を省略して描か
れている。ガラス基板２１上にＴＦＴ４０，絵素電極３
２等が形成されたアクティブマトリクス基板に対向して
、ガラス基板４１が設けられている。ガラス基板４１上
には対向電極４２が形成されている。２つの基板２１及
び４ｌの間には、液晶４３が封入されている。絵素電極
３２と対向電極４２との間に電圧が印加され、液晶４３
中の液晶分子の配向変換が行われる。FIG. 7 shows a sectional view of an active matrix display device using the substrate of FIG. 5. In Figure 7, for simplicity, TF
It is drawn with some of the films, electrodes, etc. that make up T40 omitted. TFT 40 and picture element electrode 3 on glass substrate 21
A glass substrate 41 is provided opposite to the active matrix substrate on which the substrates 2 and the like are formed. A counter electrode 42 is formed on the glass substrate 41. A liquid crystal 43 is sealed between the two substrates 21 and 4l. A voltage is applied between the picture element electrode 32 and the counter electrode 42, and the liquid crystal 43
The orientation of the liquid crystal molecules inside is changed.
このようなアクティブマトリクス表示装置では、走査信
号がゲートバス配線２３に順次入力され、これに対応す
るソースバス配線３０に画像信号が入力され、絵素電極
３２が駆動される。ゲートバス配線２３及びソースバス
配線３０の交点は、例えば４８０Ｘ６４Ｑの絵素を有す
る表示装置では、ｓａｔｚｏｏＨ所にも達する。この多
数の交点のうち、一箇所にでもゲートバス配線２３及び
ンースバス配線３０の間のリークが生じると、該リーク
箇所を交点とする十字型のライン欠陥が生じる。In such an active matrix display device, scanning signals are sequentially input to the gate bus lines 23, image signals are input to the corresponding source bus lines 30, and the picture element electrodes 32 are driven. For example, in a display device having 480×64Q picture elements, the intersection of the gate bus line 23 and the source bus line 30 reaches the satzooH point. If a leak occurs between the gate bus wiring 23 and the second bus wiring 30 at even one of these many intersections, a cross-shaped line defect occurs with the leakage location as the intersection.
このようなライン欠陥は画像品位を著しく低下させ、表
示装置の歩留りを低下させる。Such line defects significantly degrade image quality and reduce the yield of display devices.
上述の表示装置では、ゲートバス配線２３及びソースバ
ス配線３０の間を確実に絶縁するため、陽極酸化膜２４
の形成が可能なＴａ金属がゲートバス配線２３に用いら
れている。しかも、Ｔａ金属でゲートバス配線２３を形
成すると、ゲートバス配線２３の側面はなだらかな傾斜
を持ったテーバ状に形成される。そのため、ゲートバス
配線２３上に交差するソースバス配線３０が段切れを起
こし難いという利点がある。In the display device described above, in order to reliably insulate between the gate bus wiring 23 and the source bus wiring 30, the anodic oxide film 24 is
The gate bus wiring 23 is made of Ta metal, which can form the following. Moreover, when the gate bus wiring 23 is formed of Ta metal, the side surfaces of the gate bus wiring 23 are formed into a tapered shape with a gentle slope. Therefore, there is an advantage that the source bus wiring 30 crossing over the gate bus wiring 23 is less likely to break.
（発明が解決しようとする課題）
ところが、ゲートバス配線２３に用（＼られているＴａ
金属は比抵抗が大きいため、長いゲートバス配線２３を
有する大型の精細な表示を行う表示装置では、走査信号
が減衰してしまう。そのため、ゲートバス配線２３の走
査信号の入力部の近くに接続される絵素では充分な輝度
が得られるが、該入力部から遠くに接続される絵素では
充分な輝度が得られなくなる。従って、同一のゲートバ
ス配線２３上の絵素の列に、走査信号の入力部に近い方
から遠い方にかけて、輝度傾斜が生じることとなる。こ
のような輝度傾斜により、画面上の表示が不均一となる
。(Problem to be solved by the invention) However, the Ta used in the gate bus wiring 23
Since metal has a high specific resistance, the scanning signal is attenuated in a display device that has a long gate bus line 23 and performs a large, fine display. Therefore, picture elements connected near the scanning signal input section of the gate bus wiring 23 can obtain sufficient brightness, but picture elements connected far from the input section cannot obtain sufficient brightness. Therefore, in the rows of picture elements on the same gate bus wiring 23, a brightness gradient occurs from the side nearer to the input part of the scanning signal to the side farther away. Such a brightness gradient causes non-uniform display on the screen.
このような欠点を解消するために、ゲートバス配線２３
をＡＩ金属層上にＴａ金属層を重ねた２層構造とするこ
とが考えられる。ＡＩ金属はＴａよりら比抵抗が小さい
ので、上述の欠点は解消される。しかもＴａ金属層上に
は陽極酸化膜２４を形成し得る。このような２層構造を
有するゲートバス配線２３は、ＡＩ金属とＴａ金属とが
順に積層された後、エッチングによって同時にバターニ
ングされる。このようにして作製されたゲートバス配綿
２３の断面図を第８図に示す。第８図に示すように、Ａ
Ｉ金属層３３とＴａ金属層３４とのエッチング速度の違
いにより、ゲートバス配線２３の断面は逆テーパ状に形
或されている。即ち、Ａ１金属層３３のエッチング速度
はＴａ金属層３４のそれに比べて大きいため、このよう
な形状となる。In order to eliminate such drawbacks, the gate bus wiring 23
It is conceivable to have a two-layer structure in which a Ta metal layer is stacked on an AI metal layer. Since AI metal has a lower specific resistance than Ta, the above-mentioned drawbacks are eliminated. Moreover, the anodic oxide film 24 can be formed on the Ta metal layer. In the gate bus wiring 23 having such a two-layer structure, AI metal and Ta metal are sequentially laminated and then patterned at the same time by etching. A cross-sectional view of the gate bus batting 23 produced in this manner is shown in FIG. As shown in Figure 8, A
Due to the difference in etching speed between the I metal layer 33 and the Ta metal layer 34, the cross section of the gate bus wiring 23 is shaped in a reverse tapered shape. That is, since the etching rate of the A1 metal layer 33 is higher than that of the Ta metal layer 34, such a shape is obtained.
ゲートバス配線２３が逆テーパ状となると、ゲートバス
配線２３上の全面に形戊されるゲート絶縁膜２５はゲー
トバス配線２３を完全に被覆し得ない。ゲートバス配線
２３の被覆が不完全であると、後の例えばＴＰＴの形戊
工程で用いられるエッチャントによって、ゲートバス配
線２３が侵食される。このような侵食が発生すると、ゲ
ートバス配線２３の絶縁耐圧の低下や剥離につながる。When the gate bus wiring 23 has a reverse tapered shape, the gate insulating film 25 formed over the entire surface of the gate bus wiring 23 cannot completely cover the gate bus wiring 23. If the gate bus wiring 23 is incompletely covered, the gate bus wiring 23 will be eroded by an etchant used later, for example, in a TPT forming process. When such erosion occurs, the dielectric strength of the gate bus wiring 23 decreases and the gate bus wiring 23 peels off.
このような欠点を解消するために、第９図に示すように
、ゲートバス配線２３を比抵抗の小さいＡＩ金属等から
成る下部ゲート配線３３と、下部ゲート配線３３を被覆
し、Ｔａ金属から成る上部ゲート配線３４とによって構
成することが考えられる。このような構成によれば、比
抵抗の小さい下部ゲート配線３３によって前述の不均一
表示の発生が防止される。ゲートバス配線２３の断面形
状が逆テーパ状となることもない。In order to eliminate such drawbacks, as shown in FIG. 9, the gate bus wiring 23 is coated with a lower gate wiring 33 made of an AI metal or the like having a low resistivity, and a lower gate wiring 33 made of a Ta metal. It is conceivable that the upper gate wiring 34 be used. According to such a configuration, the occurrence of the above-mentioned non-uniform display can be prevented by the lower gate wiring 33 having a small specific resistance. The cross-sectional shape of the gate bus wiring 23 does not have a reverse tapered shape.
ところが、このような２層構造を有するゲートバス配線
を形或するには、２度のパターン形成を行う必要がある
。そのために製造コストが高くなるという新たな問題点
が生しる。更に、このような２ＦｆｊＩ構造を有するゲ
ートバス配線２３では、上部ゲート配線３４の幅は下部
ゲート配線３３より１〜５μｍ大きくされ、上部ゲート
配線３４は下部ゲート配線３３を完全に被覆して形成さ
れることが必要である。なぜなら、Ｔａ金属の上部ゲー
ト配線３４をパターン形或する工程では、Ｔａ金属のエ
ッチング速度よりもＡＩのそれの方が遥かに大きいから
である。このようにゲートバス配線２３の幅が大きくな
ると、表示画面全体に対してゲートバス配線の占める割
合が大きくなり、開口率が低下する。開口率が低下する
と表示画面が暗くなるという問題点が生じる。However, in order to form a gate bus wiring having such a two-layer structure, it is necessary to perform pattern formation twice. This creates a new problem of increased manufacturing costs. Furthermore, in the gate bus wiring 23 having such a 2FfjI structure, the width of the upper gate wiring 34 is made 1 to 5 μm larger than the lower gate wiring 33, and the upper gate wiring 34 is formed to completely cover the lower gate wiring 33. It is necessary to This is because, in the step of patterning the Ta metal upper gate wiring 34, the etching rate of AI is much higher than that of Ta metal. When the width of the gate bus wiring 23 increases in this way, the ratio of the gate bus wiring to the entire display screen increases, and the aperture ratio decreases. When the aperture ratio decreases, a problem arises in that the display screen becomes dark.
本発明は上述の問題点を解決するものであり、本発明の
目的は、比抵抗の小さいゲート配線を有し、開口率が低
下しないアクティブマトリクス表示装置を提供すること
である。The present invention solves the above-mentioned problems, and an object of the present invention is to provide an active matrix display device that has a gate wiring having a low specific resistance and that does not reduce the aperture ratio.
（課題を解決するための手段）
本発明のアクティブマトリクス表示装置は、対の絶縁性
基板と、該一対の基板の何れか一方の基板内面にマトリ
クス状に配列された絵素電極と、該絵素電極の間に並行
する走査線と、を有するアクティブマトリクス表示装置
であって、該走査線は、第１の金属層と第２の金属層と
が交互に重畳された積層構造を有し、該第１の金属層の
エソチング速度は該第２の金属層のエッチング速度より
大きく、該第１の金属層の比抵抗は該第２の金属層の比
抵抗より小く設定されており、そのことによって上記目
的が達成される。(Means for Solving the Problems) The active matrix display device of the present invention includes a pair of insulating substrates, pixel electrodes arranged in a matrix on the inner surface of one of the pair of substrates, and An active matrix display device having scanning lines parallel to each other between elementary electrodes, the scanning lines having a laminated structure in which first metal layers and second metal layers are alternately overlapped, The etching rate of the first metal layer is higher than the etching rate of the second metal layer, and the resistivity of the first metal layer is set to be lower than the resistivity of the second metal layer. This achieves the above objective.
（作用）
第４図に示すように、本発明のアクティブマトリクス表
示装置では、走査線は第１の金属層３５と第２の金属層
３６とが交互に重畳された積層構造を有している。第１
の金属層３５は第２の金属層３６より比抵抗が小さいの
で走査線全体の抵抗は低減される。これにより、均一な
表示画面が得られる。また、第２の金属層３６のエッチ
ング速度は第１の金属層３５のエッチング速度より小さ
い。エッチング速度の異なる金属層を交互に重畳した後
、エッチングによって走査線のバターニングを行うと、
走査線の断面形状は、基板２ｌ上から遠ざかるに従って
幅が狭くされたテーパ状となる。走査線の断面形状がテ
ーバ状であると、更に走査線の上に形成される絶縁膜は
走査線を完全に被覆して形成される。走査線の被覆が完
全であると、後の例えばスイッチング素子の形成工程に
用いられるエッチャントによって、走査線が侵食される
のを防止し得る。(Function) As shown in FIG. 4, in the active matrix display device of the present invention, the scanning line has a laminated structure in which the first metal layer 35 and the second metal layer 36 are alternately overlapped. . 1st
Since the metal layer 35 has a lower resistivity than the second metal layer 36, the resistance of the entire scanning line is reduced. This provides a uniform display screen. Further, the etching rate of the second metal layer 36 is lower than the etching rate of the first metal layer 35. After alternating metal layers with different etching speeds, patterning of scanning lines is performed by etching.
The scanning line has a tapered cross-sectional shape whose width becomes narrower as it goes away from the substrate 2l. When the cross-sectional shape of the scanning line is tapered, the insulating film formed on the scanning line is formed to completely cover the scanning line. If the scanning line is completely covered, the scanning line can be prevented from being eroded by an etchant used later, for example, in a step of forming a switching element.
（実施例） 本発明を実施例について以下に説明する。(Example) The invention will now be described with reference to examples.
第１図に本発明の表示装置の１実施例に用いられるアク
ティブマトリクス基板の平面図を示す。FIG. 1 shows a plan view of an active matrix substrate used in one embodiment of the display device of the present invention.
尚、第１図では重畳形成された膜の周囲のみに斜線を施
し、内部には斜線を施していない。第２図に第１図のｎ
−ｎ線に沿った断面図を示す。第３Ａ図〜第３Ｆ図に第
１図のアクティブマトリクス基板の製造工程を示す。In FIG. 1, only the periphery of the overlapping films is shaded, and the inside is not shaded. Figure 2 shows n in Figure 1.
A cross-sectional view taken along the -n line is shown. 3A to 3F show the manufacturing process of the active matrix substrate of FIG. 1.
本実施例を製造工程に従って説明する。ガラス基板ｌ上
に３層のＴａ金属層５と、２層のＡＩ金属層４とをスパ
ッタリング法により、交互に連続して堆積した。最上層
はＴａ金属層５である。Ｔａ金属層５及びＡＩ金属層４
の１層当りの層厚は５０〜３００大である。最上層のＴ
ａ金属層５上に所定の形状のフォトレジスト膜からなる
マスクを形成した。このマスクを用いてエッチングを行
い、第１図に示す形状のゲートバス配線３を形成したく
第３Ａ図）。このエッチングにより、ゲートバス配線３
の断面形状は、基板ｌから遠ざかるにつれて幅が小さく
されたテーバ状となる。尚、第ｌ図に示すように、ＴＦ
Ｔ５０のゲート電極２は、ゲートバス配線３の一部とし
て形戊される。This example will be explained according to the manufacturing process. Three Ta metal layers 5 and two AI metal layers 4 were alternately and successively deposited on a glass substrate l by sputtering. The top layer is a Ta metal layer 5. Ta metal layer 5 and AI metal layer 4
The layer thickness per layer is 50 to 300 mm. Top layer T
A A mask made of a photoresist film having a predetermined shape was formed on the metal layer 5. Etching is performed using this mask to form the gate bus wiring 3 having the shape shown in FIG. 1 (FIG. 3A). With this etching, the gate bus wiring 3
The cross-sectional shape becomes a tapered shape whose width becomes smaller as the distance from the substrate l increases. In addition, as shown in Figure l, TF
The gate electrode 2 of T50 is formed as part of the gate bus wiring 3.
ゲート電極２となる部分の幅は、ゲートバス配線３のゲ
ート電極２以外の部分の幅に比べ大きくされている。The width of the portion that will become the gate electrode 2 is larger than the width of the portion of the gate bus wiring 3 other than the gate electrode 2.
次に、ゲートバス配１３の陽極酸化を行い、ゲートバス
配線３の最上層のＴａ金属層５をＴａ２０５とした。こ
の時、ゲートバス配線３の側面に露出しているＴａ金属
層５も同時に陽極酸化される。Next, the gate bus wiring 13 was anodized, and the uppermost Ta metal layer 5 of the gate bus wiring 3 was made of Ta205. At this time, the Ta metal layer 5 exposed on the side surface of the gate bus wiring 3 is also anodized at the same time.
Ｔａ金属層５の陽極酸化により、ゲートバス記線３の上
面及び側面には陽極酸化膜６が形成される（第３図Ｂ）
。陽極酸化膜６はゲート絶縁膜として機能する。また、
Ｔａ２０５から成る陽極酸化膜６は耐エッチング性に優
れているので、後のエッチング工程でゲートバス配線３
を保護する役割も果たすことができる。By anodic oxidation of the Ta metal layer 5, an anodic oxide film 6 is formed on the top and side surfaces of the gate bus markings 3 (FIG. 3B).
. The anodic oxide film 6 functions as a gate insulating film. Also,
Since the anodic oxide film 6 made of Ta205 has excellent etching resistance, the gate bus wiring 3 will be removed in the subsequent etching process.
It can also play a role in protecting the environment.
更に、基板１の全面にプラズマＣＶＤ法により、ＳＩＮ
ｘから成るゲート絶縁膜７（層厚２０００〜５０００入
）を形成した。次に、基板ｌの全面に、後に半導体層８
となるａ−Ｓｉ（１）層（層厚３００〜ｌ０００＾）、
及び後に絶縁層９となるＳＩＮＮ層（Ｒ厚５００〜２０
００大）を順次堆積させた。後に絶縁層９となる上記Ｓ
ＩＮＸ層を所定の形状にバターニングし、ゲート電極２
の上方のみを残して絶縁層９を形成した（第３Ｃ図）。Furthermore, SIN is formed on the entire surface of the substrate 1 by plasma CVD method.
A gate insulating film 7 (layer thickness: 2,000 to 5,000 layers) was formed. Next, a semiconductor layer 8 is formed on the entire surface of the substrate l.
a-Si(1) layer (layer thickness 300 to 1000^),
and a SINN layer (R thickness 500 to 20
00 large) were deposited sequentially. The above S which will later become the insulating layer 9
The INX layer is patterned into a predetermined shape, and the gate electrode 2 is formed.
An insulating layer 9 was formed leaving only the upper part (FIG. 3C).
絶縁層９を覆って全面に、後にコンタクト層ｌＯとなる
Ｐ（リン）をドーブしたａ−Ｓｔ（ｎ″））層（層厚５
００〜１５００λ）を、プラズマｃｖＤ法により堆積し
た。次に、上述のａ−Ｓｉ（ｉ）層及びａ−Ｓ１（ｎ“
）層を所定の形状にパターニングし、半導体層８及びコ
ンタクト層１ｏを形成した（第３Ｄ図）。コンタクト層
１０は半導体層８と、後に形成されるソース電極１１及
びドレイン電極１３とのオーミックコンタクトのために
設けられる。この時点ではコンタクト層１ｏは、絶縁層
９上で連続している。Covering the insulating layer 9 and covering the entire surface, a P (phosphorus) doped a-St(n'') layer (layer thickness 5
00 to 1500λ) was deposited by plasma CVD method. Next, the above a-Si(i) layer and a-S1(n“
) layer was patterned into a predetermined shape to form a semiconductor layer 8 and a contact layer 1o (FIG. 3D). The contact layer 10 is provided for ohmic contact between the semiconductor layer 8 and a source electrode 11 and a drain electrode 13 that will be formed later. At this point, the contact layer 1o is continuous on the insulating layer 9.
この基板の全面にＭｏ金属層（層厚２０００〜３０００
Ａ）を堆積し、このＭｏ金属層をエッチングによりバタ
ーニングして、ソース電極ｌｌ及びドレイン電極ｌ３を
形成した。この時、絶縁層９上ではコンタクト層１０も
同時にエッチング除去され、ソース電極１１の下方の部
分と、ドレイン電極１３の下方の部分とに分割される（
第３Ｅ図）。また、第１図に示すソースバス配線ｌ２も
この時に同時に形或される。ソースバス配線１２はゲー
ト絶縁膜７及び陽極酸化膜６を介して、ゲートバス配線
３と交差することになる。Mo metal layer (layer thickness 2000-3000
A) was deposited, and this Mo metal layer was patterned by etching to form a source electrode 11 and a drain electrode 13. At this time, the contact layer 10 on the insulating layer 9 is also etched away, and is divided into a portion below the source electrode 11 and a portion below the drain electrode 13 (
Figure 3E). Further, the source bus wiring 12 shown in FIG. 1 is also formed at the same time. The source bus wiring 12 intersects with the gate bus wiring 3 via the gate insulating film 7 and the anodic oxide film 6.
次に、スパッタリングにより基板１の全面に、ＩＴＯ膜
を堆積させた。このＩＴＯ膜が所定の形状にパターニン
グされ、絵素電極１４が形戊され（第３Ｆ図）、アクテ
ィブマトリクス基板が作製される。Next, an ITO film was deposited on the entire surface of the substrate 1 by sputtering. This ITO film is patterned into a predetermined shape, the picture element electrode 14 is formed (FIG. 3F), and an active matrix substrate is produced.
本実施例では、ゲートバス配線３は比抵抗の小さいＡＩ
金属層４と、Ｔａ金属層５とが重畳された積層構造を有
しているので、ゲートバス配線３の抵抗は低減されてい
る。従って、本実施例では同一ゲートバス配線３に接続
された絵素電極１４によって表示される絵素の列に、輝
度傾斜は生じない。従って、均一な表示画面が得られる
。In this embodiment, the gate bus wiring 3 is made of AI with low specific resistance.
Since it has a laminated structure in which the metal layer 4 and the Ta metal layer 5 are overlapped, the resistance of the gate bus wiring 3 is reduced. Therefore, in this embodiment, no brightness gradient occurs in the rows of picture elements displayed by the picture element electrodes 14 connected to the same gate bus wiring 3. Therefore, a uniform display screen can be obtained.
本実施例のゲートバス配線３の上には、Ｔａ金属層５を
陽極酸化して得られる陽極酸化膜６が形戊されている。An anodic oxide film 6 obtained by anodizing the Ta metal layer 5 is formed on the gate bus wiring 3 of this embodiment.
また、ゲートバス配線３の断面形状は、基板１上から遠
ざかるに従って幅が小さくされたテーパ状である。この
ようにゲートパス配線３の断面形状がテーパ状であると
、陽極酸化膜６を介してゲートバス配線３上に形成され
るゲート絶縁膜７は、ゲートバス配ｆｉ３及び陽極酸化
膜６を確実に被覆し得る。ゲート絶縁膜７の被覆が確実
であること、及び陽極酸化膜６を形成し得ることによっ
て、後の例えばＴＦＴ５０の形或工程で使用されるエッ
チャントによって、ゲートバス配線３が侵食されるのを
防止し得る。また、ソースバス配線１２とゲートバス配
線との間のリークも防がれる。更に、ゲートバス配線３
の断面形状がテーパ状であると、ゲートバス配線３と交
差するソースバス配線１２の段切れが防止される。Further, the cross-sectional shape of the gate bus wiring 3 is tapered such that the width becomes smaller as the distance from the substrate 1 increases. When the cross-sectional shape of the gate pass wiring 3 is tapered in this way, the gate insulating film 7 formed on the gate bus wiring 3 through the anodic oxide film 6 can reliably connect the gate bus wiring fi 3 and the anodic oxide film 6. Can be coated. By ensuring the coverage of the gate insulating film 7 and by forming the anodic oxide film 6, it is possible to prevent the gate bus wiring 3 from being eroded by the etchant used later, for example, in a process for forming the TFT 50. It is possible. Furthermore, leakage between the source bus wiring 12 and the gate bus wiring is also prevented. Furthermore, gate bus wiring 3
When the cross-sectional shape of the source bus line 12 is tapered, breakage of the source bus line 12 that intersects with the gate bus line 3 is prevented.
（発明の効果）
本発明のアクティブマトリクス表示装置は、比抵抗の小
さい走査線を有しているので、均一な表示画面を有する
表示装置が得られる。また、本発明の表示装置では走査
線の幅を大きくする必要がないので、開口率の低下も生
じない。従って、本発明によれば均一で明るい表示画面
を有する表示装置が得られ、表示装置の歩留りも向上す
る。更に、表示装置の大型化、精細化にも対処し得る。(Effects of the Invention) Since the active matrix display device of the present invention has scanning lines with low specific resistance, a display device having a uniform display screen can be obtained. Furthermore, in the display device of the present invention, there is no need to increase the width of the scanning line, so the aperture ratio does not decrease. Therefore, according to the present invention, a display device having a uniform and bright display screen can be obtained, and the yield of the display device can also be improved. Furthermore, it is possible to cope with the increase in size and definition of display devices.
４． の な！ ■
第１図は本発明のアクティブマトリクス表示装置の１実
施例に用いられるアクティブマトリクス基板の平面図、
第２図は第１図のｎ−ｎ線に沿った断面図、第３Ａ図〜
第３Ｆ図は第２図の基板の製造工程を示す図、第４図は
本発明表示装置の走査線の断面構成の説明図、第５図は
従来のアクティブマトリクス基板の平面図、第６図は第
５図のＶｌ−ＶＩ線に沿った断面図、第７図は従来のア
クティブマトリクス表示装置の断面図、第８図は２層構
造を有するゲートバス配線の断面図、第９図はゲートバ
ス配線の改良例の断面図である。4. No! ■ Figure 1 is a plan view of an active matrix substrate used in one embodiment of the active matrix display device of the present invention;
Figure 2 is a cross-sectional view taken along the line nn in Figure 1, Figures 3A--
3F is a diagram showing the manufacturing process of the substrate in FIG. 2, FIG. 4 is an explanatory diagram of the cross-sectional structure of the scanning line of the display device of the present invention, FIG. 5 is a plan view of a conventional active matrix substrate, and FIG. 6 is a sectional view taken along the line Vl-VI in Fig. 5, Fig. 7 is a sectional view of a conventional active matrix display device, Fig. 8 is a sectional view of a gate bus wiring having a two-layer structure, and Fig. 9 is a sectional view of a gate bus wiring. FIG. 3 is a sectional view of an improved example of bus wiring.
１・・・ガラス基板、２・・・ゲート電極、３・・・ゲ
ートバス配線、４・・・ＡＩ金属層、５・・・Ｔａ金属
層、６・・・陽極酸化膜、７・・・ゲート絶縁膜、８・
・・半導体層、１ｌ・・・ソース’ＩＬ１２・・・ソー
スバスＥｌＫ、１３・・・ドレイン電極、ｌ４・・・絵
素電極、５０・・・Ｔ Ｆ Ｔ．以上DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Gate electrode, 3... Gate bus wiring, 4... AI metal layer, 5... Ta metal layer, 6... Anodic oxide film, 7... Gate insulating film, 8.
...Semiconductor layer, 1l...Source 'IL12...Source bus ElK, 13...Drain electrode, l4...Picture element electrode, 50...T F T. that's all
Claims (1)
の基板内面にマトリクス状に配列された絵素電極と、該
絵素電極の間に並行する走査線と、を有するアクティブ
マトリクス表示装置であって、該走査線は、第１の金属
層と第２の金属層とが交互に重畳された積層構造を有し
、該第１の金属層のエッチング速度は該第２の金属層の
エッチング速度より大きく、該第１の金属層の比抵抗は
該第２の金属層の比抵抗より小く設定されているアクテ
ィブマトリクス表示装置。1. An active matrix display comprising a pair of insulating substrates, picture element electrodes arranged in a matrix on the inner surface of one of the pair of substrates, and scanning lines parallel to each other between the picture element electrodes. The scanning line has a laminated structure in which first metal layers and second metal layers are alternately stacked, and the etching rate of the first metal layer is higher than that of the second metal layer. , and the resistivity of the first metal layer is set to be lower than the resistivity of the second metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24386989A JPH0820645B2 (en) | 1989-09-19 | 1989-09-19 | Active matrix display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24386989A JPH0820645B2 (en) | 1989-09-19 | 1989-09-19 | Active matrix display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03105325A true JPH03105325A (en) | 1991-05-02 |
| JPH0820645B2 JPH0820645B2 (en) | 1996-03-04 |
Family
ID=17110190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24386989A Expired - Lifetime JPH0820645B2 (en) | 1989-09-19 | 1989-09-19 | Active matrix display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0820645B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100759153B1 (en) * | 2004-02-19 | 2007-09-14 | 샤프 가부시키가이샤 | Method for manufacturing conductive element substrate, conductive element substrate, method for manufacturing liquid crystal display, liquid crystal display, and electronic information equipment |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015047719A1 (en) | 2013-09-25 | 2015-04-02 | Ticona Llc | Method of polyarylene sulfide crystallization |
| US9562139B2 (en) | 2013-09-25 | 2017-02-07 | Ticona Llc | Process for forming low halogen content polyarylene sulfides |
| US9403948B2 (en) | 2013-09-25 | 2016-08-02 | Ticona Llc | Salt byproduct separation during formation of polyarylene sulfide |
| WO2015047718A1 (en) | 2013-09-25 | 2015-04-02 | Ticona Llc | Multi-stage process for forming polyarylene sulfides |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246873A (en) * | 1987-04-02 | 1988-10-13 | Seikosha Co Ltd | Thin film transistor |
-
1989
- 1989-09-19 JP JP24386989A patent/JPH0820645B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246873A (en) * | 1987-04-02 | 1988-10-13 | Seikosha Co Ltd | Thin film transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100759153B1 (en) * | 2004-02-19 | 2007-09-14 | 샤프 가부시키가이샤 | Method for manufacturing conductive element substrate, conductive element substrate, method for manufacturing liquid crystal display, liquid crystal display, and electronic information equipment |
| US7550183B2 (en) | 2004-02-19 | 2009-06-23 | Sharp Kabushiki Kaisha | Method for manufacturing conductive element substrate, conductive element substrate, method for manufacturing liquid crystal display, liquid crystal display and electronic information equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0820645B2 (en) | 1996-03-04 |
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