JPS63246873A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63246873A JPS63246873A JP8164387A JP8164387A JPS63246873A JP S63246873 A JPS63246873 A JP S63246873A JP 8164387 A JP8164387 A JP 8164387A JP 8164387 A JP8164387 A JP 8164387A JP S63246873 A JPS63246873 A JP S63246873A
- Authority
- JP
- Japan
- Prior art keywords
- heat
- resisting
- metal
- resistant
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 14
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000010030 laminating Methods 0.000 claims abstract 2
- 239000002253 acid Substances 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 24
- 238000005530 etching Methods 0.000 abstract description 14
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract description 11
- 239000011733 molybdenum Substances 0.000 abstract description 11
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 7
- 239000011651 chromium Substances 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 6
- 229910052804 chromium Inorganic materials 0.000 abstract description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 3
- 239000007772 electrode material Substances 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract description 3
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 2
- 230000007797 corrosion Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract 1
- 229910001120 nichrome Inorganic materials 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001362 Ta alloys Inorganic materials 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005477 sputtering target Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は薄膜トランジスタに関するもので、とりわけ
液晶表示パネルなどに使用される薄膜トランジスタに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to thin film transistors, and particularly to thin film transistors used in liquid crystal display panels and the like.
［従来の技術］
従来の薄膜トランジスタの構成について、液晶表示パネ
ルについて実施した例を製造工程を追って説明する。[Prior Art] Regarding the structure of a conventional thin film transistor, an example implemented for a liquid crystal display panel will be explained following the manufacturing process.
ガラスまたは石英よりなる基板１の上にモリブデン、ニ
ッケルクロム合金、タンタル、クロムなどの耐熱性金属
よりなるゲート電極２をパターン形成する。さらにプラ
ズマＣＶＤ法により絶縁膜３としてシリコン窒化膜また
はシリコン酸化膜を形成後、イントリンシックアモルフ
ァスシリコン膜４、リンＰをドープしたｎ型アモルファ
スシリコン膜５を連続で成膜する（第３図Ａ）。その後
イントリンシックアモルファスシリコン膜４、ｎ型アモ
ルファスシリコン膜５の必要部分を残してエツチングす
るｄこの上にソース電極６、ドレイン電極７をＩＴＯな
どの透明電極でパターン形成し、画素電極８はドレイン
電極７と同時に接続して形成する（第３図Ｂ）。画素電
極８はドレイン電極７とは別に形成してもよいことはも
ちろんである。ソース電極６、ドレイン電極７を形成後
、これら電極をマスクにしてｎ型アモルファスシリコン
膜５を部分的にエツチングして、イントリンシックアモ
ルファスシリコン膜４を残してチャンネル９を形成する
。パシベーション膜１０としてシリコン酸化膜またはシ
リコン窒化膜をプラズマＣＶＤ法にて成膜する（第３図
Ｃ）。さらにアルミニウムやモリブデンなどにより光遮
蔽膜１１を形成し、液晶配向膜１２としてポリイミド型
の樹脂やシリコン酸化膜を形成する（第３図Ｄ）。A gate electrode 2 made of a heat-resistant metal such as molybdenum, nickel-chromium alloy, tantalum, or chromium is patterned on a substrate 1 made of glass or quartz. Furthermore, after forming a silicon nitride film or a silicon oxide film as an insulating film 3 by plasma CVD method, an intrinsic amorphous silicon film 4 and an n-type amorphous silicon film 5 doped with phosphorus P are successively formed (FIG. 3A). . After that, the intrinsic amorphous silicon film 4 and the n-type amorphous silicon film 5 are etched, leaving the necessary parts.d A source electrode 6 and a drain electrode 7 are patterned with transparent electrodes such as ITO on this, and the pixel electrode 8 is the drain electrode. 7 and formed at the same time (FIG. 3B). Of course, the pixel electrode 8 may be formed separately from the drain electrode 7. After forming the source electrode 6 and drain electrode 7, the n-type amorphous silicon film 5 is partially etched using these electrodes as a mask to form a channel 9, leaving the intrinsic amorphous silicon film 4. A silicon oxide film or a silicon nitride film is formed as a passivation film 10 by plasma CVD (FIG. 3C). Furthermore, a light shielding film 11 is formed of aluminum, molybdenum, etc., and a polyimide type resin or silicon oxide film is formed as a liquid crystal alignment film 12 (FIG. 3D).
［発明が解決しようとする問題点］
上記従来例において、ゲート電極２をＭＯｌＮｉｃｒ、
Ｃｒ、Ｎｉ等の金属材料で形成した場合、これら金属は
後工程のソース電極６、ドレイン電極７、画素電極８を
形成するためのＩＴＯのエツチング液、たとえば塩酸と
塩化鉄系のエツチング液に侵される。ゲート電極２を覆
うゲート絶縁膜のシリコン窒化膜やシリコン酸化膜にピ
ンホールやフラッフがなければ問題がないが、実際には
ピンホールやフラッフが存在し、そこからＩＴＯのエツ
チング液がしみ込み、ゲート電極を侵す。[Problems to be Solved by the Invention] In the above conventional example, the gate electrode 2 is made of MOlNicr,
When formed from metal materials such as Cr and Ni, these metals are eroded by an ITO etching solution, such as a hydrochloric acid and iron chloride based etching solution, for forming the source electrode 6, drain electrode 7, and pixel electrode 8 in the subsequent process. It will be done. There is no problem if there are no pinholes or fluffs in the silicon nitride film or silicon oxide film of the gate insulating film that covers the gate electrode 2, but in reality, pinholes and fluffs exist, and the ITO etching solution seeps through them. Attacks the gate electrode.
ゲート電極材料として、ＩＴＯのエツチング液や強酸に
強いＴａを用いると、ゲートのライン抵抗がＭｏで形成
した場合より２．５〜１０倍も高くなり、寄生容量と併
せてゲートパルスのなまりを生ずる。したがって、アク
ティブマトリックス駆動表示パネル等に応用した場合、
表示品質の低下を生じる。If Ta, which is resistant to ITO etching solution and strong acids, is used as the gate electrode material, the line resistance of the gate will be 2.5 to 10 times higher than when it is made of Mo, which, together with the parasitic capacitance, will cause the gate pulse to become blunt. . Therefore, when applied to active matrix drive display panels, etc.
This results in a decrease in display quality.
こうした欠点を解決するために耐強酸性と抵抗値の両方
を満足させるために、ＭＯなどの金属材の上にエツチン
グ液に強いＴａを被覆することも考えられるが、これだ
とスパッタに手間がかかり、パターニング工程が２度に
なる、などの欠点がある。In order to solve these drawbacks and satisfy both strong acid resistance and resistance value, it is possible to coat a metal material such as MO with Ta, which is resistant to etching liquids, but this would require less time and effort for sputtering. There are drawbacks such as the patterning process being repeated twice.
［問題点を解決するための手段］
この発明はゲート電極材料として耐熱、耐強酸性金属と
耐熱、低抵抗金属とを用いて構成することにより、ゲー
ト特性を損なわずに、エツチング液に侵されないゲート
電極を有する薄膜トランジスタを提供するものである。[Means for Solving the Problems] The present invention uses a heat-resistant, strong acid-resistant metal and a heat-resistant, low-resistance metal as gate electrode materials, so that the gate electrode is not attacked by an etching solution without impairing the gate characteristics. A thin film transistor having a gate electrode is provided.
［実施例］
この発明の実施例が上記従来例に対して特徴を有する点
はゲート電極の構成にある。[Embodiment] The feature of the embodiment of the present invention compared to the above-mentioned conventional example lies in the structure of the gate electrode.
第１図の第１の実施例では基板１の上のゲート電極２は
タンタルによりなる耐熱、耐強酸性金属２ａと、タンタ
ル以外のモリブデンＭ ｏ 、ニッケルクロム合金Ｎ
ｉＣｒ ｓクロムＣｒ、ニッケルＮｉなどの耐熱、低抵
抗金属２ｂとが交互にスパッタにより積層形成されてい
る。この場合、耐強酸性金属２ａの各膜厚は１０ｎｍ以
下、好ましくは３〜５ｎｍ以下にする。１０ｎｍ以上に
するとエツチング液の浸み込みでゲート電極パターンが
侵される。このスパッタにあたっては、同一スパッタ用
ターゲットに２種類の金属材料を配置してもよいし、二
つのターゲットを交互にスパッタしてもよい。基板１に
最初にスパッタされる膜はタンタルの耐熱、耐強酸性金
属２ａが好ましいが他方の低抵抗金属２ｂであってもよ
い。In the first embodiment shown in FIG. 1, a gate electrode 2 on a substrate 1 is made of a heat-resistant, strong acid-resistant metal 2a made of tantalum, molybdenum M o other than tantalum, and a nickel-chromium alloy N.
iCr s Heat-resistant, low-resistance metals 2b such as chromium Cr and nickel Ni are laminated alternately by sputtering. In this case, each film thickness of the strong acid-resistant metal 2a is 10 nm or less, preferably 3 to 5 nm or less. If the thickness is 10 nm or more, the gate electrode pattern will be attacked by the etching solution. In this sputtering, two types of metal materials may be placed on the same sputtering target, or the two targets may be sputtered alternately. The film first sputtered onto the substrate 1 is preferably a heat-resistant, strong acid-resistant metal such as tantalum 2a, but may be the other low-resistance metal 2b.
第２図の第２の実施例では基板１上のゲート電極２はタ
ンタルよりなる耐熱、耐強酸性金属２ａとモリブデンな
どの耐熱、低抵抗金属２ｂとがミックス状態で形成され
ている。スパッタにあたってはタンタルとそれ以外のモ
リブデンなどの金属とを粉末状にしたものをミックスし
た焼結型のものをターゲットにしておこなえばよい。タ
ンタルの含有割合は１〜９９％で可能であるが、通常３
０〜７０％位が用いられる。なお二種類の金属は合金状
態であってもよい。In the second embodiment shown in FIG. 2, the gate electrode 2 on the substrate 1 is formed of a mixture of a heat-resistant, strong acid-resistant metal 2a made of tantalum and a heat-resistant, low-resistance metal 2b such as molybdenum. Sputtering may be performed using a sintered target that is a mixture of powdered tantalum and other metals such as molybdenum. The content ratio of tantalum can be 1 to 99%, but it is usually 3%.
Approximately 0 to 70% is used. Note that the two types of metals may be in an alloy state.
上記第１実施例でタンタルよりなる耐熱、耐強酸性金属
２ａとモリブデンよりなる耐熱、低抵抗金属２ｂを、５
０ｗｔ％ずつの比率で形成したもの、および第２の実施
例でタンタルとモリブデンを５０ｗｔ％ずつの比で合金
化したものの抵抗値はモリブデンだけで形成した場合の
１．５倍程度であり、抵抗値の著しい増加はなかった。In the first embodiment, the heat-resistant, strong acid-resistant metal 2a made of tantalum and the heat-resistant, low-resistance metal 2b made of molybdenum are
The resistance value of the alloy formed with tantalum and molybdenum in a ratio of 0 wt% each and the alloy of tantalum and molybdenum in a ratio of 50 wt% in the second example is about 1.5 times that of the case formed with only molybdenum, and the resistance is There was no significant increase in value.
またこれらを塩酸と塩化鉄系のＩＴＯエツチング液に浸
してＩＴＯのエツチング時間だけ漬けたが、ゲート電極
パターンのサイドエツチングや電極膜のハガレは生じな
かった。また薄膜トランジスタ製造プロセスに入れたと
ころ、ゲートラインの断線が減少しＩＴＯエッチング工
程の影響は認められなかった。Furthermore, when these were immersed in an ITO etching solution containing hydrochloric acid and iron chloride for the ITO etching time, no side etching of the gate electrode pattern or peeling of the electrode film occurred. Furthermore, when it was used in a thin film transistor manufacturing process, the number of disconnections in the gate line was reduced, and no influence of the ITO etching process was observed.
上記実施例では耐熱、耐強酸性金属２ａとしてタンタル
を用いているが、その代りにタンタルとシリコンの合金
Ｔａ５１２にしてもよく、またその中に微量のボロンや
炭素、窒素、酸素等が混入したものであってもよい。In the above embodiment, tantalum is used as the heat-resistant and strong acid-resistant metal 2a, but an alloy of tantalum and silicon, Ta512, may be used instead, and a trace amount of boron, carbon, nitrogen, oxygen, etc. may be mixed therein. It may be something.
さらに耐熱、強酸性金属２ａとしてはタンタルの代りに
モリブデン、タングステン、チタンなどの耐熱、低抵抗
金属のシリサイドを用いてもよい。Further, as the heat-resistant, strongly acidic metal 2a, a silicide of a heat-resistant, low-resistance metal such as molybdenum, tungsten, or titanium may be used instead of tantalum.
また耐熱、耐強酸性金属２ａおよび耐熱、低抵抗金属２
ｂはそれぞれ一種類ずつの材料より構成するものに限ら
ず、二種類以上の材料を用いて積層あるいは合金などに
してもよい。Also heat resistant, strong acid resistant metal 2a and heat resistant, low resistance metal 2
Each b is not limited to being made of one type of material, but may be laminated or alloyed using two or more types of materials.
ゲート電極２の形成方法としては、スパッタ法に限るも
のではなく、蒸着法やＣＶＤ法を用いてもよい。The method for forming the gate electrode 2 is not limited to the sputtering method, and a vapor deposition method or a CVD method may be used.
［発明の効果］
この発明によればゲート電極はゲート特性を損わずに透
明電極膜のエツチング液に対する耐蝕性を有するのでゲ
ートラインの断線の少ない薄膜トランジスタを得ること
ができる。[Effects of the Invention] According to the present invention, since the gate electrode has corrosion resistance to the etching solution of the transparent electrode film without impairing the gate characteristics, it is possible to obtain a thin film transistor with less disconnection of the gate line.
第１図はこの発明の実施例の断面図、第２図は他の実施
例の断面図、第３図（Ａ）〜（Ｄ）は従来例における薄
膜トランジスタの製造工程を追って示す断面図である。
２・・・・ゲート電極
２ａ・・・耐熱、耐強酸性金属
２ｂ・・・耐熱、低抵抗金属。
以 上Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a sectional view of another embodiment, and Figs. 3 (A) to (D) are sectional views sequentially showing the manufacturing process of a thin film transistor in a conventional example. . 2...Gate electrode 2a...Heat resistant, strong acid resistant metal 2b...Heat resistant, low resistance metal. that's all
Claims (5)
抗金属とより構成したことを特徴とする薄膜トランジス
タ。(1) A thin film transistor characterized in that the gate electrode is composed of a heat-resistant, strong acid-resistant metal and a heat-resistant, low-resistance metal.
抗金属とを積層させて構成したことを特徴とする特許請
求の範囲第１項の薄膜トランジスタ。(2) The thin film transistor according to claim 1, wherein the gate electrode is formed by laminating a heat-resistant, strong acid-resistant metal and a heat-resistant, low-resistance metal.
抗金属との混合または合金により構成したことを特徴と
する特許請求の範囲第１項の薄膜トランジスタ。(3) The thin film transistor according to claim 1, wherein the gate electrode is made of a mixture or alloy of a heat-resistant, strong acid-resistant metal and a heat-resistant, low-resistance metal.
求の範囲第１項の薄膜トランジスタ。(4) The thin film transistor according to claim 1, wherein the heat-resistant and strong acid-resistant metal is tantalum.
イドである特許請求の範囲第１項の薄膜トランジスタ。(5) The thin film transistor according to claim 1, wherein the heat-resistant and strong acid-resistant metal is a silicide of a heat-resistant metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62081643A JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62081643A JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63246873A true JPS63246873A (en) | 1988-10-13 |
| JPH0671082B2 JPH0671082B2 (en) | 1994-09-07 |
Family
ID=13752021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62081643A Expired - Fee Related JPH0671082B2 (en) | 1987-04-02 | 1987-04-02 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0671082B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03105325A (en) * | 1989-09-19 | 1991-05-02 | Sharp Corp | Active matrix display device |
| US5070379A (en) * | 1989-06-29 | 1991-12-03 | Oki Electric Industry Co., Ltd. | Thin-film transistor matrix for active matrix display panel with alloy electrodes |
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| US5225364A (en) * | 1989-06-26 | 1993-07-06 | Oki Electric Industry Co., Ltd. | Method of fabricating a thin-film transistor matrix for an active matrix display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60110165A (en) * | 1983-11-21 | 1985-06-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6142962A (en) * | 1984-08-07 | 1986-03-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS62145870A (en) * | 1985-12-20 | 1987-06-29 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS62205656A (en) * | 1986-03-06 | 1987-09-10 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-04-02 JP JP62081643A patent/JPH0671082B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60110165A (en) * | 1983-11-21 | 1985-06-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS6142962A (en) * | 1984-08-07 | 1986-03-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPS62145870A (en) * | 1985-12-20 | 1987-06-29 | Matsushita Electric Ind Co Ltd | Thin film transistor |
| JPS62205656A (en) * | 1986-03-06 | 1987-09-10 | Toshiba Corp | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5225364A (en) * | 1989-06-26 | 1993-07-06 | Oki Electric Industry Co., Ltd. | Method of fabricating a thin-film transistor matrix for an active matrix display panel |
| US5070379A (en) * | 1989-06-29 | 1991-12-03 | Oki Electric Industry Co., Ltd. | Thin-film transistor matrix for active matrix display panel with alloy electrodes |
| JPH03105325A (en) * | 1989-09-19 | 1991-05-02 | Sharp Corp | Active matrix display device |
| WO1992006504A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Thin film transistor having an improved gate structure and gate coverage by the gate dielectric |
| WO1992006490A1 (en) * | 1990-10-05 | 1992-04-16 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
| GB2253742A (en) * | 1990-10-05 | 1992-09-16 | Gen Electric | Device self-alignment by propagation of a reference structure's topography |
| US5340758A (en) * | 1990-10-05 | 1994-08-23 | General Electric Company | Device self-alignment by propagation of a reference structure's topography |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0671082B2 (en) | 1994-09-07 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |