CN107346071A - A kind of new tft array substrate, display panel and terminal device - Google Patents
A kind of new tft array substrate, display panel and terminal device Download PDFInfo
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- CN107346071A CN107346071A CN201710798921.0A CN201710798921A CN107346071A CN 107346071 A CN107346071 A CN 107346071A CN 201710798921 A CN201710798921 A CN 201710798921A CN 107346071 A CN107346071 A CN 107346071A
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- 239000011521 glass Substances 0.000 claims abstract description 108
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- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 16
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- 229910052802 copper Inorganic materials 0.000 claims description 2
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
This application discloses a kind of new tft array substrate, display panel and terminal device, the new tft array substrate includes glass substrate, sets gradually gate routing layers, multi-strip scanning line and a plurality of data lines on the glass substrate, wherein, scan line insulate arranged in a crossed manner with data wire, glass substrate is provided with gate drivers close to the periphery of data thread end, the end set of scan line has via, and metal routing one end connection gate drivers, the other end for being laid in gate routing layers connect scan line through via.The application sets up one layer of gate routing layer on the glass substrate, originally the gate drivers close to scanning thread end are moved to close to the position of data thread end, via the metal routing connection scan line and gate drivers being laid on gate routing layers, so as to save glass substrate close to the metal routing space of scanning thread end, width of the liquid crystal panel close to the BM regions of scanning thread end is reduced.
Description
Technical field
The present invention relates to liquid crystal display panel technology field, more particularly to a kind of new tft array substrate, display panel and end
End equipment.
Background technology
With the development of the social economy, in electronic equipment widely apply liquid crystal display (Liquid Crystal Display,
LCD) panel, LCD are broadly divided into STN according to different material and manufacturing technology and (Super Twisted Nematic, surpassed
Twisted-nematic)-LCD, TFT (Thin Film Transistor, thin film transistor (TFT))-LCD, LTPS (Low
Temperature Polycrystalline Silicon, low temperature polycrystalline silicon) TFT-LCD panels etc., wherein, TFT-LCD panels
There is small volume, in light weight, Low emissivity line, low power consumption, true color, be widely used on kinds of displays material.
Tft array substrate is one of important component of TFT-LCD panels, for providing drive circuit to LCD.Fig. 1
For the structural representation of tft array substrate.As shown in figure 1, tft array substrate includes glass substrate 1, is arranged on glass substrate 1
On multi-strip scanning line 2, a plurality of data lines 3 intersected that insulate with scan line 2, be arranged on two adjacent scan lines 2 and adjacent
Two data lines 3 surround the pixel electrode 5 and TFT switch 4 in region.Fig. 2 is A-A ' in tft array substrate shown in Fig. 1
Sectional view.As shown in Fig. 2 TFT switch 4 includes the grid 401, source electrode 402 and drain electrode 403 being successively set on glass substrate 1
And passivation layer 404, source electrode 402 are located at same layer with drain electrode 403, grid 401 is connected with scan line 2, source electrode 402 and data wire
3 connections, drain electrode 403 are connected with pixel electrode 5.Scan line 2 is by the metal routing on glass substrate 1 and is located at glass substrate 1
The gate drivers (Gate Driver) 6 of periphery connect, and data wire 3 is by the metal routing on glass substrate 1 and is located at glass
The source electrode driver (Source Driver) 7 of the periphery of substrate 1 connects, and gate drivers 6 are that scan line 2 sends scanning signal, are swept
Retouching after line 2 receives scanning signal controls the TFT switch 4 of corresponding line to enter conducting state, while source electrode driver 7 sends data letter
Number it is added to by data wire 3 on the source electrode 402 of TFT switch 4 to data wire 3, data-signal, the TFT that data-signal passes through conducting
Switch 4 reaches the drain electrode 403 of TFT switch 4, and electric field is formed on pixel electrode 5, and pixel electrode 5 applies voltage, control to liquid crystal cell
The rotation direction of liquid crystal molecule processed, so as to change the light path of transmitted light, realize the control to image.
But the metal routing of connection scan line and gate drivers forms cabling arranged side by side in glass substrate both sides, then add
Top glass substrate edge needs the signal lead related to gate drivers, causes glass substrate close to the gold at scan line both ends
It is larger to belong to cabling space.And in order to block metal routing space, it is necessary to increase black matrix" (Black Matrix, BM) region
Width, so as to cause glass substrate wider close to the BM regions at scan line both ends, cause the black surround in display picture wider.
The content of the invention
The invention provides a kind of new tft array substrate, display panel and terminal device, to solve current TFT-LCD
On panel close to scan line both ends metal routing space it is larger, cause in LCD close to scan line both ends BM regions compared with
The problem of wide.
In a first aspect, the embodiments of the invention provide a kind of new tft array substrate, including glass substrate, set gradually
Gate routing layers, multi-strip scanning line and a plurality of data lines on the glass substrate, wherein,
The scan line insulate arranged in a crossed manner with data wire；
The periphery of the glass substrate is provided with gate drivers, and the gate drivers are positioned close to the data wire
The position of end；
The end set of the scan line has via, the metal routing one end connection institute being laid on the gate routing layers
State gate drivers, the other end connects the scan line through the via.
Second aspect, the embodiments of the invention provide a kind of display panel, including tft array substrate, the coloured silk being oppositely arranged
Ilm substrate and the liquid crystal layer being arranged between the tft array substrate and color membrane substrates, the tft array substrate are described above
New tft array substrate.
The third aspect, the embodiments of the invention provide a kind of terminal device, including display panel described above.
Technical scheme provided by the invention can include the following benefits：
New tft array substrate provided by the invention is walked including glass substrate, the gate set gradually on the glass substrate
Line layer, multi-strip scanning line and a plurality of data lines, wherein, scan line insulate arranged in a crossed manner with data wire；The periphery of glass substrate
Gate drivers are provided with, gate drivers are positioned close to the position of data thread end；The end set of scan line has via,
Metal routing one end connection gate drivers, the other end being laid on gate routing layers connect scan line through via.This Shen
One layer of gate routing layer is please set up on the glass substrate, and the gate drivers originally close to scanning thread end are moved to close to number
According to the position of thread end, scan line and gate drivers are connected respectively via the metal routing being laid on gate routing layers, can
To cancel arranged side by side metal routing of the glass substrate close to scanning thread end, gold of the glass substrate close to scanning thread end can be saved
Belong to cabling space, and then width of the liquid crystal display panel close to black matrix" (BM) region of scanning thread end can be reduced, it is real
The extremely narrow side of existing liquid crystal display panel, advantageously supports narrow frame product programming.
It should be appreciated that the general description and following detailed description of the above are only exemplary and explanatory, not
Can the limitation present invention.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, letter will be made to the required accompanying drawing used in embodiment below
Singly introduce, it should be apparent that, for those of ordinary skills, without having to pay creative labor,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of structural representation for tft array substrate that prior art provides；
Fig. 2 is along A-A ' cross-sectional view in a kind of tft array substrate that prior art provides；
Fig. 3 is a kind of structural representation of new tft array substrate provided in an embodiment of the present invention；
Fig. 4 is along B-B ' cross-sectional view in a kind of new tft array substrate provided in an embodiment of the present invention；
Fig. 5 is the knot for the metal routing that scan line is connected in a kind of new tft array substrate provided in an embodiment of the present invention
Structure schematic diagram；
Fig. 6 is a kind of structural representation of display panel provided in an embodiment of the present invention；
Fig. 1-Fig. 6 symbols represent：1- glass substrates, 2- scan lines, 21- vias, 3- data wires, 4-TFT switches, 401- grid
Pole, 402- source electrodes, 403- drain electrodes, 404- passivation layers, 405- contact holes, 5- pixel electrodes, 6- gate drivers, 7- source drives
Device, 8-gate routing layers, 9- insulating barriers, 10- color membrane substrates, 11- black matrix"s.
Embodiment
Tft array substrate is one of important component of TFT-LCD panels, for providing drive circuit to LCD.TFT
The periphery of glass substrate sets gate drivers and source electrode driver respectively in array base palte, and gate drivers are close to scan line
End and scan line is connected by metal routing on glass substrate, source electrode driver is close to the end of data wire and passes through glass
Metal routing connection data wire on substrate.The embodiment of the present application is so that scan line is horizontally disposed, data wire is vertically arranged as an example.
But the metal routing of connection scan line and gate drivers forms cabling arranged side by side at left and right sides of glass substrate,
Along with glass substrate edge has the signal lead related to gate drivers, cause the metal routing of glass substrate left and right sides
Space is larger.And in order to block metal routing space, the width in black matrix" BM regions can only be increased, so as to cause glass substrate
The BM regions of left and right sides are wider, and it is wider to show as black surround in display picture.To solve this problem, the embodiments of the invention provide
A kind of new tft array substrate, gate drivers are moved to glass by the left and right sides of glass substrate (close to scanning thread end)
The position of substrate upper and lower sides (close to data thread end), the metal routing for eliminating glass substrate left and right sides connection scan line are empty
Between, so as to reduce the width in glass substrate left and right sides BM regions.
Referring to Fig. 3, Fig. 4, Fig. 3 is a kind of structural representation of tft array substrate provided in an embodiment of the present invention, and Fig. 4 is
Sectional views of the Fig. 3 along B-B '.
As shown in Figure 3, Figure 4, tft array substrate provided in an embodiment of the present invention includes glass substrate 1, is successively set on glass
Gate routing layers 8, multi-strip scanning line 2 and a plurality of data lines 3 on glass substrate 1, wherein,
Scan line 2 insulate arranged in a crossed manner with data wire 3.In specific implementation process, scan line 2 is arranged on gate routing layers
On 8, data wire 3 is located at the top of scan line 2, and insulating barrier is provided between scan line 2 and data wire 3 so that scan line 2 and number
Intersect according to being insulated between line 3, avoid the signal between scan line 2 and data wire 3 from interfering.
In specific implementation process, the TFT switch 4 of tft array substrate is close to scan line 2 and the infall of data wire 3, phase
Pixel electrode 5 is provided with the region surrounded between adjacent two scan lines 2 and adjacent two data line 3.The grid of TFT switch 4
401 are also disposed on gate routing layers 8, and it is located at same layer with scan line 2, and the drain electrode of source electrode 402/ 403 of TFT switch 4 is located at
The top of gate routing layers 8.Source electrode 402 forms conducting channel with drain electrode 403, and the drain electrode of source electrode 402/ 403 is located at data wire 3
Same layer.The top of the drain electrode of source electrode 402/ 403 sets passivation layer 404, for protecting TFT switch 4.Passivation layer 404 is close to pixel
One end of electrode 5 is provided with contact hole 405, and pixel electrode 5 connects drain electrode 403 through contact hole 405.
In specific implementation process, scan line 2 receives the TFT switch 4 of opening corresponding line after scanning signal, and TFT switch 4 is led
Logical, i.e., the source electrode 402 of TFT switch 4 turns on drain electrode 403.Meanwhile after data wire 3 receives data-signal, apply voltages to TFT
On the source electrode 402 of switch 4, because TFT switch 4 turns on, the voltage on source electrode 402 is added in the drain electrode 403 of TFT switch 4, is leaked afterwards
Voltage on pole 403 is added on pixel electrode 5, and electric field is formed on pixel electrode 5, and pixel electrode 5 is liquid crystal cell application electricity
Pressure, controls the rotation direction of liquid crystal molecule, so as to change the light path of transmitted light, realizes the control to image to be displayed.
To send scanning signal to scan line 2, the periphery of glass substrate 1 is provided with gate drivers 6, gate drivers 6
It is positioned close to the position of the end of data wire 3.Gate drivers 6 connect scan line 2 by metal routing, so as to scan line 2
Scanning signal is provided.
In specific implementation process, the end set of scan line 2 has via 21, the metal being laid on gate routing layers 8
Cabling one end connection gate drivers 6, the other end connect scan line 2 through via 21.Metal routing is laid in gate routing layers 8
On, the outside that metal routing is dispersed in glass substrate 1 is avoided, reduces the metal routing space in the outside of glass substrate 1.
In a kind of application scenarios, tft array substrate provides drive circuit using dual-driving-mode to LCD, wherein,
Gate drivers 6 are located at the periphery of the opposite sides of glass substrate 1 respectively, i.e. the both ends of scan line 2 connect 1 liang of glass substrate respectively
The gate drivers 6 of side.In specific implementation process, the periphery of glass substrate 1 is respectively arranged with first grid driver and second
Gate drivers, first grid driver are separately positioned on close to the position at the both ends of data wire 3 with second grid driver；Scanning
The both ends of line 2 are respectively arranged with the first via and the second via, and first metal routing one end being laid on gate routing layers 8 connects
First grid driver, the other end are connect through the first via connection scan line 2, the second metal being laid on gate routing layers 8
Cabling one end connection second grid driver, the other end connect scan line 2 through the second via.
In other words, the right-hand member of scan line 2 sets the first via, left end to set the second via, and the upside of glass substrate 1 is set
First grid driver, downside set second grid driver, and first metal routing one end being laid on gate routing layers 8 connects
First grid driver, the other end are connect through the first via connection scan line 2, the second metal being laid on gate routing layers 8
Cabling one end connection second grid driver, the other end connect scan line 2 through the second via.Or the left end of scan line 2 is set
First via, right-hand member set the second via, and the upside of glass substrate 1 sets first grid driver, downside to set second grid
Driver, first metal routing one end connection first grid driver, the other end being laid on gate routing layers 8 pass through first
Via connects scan line 2, is laid in second metal routing one end connection second grid driver on gate routing layers 8, another
End connects scan line 2 through the second via.
In another application scenarios, tft array substrate provides drive circuit using dual-driving-mode to LCD, its
In, gate drivers 6 are located at the periphery of the side of glass substrate 1, i.e. scan line 2 connects the grid drive of the side of glass substrate 1 respectively
Dynamic device 6.In specific implementation process, the periphery of glass substrate 1 is provided with gate drivers 6, and gate drivers 6 are positioned close to count
According to the position of the one end of line 3；The both ends of scan line 2 are respectively arranged with the 3rd via and the 4th via, are laid on gate routing layers 8
The 3rd metal routing one end connection gate drivers 6, the other end through the 3rd via connection scan line 2, be laid in gate and walk
The 4th metal routing one end connection gate drivers 6, the other end on line layer 8 connect scan line 2 through the 4th via.
In other words, gate drivers 6 are arranged on the position of the upside of glass substrate 1, and the left and right ends of scan line 2 are set respectively
Via is equipped with, the 3rd metal routing one end connection gate drivers 6, the other end being laid on gate routing layers 8 pass through scanning
The via connection scan line 2 of 2 left ends of line/right-hand member, the 4th metal routing one end connection grid being laid on gate routing layers 8 drive
Dynamic device 6, the other end connect scan line 2 through scan line right-hand member/left end via.Or gate drivers 6 are arranged on glass substrate 1
The position of downside, the left and right ends of scan line 2 are respectively arranged with via, the 3rd metal routing being laid on gate routing layers 8
One end connection gate drivers 6, the other end are laid in gate and walked through the via connection scan line 2 of 2 left ends of scan line/right-hand member
The 4th metal routing one end connection gate drivers 6, the other end on line layer 8 are swept through scan line right-hand member/left end via connection
Retouch line 2.
The first metal routing, the second metal routing, the 3rd metal routing and the 4th metal being laid on gate routing layers
Cabling is not an only metal routing, and it represents all metal routings of connection scan line and gate drivers, scan line
Bar number it is more, the quantity of metal routing is more.
In another application scenarios, tft array substrate provides drive circuit using single type of drive to LCD, its
In, gate drivers 6 are located at the periphery of the side of glass substrate 1, with source electrode driver 7 be located at glass substrate 1 the same side or
Positioned at the not homonymy of glass substrate 1.In specific implementation process, the periphery of glass substrate 1 is provided with gate drivers 6, and grid drives
Dynamic device 6 is positioned close to the position of the one end of data wire 3, and gate drivers 6 are located at the same of glass substrate 1 with source electrode driver 7
Side；One end of scan line 2 is provided with via 21, the metal routing one end connection gate drivers being laid on gate routing layers 8
6th, the other end connects scan line 2 through via 21.
In other words, gate drivers 6 are arranged on the position of the upside of glass substrate 1, the gold being laid on gate routing layers 8
Belong to cabling one end connection gate drivers 6, the other end passes through the via 21 of the left end of scan line 2 to connect scan line 2, or grid drive
Dynamic device 6 is arranged on the position of the upside of glass substrate 1, the metal routing one end connection raster data model being laid on gate routing layers 8
Device 6, the via 21 of the other end through the right-hand member of scan line 2 connect scan line 2, or gate drivers 6 are arranged under glass substrate 1
The position of side, metal routing one end connection gate drivers 6, the other end being laid on gate routing layers 8 are left through scan line 2
The via connection scan line 2 at end, or gate drivers 6 are arranged on the position of the downside of glass substrate 1, are laid in gate routing layers
Metal routing one end connection gate drivers 6, the via 21 of the other end through the right-hand member of scan line 2 on 8 connect scan line 2.
In specific implementation process, it is located at the right side of glass substrate 1 respectively with the metal electrode of scan line 2 and data wire 3
Exemplified by downside.As shown in figure 5, metal electrode G1, G2, G3 of scan line 2 are located at the right side of glass substrate 1, the gold of data wire 3
Category electrode S1, S2 are located at the downside of glass substrate 1, and the metal routing being laid on gate routing layers 8 respectively will through via 21
Metal electrode G1, G2, G3 of scan line 2 move to the downside of glass substrate 1, form new metal electrode G1 ', G2 ', G3 ', afterwards
Metal routing connects metal electrode G1 ', G2 ', G3 ' and gate drivers 6 respectively, realizes the company of scan line 2 and gate drivers 6
Connect.Meanwhile the metal electrode of scan line 2 is moved to the downside of glass substrate 1 by gate routing layers 8 so that scan line 2
The metal electrode of metal electrode and data wire 3 is located at the same side of glass substrate 1, is connected so as to save the right side of glass substrate 1
The metal routing space of scan line 2, the width in the right side BM regions of glass substrate 1 is reduced, realize extremely narrow side panel construction and set
Meter.
In specific implementation process, because by the gate drivers of the left and right sides of script glass substrate 1 (close to the both ends of scan line 2)
6 move to the position of the upper and lower sides of glass substrate 1, then eliminate the metal routing arranged side by side of the left and right sides of glass substrate 1 connection scan line 2,
Signal lead simultaneously related to gate drivers 6 also moves to the upper and lower sides of glass substrate 1 by the left and right sides of glass substrate 1 so that glass
The metal routing space of the left and right sides of glass substrate 1 greatly reduces the even left and right sides of glass substrate 1 and metal routing space no longer be present, enters
And the width in the left and right sides BM regions of glass substrate 1 is greatly reduced, or even BM regions are not present in the left and right sides of glass substrate 1, it is real
The extremely narrow side of LCD left and right sides is showed.
Scan line 2 connects the raster data model of the upper and lower sides of glass substrate 1 by the metal routing being laid on gate routing layers 8
Device 6, gate drivers 6 can be located at the same side of glass substrate 1 with the source electrode driver 7 of the upper and lower sides of glass substrate 1, can also
Positioned at the not homonymy of glass substrate 1.Blocking the metal routing of connection source electrode driver 7 in the BM regions of the upper and lower sides of glass substrate 1
While space, the metal routing space of connection gate drivers 6 can also be blocked, therefore is not required to increase glass substrate about 1
The width in side BM regions, the width in the BM regions of the upper and lower sides of glass substrate 1 are constant.
In specific implementation process, the size of gate routing layers 8 and the size one of the place metal level of scan line 2
Cause, i.e. the consistency of thickness of the thickness of gate routing layers 8 and scan line 2, its length and width size also with the place metal level of scan line 2
Size is consistent.Gate routing layers 8 are consistent with the processing technology of scan line 2, can simplify processing technology.Preferably, gate cablings
Layer 8 is metal level, and its material is aluminium or copper.
It should be insulated between gate routing layers 8 and scan line 2 and grid 401, in case gate routing layers 8 influence scan line
2 with the performance of grid 401.In specific implementation process, the side plating last layer insulation of gate routing layers 8 towards scan line 2 is thin
Film, i.e., using gate routing layers 8 as substrate, using PECVD (Plasma Enhanced Chemical Vapor
Deposition, the vapour deposition process of plasma enhanced chemical) mode deposits insulation film on substrate.Preferably, originally
The insulation film for applying using is silicon nitride film.
Silicon nitride film has the characteristics that high-k, high insulation resistance, electric leakage are low and anti-oxidant, in microelectronic material
And in device production, generally used as passivating film, dielectric film and diffusion mask.
In specific implementation process, insulating barrier 9 can be also set between gate routing layers 8 and scan line 2, insulating barrier 9
Material uses silicon nitride.Using gate routing layers 8 as substrate, insulating barrier 9 is deposited on substrate by the way of PECVD, should
The thickness of insulating barrier 9 and the consistency of thickness of gate routing layers 8.
When insulating barrier 9 is set between gate routing layers 8 and scan line 2, via is also equipped with insulating barrier 9, the via
Corresponding with the via 21 of the end of scan line 2, that is, the metal routing being laid on gate routing layers 8 is sequentially passed through on insulating barrier 9
Via be connected scan line 2 with the via 21 of the end of scan line 2.
The new tft array substrate processing technology that the application provides is array processes, similar to semiconductor technology, array work
Skill is to make the process of the patterns such as TFT devices, pixel regularly on the glass substrate.Array processes include cleaning technology, CVD
(Chemical Vapor Deposition, chemical vapor deposition) film technique, Sputter (sputter) film technique, photoresist
It is thin finally to form 4-5 layers with lift-off technology, exposure technique, wet etching techniques, dry etching technology etc. on the glass substrate for coating, development
Film figure.
It is per layer film patterning process：It is first that cleaning glass substrate is clean, then film forming (metal Sputter
Mode, nonmetallic CVD modes), PR (Photoresist, photoresist) is then coated with after film forming on glass substrate, and use MASK
(photomask) is exposed, and the pattern of needs is transferred on PR from MASK, and part photosensitive in PR is washed away by development, is left
PR be exactly required pattern, then perform etching technique (common metal wet etching, nonmetallic use dry etching), remove no PR guarantors
The film of shield, what is left is exactly required Thinfilm pattern, and finally PR is peeled off to form final TFT device patterns.
Existing array processes are divided into 4 layers of MASK techniques and 5 layers of MASK techniques, and the embodiment of the present application is with 5 layers of MASK techniques
Exemplified by.5 layers of MASK techniques of tft array substrate are divided into G engineerings, I engineerings, D engineerings, C engineerings and PI engineerings according to sequencing,
Wherein, G engineerings form scan line pattern, and I engineerings form TFT channel silicon island pattern, and D engineerings form data line pattern, C engineerings
Contact hole pattern is formed, PI engineerings form pixel electrode.Often form thin film pattern, it is necessary to one layer of MASK, ultimately form
TFT metal electrodes and pixel electrode.
The new tft array substrate that the embodiment of the present application provides before array processes G engineerings by forming independent one layer of gold
Belong to layer, referred to as PRE-G engineerings, i.e., before G engineerings form scan line, form one layer of gate routing layer on the glass substrate,
Or gate routing layers and insulating barrier are sequentially formed on the glass substrate, carried out successively on gate routing layers or insulating barrier afterwards
G engineerings, I engineerings, D engineerings, C engineerings and PI engineerings, ultimately form new tft array substrate.
Referring to Fig. 6, for the structural representation of display panel provided in an embodiment of the present invention.
As shown in fig. 6, display panel provided in an embodiment of the present invention includes tft array substrate, the color film base being oppositely arranged
Plate 10 and the liquid crystal layer being arranged between tft array substrate and color membrane substrates 10, wherein, tft array substrate is any of the above-described
The new tft array substrate that technical scheme provides.
In specific implementation process, color membrane substrates 10 are provided with black matrix" 11, black square towards the side of tft array substrate
Battle array 11 blocks scan line 2, data wire 3 and the metal routing for connecting gate drivers 6 on tft array substrate.Liquid crystal panel
Each pixel controls activity by thin film transistor (TFT) (TFT), and these thin film transistor (TFT)s control these " to open equivalent to " switch "
Close " circuit is needed, therefore, it is necessary on the side of LCD screen using gate line arrangement design, the resolution ratio of screen is higher, pixel
It is more, control the gate line of these pixels also more, therefore, it is necessary to very roomy frame after screen resolution is high
To place gate line.And the black matrix" 11 on color membrane substrates 10 is used to the metal routing space for blocking the outside of glass substrate 1, carry
The aesthetic property of high display panel.
Black matrix" 11 also has except the metal routing space for blocking the outside of glass substrate 1, its effect：First, prevent
Light leak, prevent display panel internal backlight plate light from being spilt from LCD display edge, if BM areas are narrow, gently then in black
Screen edge has a light leakage phenomena during picture, heavy then obvious halation occurs；Second, liquid crystal is poured in display panel interlayer
When in order to prevent its leakage, to carry out frame sealing, BM areas are used to block this circle colloid.
The embodiment of the present invention additionally provides a kind of terminal device, including the display panel described in above-mentioned technical proposal, and this is aobvious
Showing the BM areas of panel left and right sides can accomplish within 2mm and (include 2mm), realize the extremely narrow side of display panel, advantageously support
Narrow frame product programming.
New tft array substrate provided in an embodiment of the present invention includes glass substrate, set gradually on the glass substrate
Gate routing layers, multi-strip scanning line and a plurality of data lines, wherein, scan line and arranged in a crossed manner, the glass substrate of data wire insulation
Periphery be provided with gate drivers, gate drivers are positioned close to the position of data thread end, the end set of scan line
There is via, metal routing one end connection gate drivers, the other end being laid on gate routing layers scan through via connection
Line.The application sets up one layer of gate routing layer on the glass substrate, and the gate drivers originally close to scanning thread end are moved
To close to the position of data thread end, scan line and raster data model are connected by the metal routing being laid on gate routing layers
Device, the metal routing arranged side by side of connection scan line at left and right sides of script glass substrate is eliminated, is reduced at left and right sides of glass substrate
Row driving metal routing space, so as to reduce the width in BM regions at left and right sides of glass substrate, realizes liquid crystal display panel
Extremely narrow side, advantageously support narrow frame product programming.
It should be noted that herein, such as relation art of " first ", " second ", " the 3rd " and " the 4th " or the like
Language is used merely to make a distinction an entity or operation with another entity or operation, and not necessarily requires or imply this
Any this actual relation or order be present between a little entities or operation.
Those skilled in the art will readily occur to the present invention its after considering specification and putting into practice the disclosure invented here
Its embodiment.The application be intended to the present invention any modification, purposes or adaptations, these modifications, purposes or
Person's adaptations follow the general principle of the present invention and including undocumented common knowledges in the art of the invention
Or conventional techniques.Description and embodiments are considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
Invention described above embodiment is not intended to limit the scope of the present invention..
Claims (10)
1. a kind of new tft array substrate, it is characterised in that including glass substrate, be successively set on the glass substrate
Gate routing layers, multi-strip scanning line and a plurality of data lines, wherein,
The scan line insulate arranged in a crossed manner with data wire；
The periphery of the glass substrate is provided with gate drivers, and the gate drivers are positioned close to the data thread end
Position；
The end set of the scan line has via, and the metal routing one end being laid on the gate routing layers connects the grid
Driver, the other end connect the scan line through the via.
2. new tft array substrate as claimed in claim 1, it is characterised in that the periphery of the glass substrate is set respectively
There are first grid driver and second grid driver, the first grid driver is separately positioned on second grid driver
Close to the position at the data wire both ends；
The both ends of the scan line are respectively arranged with the first via and the second via, first be laid on the gate routing layers
Metal routing one end connects the first grid driver, the other end connects the scan line through first via, lays
Second metal routing one end on the gate routing layers connects the second grid driver, the other end passes through described second
Via connects the scan line.
3. new tft array substrate as claimed in claim 1, it is characterised in that the periphery of the glass substrate is provided with grid
Driver, the gate drivers are positioned close to the position of described data wire one end；
The both ends of the scan line are respectively arranged with the 3rd via and the 4th via, the 3rd be laid on the gate routing layers
Metal routing one end connects the gate drivers, the other end connects the scan line through the 3rd via, is laid in institute
The 4th metal routing one end connection gate drivers, the other end stated on gate routing layers connect through the 4th via
The scan line.
4. new tft array substrate as claimed in claim 1, it is characterised in that the periphery of the glass substrate is provided with grid
Driver, the gate drivers are positioned close to the position of described data wire one end；
One end of the scan line is provided with via, and the metal routing one end being laid on the gate routing layers connects the grid
Driver, the other end connect the scan line through the via.
5. the new tft array substrate as described in any one of claim 1, it is characterised in that the size of the gate routing layers
Size is consistent with the size of metal level where the scan line.
6. new tft array substrate as claimed in claim 5, it is characterised in that the gate routing layers are metal level, described
The material of metal level is aluminium or copper.
7. new tft array substrate as claimed in claim 1, it is characterised in that the gate routing layers and the scan line
Between be provided with insulating barrier, the insulating barrier is silicon nitride dielectric layer.
A kind of 8. display panel, it is characterised in that including be oppositely arranged tft array substrate, color membrane substrates and be arranged at described
Liquid crystal layer between tft array substrate and color membrane substrates, the tft array substrate are new described in claim any one of 1-7
Type tft array substrate.
9. display panel as claimed in claim 8, it is characterised in that the color membrane substrates are towards the tft array substrate
Side is provided with black matrix", and the black matrix" blocks scan line, data wire and connection grid on the tft array substrate
The metal routing of driver.
10. a kind of terminal device, it is characterised in that including the display panel as described in claim any one of 8-9.
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| CN201710798921.0A CN107346071A (en) | 2017-09-07 | 2017-09-07 | A kind of new tft array substrate, display panel and terminal device |
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| CN201710798921.0A CN107346071A (en) | 2017-09-07 | 2017-09-07 | A kind of new tft array substrate, display panel and terminal device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107911507A (en) * | 2017-11-22 | 2018-04-13 | 广东欧珀移动通信有限公司 | Display screen component and electronic equipment |
| CN108957891A (en) * | 2018-08-21 | 2018-12-07 | 信利半导体有限公司 | A kind of array substrate |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1897094A (en) * | 2005-07-11 | 2007-01-17 | 中华映管股份有限公司 | Liquid-crystal display panel and its inspection |
| CN102081246A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN102103293A (en) * | 2009-12-18 | 2011-06-22 | 胜华科技股份有限公司 | Display panel with narrow frame and electronic device using display panel |
| CN104035257A (en) * | 2014-06-26 | 2014-09-10 | 南京中电熊猫液晶显示科技有限公司 | Pixel array and manufacturing method thereof and display panel |
| CN104756177A (en) * | 2012-10-30 | 2015-07-01 | 夏普株式会社 | Active matrix substrate, display panel and display device provided with same |
| CN105093757A (en) * | 2015-09-02 | 2015-11-25 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN205750222U (en) * | 2016-05-13 | 2016-11-30 | 京东方科技集团股份有限公司 | Display device and driving means |
| CN106932981A (en) * | 2012-01-12 | 2017-07-07 | 精工爱普生株式会社 | Liquid-crystal apparatus and electronic equipment |
| CN107077033A (en) * | 2014-10-01 | 2017-08-18 | 苹果公司 | Display with vertical gate line extension and minimum frame |
-
2017
- 2017-09-07 CN CN201710798921.0A patent/CN107346071A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1897094A (en) * | 2005-07-11 | 2007-01-17 | 中华映管股份有限公司 | Liquid-crystal display panel and its inspection |
| CN102081246A (en) * | 2009-12-01 | 2011-06-01 | 群康科技(深圳)有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN102103293A (en) * | 2009-12-18 | 2011-06-22 | 胜华科技股份有限公司 | Display panel with narrow frame and electronic device using display panel |
| CN106932981A (en) * | 2012-01-12 | 2017-07-07 | 精工爱普生株式会社 | Liquid-crystal apparatus and electronic equipment |
| CN104756177A (en) * | 2012-10-30 | 2015-07-01 | 夏普株式会社 | Active matrix substrate, display panel and display device provided with same |
| CN104035257A (en) * | 2014-06-26 | 2014-09-10 | 南京中电熊猫液晶显示科技有限公司 | Pixel array and manufacturing method thereof and display panel |
| CN107077033A (en) * | 2014-10-01 | 2017-08-18 | 苹果公司 | Display with vertical gate line extension and minimum frame |
| CN105093757A (en) * | 2015-09-02 | 2015-11-25 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN205750222U (en) * | 2016-05-13 | 2016-11-30 | 京东方科技集团股份有限公司 | Display device and driving means |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107911507A (en) * | 2017-11-22 | 2018-04-13 | 广东欧珀移动通信有限公司 | Display screen component and electronic equipment |
| CN108957891A (en) * | 2018-08-21 | 2018-12-07 | 信利半导体有限公司 | A kind of array substrate |
| CN108957891B (en) * | 2018-08-21 | 2024-05-07 | 信利半导体有限公司 | Array substrate |
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Address after: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Applicant after: Hisense Visual Technology Co., Ltd. Address before: 266555 Qingdao economic and Technological Development Zone, Shandong, Hong Kong Road, No. 218 Applicant before: QINGDAO HISENSE ELECTRONICS Co.,Ltd. |
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Application publication date: 20171114 |