KR100328847B1 - Manufacturing Method of Thin Film Transistor - Google Patents
Manufacturing Method of Thin Film Transistor Download PDFInfo
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- KR100328847B1 KR100328847B1 KR1019980024340A KR19980024340A KR100328847B1 KR 100328847 B1 KR100328847 B1 KR 100328847B1 KR 1019980024340 A KR1019980024340 A KR 1019980024340A KR 19980024340 A KR19980024340 A KR 19980024340A KR 100328847 B1 KR100328847 B1 KR 100328847B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000010409 thin film Substances 0.000 title abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- 238000009832 plasma treatment Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000010408 film Substances 0.000 abstract description 9
- 239000011521 glass Substances 0.000 description 5
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- -1 B 2 H 6 Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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Abstract
본 발명은 오믹 접촉층의 저항을 감소시킬 수 있는 박막 트랜지스터의 제조방법에 관한 것으로, 본 발명의 막막 트랜지스터의 제조방법은, 상부면에 게이트 전극이 형성되고, 상기 게이트 전극이 덮혀지도록 상부면 전면에 게이트 절연막이 도포된 기판을 제공하는 단계; 상기 게이트 절연막 상에 반도체층을 형성하기 제1비정질실리콘층과 에치 스톱퍼를 형성하기 위한 금속층을 순차적으로 형성하는 단계; 상기 금속층을 식각하여 게이트 전극 상부의 제1비정질실리콘층 부분 상에 에치 스톱퍼를 형성하는 단계; 상기 에치 스톱퍼 양측의 노출된 제1비정질실리콘층 표면을 소정 가스로 플라즈마 처리한 후, 상기 플라즈마 처리된 제1비정질실리콘층 표면에 플라즈마 방식으로 불순물을 도핑하는 단계: 전체 상부에 오믹 접촉층을 형성하기 위한 제2비정질실리콘층을 형성하는 단계; 상기 제2비정질실리콘층을 소정 가스로 플라즈마 처리한 후, 상기 플라즈마 처리된 제2비정질실리콘층에 플라즈마 방식으로 불순물을 도핑하는 단계; 상기 게이트 절연막이 노출되도록 상기 제2 및 제1비정질실리콘층을 식각하여 오믹 접촉층 및 반도체층을 형성하는 단계; 및 상기 오믹 접촉층 상에 소오스/드레인 전극을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of manufacturing a thin film transistor capable of reducing the resistance of an ohmic contact layer. In the method of manufacturing a film transistor of the present invention, a gate electrode is formed on an upper surface, and an entire upper surface of the upper surface of the gate electrode is covered. Providing a substrate having a gate insulating film coated thereon; Sequentially forming a first amorphous silicon layer for forming a semiconductor layer and a metal layer for forming an etch stopper on the gate insulating film; Etching the metal layer to form an etch stopper on a portion of the first amorphous silicon layer on the gate electrode; Plasma-treating the exposed first amorphous silicon layer surfaces on both sides of the etch stopper with a predetermined gas, and then doping impurities on the plasma-treated first amorphous silicon layer surface in a plasma manner: forming an ohmic contact layer over the entire surface Forming a second amorphous silicon layer; Plasma-processing the second amorphous silicon layer with a predetermined gas, and then doping the plasma-treated second amorphous silicon layer with impurities in a plasma manner; Etching the second and first amorphous silicon layers to expose the gate insulating layer to form an ohmic contact layer and a semiconductor layer; And forming a source / drain electrode on the ohmic contact layer.
Description
본 발명은 박막 트랜지스터 액정표시소자에 관한 것으로, 보다 상세하게는, 저저항의 오믹 접촉층을 형성할 수 있는 박막 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a thin film transistor liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor capable of forming a low resistance ohmic contact layer.
텔레비젼 및 그래픽 디스플레이 등의 표시 장치에 이용되는 액정표시소자(Liquid Crystal Display : 이하, LCD)는 CRT(Cathod-ray tube)를 대신하여 개발되어져 왔다.Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube).
특히, 매트릭스 형태로 배열된 각 화소마다 박막 트랜지스터(Thin Film Transistor : 이하, TFT)가 구비되는 TFT LCD는 고속 응답 특성을 갖는 잇점과 고화소수에 적합하다는 잇점 때문에 CRT에 필적할만한 화면의 고화질화 및 대형화, 컬러화 등을 실현하고 있다.In particular, TFT LCDs equipped with thin film transistors (TFTs) for each pixel arranged in a matrix form have high speed response characteristics and are suitable for high pixel numbers, so that the screen quality comparable to the CRT is increased and large. Colorization is realized.
도 1은 종래 TFT를 도시한 도면으로서, 도시된 바와 같이, 유리 기판(1) 상에 게이트 전극(2)이 형성되며, 이러한 게이트 전극(2)은 유리기판(1) 전면 상에 도포되는 게이트 절연막(3)에 의해 피복된다.FIG. 1 is a view showing a conventional TFT, and as shown, a gate electrode 2 is formed on a glass substrate 1, and the gate electrode 2 is a gate applied on the entire surface of the glass substrate 1. It is covered by the insulating film 3.
또한, 게이트 전극(2) 상부의 게이트 절연막(3) 상에는 패턴의 형태로 비정질실리콘층으로된 반도체층(4)이 형성되며, 이 반도체층(4)의 중심부 상에는 후속 공정인 소오스/드레인 전극 형성시에 반도체층이 손상되는 것을 방지하기 위한 에치 스톱퍼(5)가 형성된다.In addition, a semiconductor layer 4 made of an amorphous silicon layer in the form of a pattern is formed on the gate insulating film 3 on the gate electrode 2, and a source / drain electrode, which is a subsequent process, is formed on the center of the semiconductor layer 4. An etch stopper 5 is formed to prevent the semiconductor layer from being damaged at the time.
그리고, 에치 스톱퍼(5) 및 반도체층(4) 상에는 불순물이 도핑된 비정질실리콘층으로 이루어진 오믹 접촉층(6)이 형성되며, 상기 오믹 접촉층(6) 상에는 소오스/드레인 전극(7a, 7b)이 형성되어 TFT가 완성된다.An ohmic contact layer 6 made of an amorphous silicon layer doped with impurities is formed on the etch stopper 5 and the semiconductor layer 4, and source / drain electrodes 7a and 7b are formed on the ohmic contact layer 6. This is formed to complete the TFT.
그러나, 상기와 같은 종래 TFT는 통상 SiH4가스에 PH3, B2H6, AsH3또는 BF6등의 도핑 가스를 혼합하여 직접 증착하는 방식으로 오믹 접촉층을 형성하게 되는데, 이러한 방식에 의해 형성된 오믹 접촉층은 불순물의 도핑 효율이 낮기 때문에 면저항(Sheet Resistance)이 매우 높으며, 이로 인하여, TFT의 온(On) 전류를 원할하게 유도하는데 어려운 문제점이 있었다.However, the conventional TFT as described above typically forms an ohmic contact layer by directly depositing a doping gas such as PH 3 , B 2 H 6 , AsH 3, or BF 6 into SiH 4 gas. The formed ohmic contact layer has a very high sheet resistance because the doping efficiency of impurities is low, and thus, it is difficult to smoothly induce the on current of the TFT.
따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출된 것으로서, 저저항의 오믹 접촉층을 형성할 수 있는 TFT의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a TFT capable of forming a ohmic contact layer having a low resistance, which is devised to solve the conventional problems as described above.
도 1은 종래 기술에 따른 박막 트랜지스터의 제조방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for manufacturing a thin film transistor according to the prior art.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 박막 트랜지스터의 제조방법을 설명하기 위한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 유리기판 12 : 게이트 전극11 glass substrate 12 gate electrode
13 : 게이트 절연막 14 : 제1비정실리콘층13 gate insulating film 14 first amorphous silicon layer
14a : 반도체층 15 : 금속층14a: semiconductor layer 15: metal layer
15a : 에치 스톱퍼 16 : 제2비정질실리콘층15a: etch stopper 16: second amorphous silicon layer
16a : 오믹 접촉층 17a : 소오스 전극16a: ohmic contact layer 17a: source electrode
17b : 드레인 전극17b: drain electrode
상기와 같은 목적을 달성하기 위한 본 발명의 TFT의 제조방법은, 상부면에 게이트 전극이 형성되고, 상기 게이트 전극이 덮혀지도록 상부면 전면에 게이트 절연막이 도포된 기판을 제공하는 단계; 상기 게이트 절연막 상에 반도체층을 형성하기 제1비정질실리콘층과 에치 스톱퍼를 형성하기 위한 금속층을 순차적으로 형성하는 단계; 상기 금속층을 식각하여 게이트 전극 상부의 제1비정질실리콘층 부분 상에 에치 스톱퍼를 형성하는 단계; 상기 에치 스톱퍼 양측의 노출된 제1비정질실리콘층 표면을 소정 가스로 플라즈마 처리하여 미세 결정화시킨 후, 상기 플라즈마 처리된 제1비정질실리콘층 표면에 플라즈마 방식으로 불순물을 도핑하는 단계: 전체 상부에 오믹 접촉층을 형성하기 위한 제2비정질실리콘층을 형성하는 단계; 상기 제2비정질실리콘층을 소정 가스로 플라즈마 처리하여 미세결정화시킨 후, 상기 플라즈마 처리된 제2비정질실리콘층에 플라즈마 방식으로 불순물을 도핑하는 단계; 상기 게이트 절연막이 노출되도록 상기 제2 및 제1비정질실리콘층을 식각하여 오믹 접촉층 및 반도체층을 형성하는 단계; 및 상기 오믹 접촉층 상에 소오스/드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a TFT, including: providing a substrate having a gate electrode formed on an upper surface thereof, and a gate insulating film coated on an entire surface of the upper surface such that the gate electrode is covered; Sequentially forming a first amorphous silicon layer for forming a semiconductor layer and a metal layer for forming an etch stopper on the gate insulating film; Etching the metal layer to form an etch stopper on a portion of the first amorphous silicon layer on the gate electrode; Plasma-crystallizing the exposed first amorphous silicon layer surfaces on both sides of the etch stopper with a predetermined gas, and then doping impurities on the plasma-treated first amorphous silicon layer surface in a plasma manner: Forming a second amorphous silicon layer for forming the layer; Plasma-treating the second amorphous silicon layer with a predetermined gas and then doping impurities into the plasma-treated second amorphous silicon layer in a plasma manner; Etching the second and first amorphous silicon layers to expose the gate insulating layer to form an ohmic contact layer and a semiconductor layer; And forming a source / drain electrode on the ohmic contact layer.
본 발명에 따르면, 오믹 접촉층과 접촉될 반도체층 부분을 미세 결정질화시키고, 이어서, 이러한 반도체층 부분에 미세 결정화된 오믹 접촉층을 형성시킴으로써, 상기 오믹 접촉층의 면저항을 현저하게 감소시킬 수 있다.According to the present invention, it is possible to remarkably reduce the sheet resistance of the ohmic contact layer by finely crystallizing the portion of the semiconductor layer to be in contact with the ohmic contact layer, and then forming the microcrystalline crystallized ohmic contact layer on the semiconductor layer portion. .
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 TFT의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a TFT according to an embodiment of the present invention.
본 발명의 실시예에 따른 TFT 제조방법은, 먼저 도 2a에 도시된 바와 같이, 유리기판(11) 상에 게이트 전극(12)을 형성하고, 상기 게이트 전극(12)이 덮혀지도록 유리기판(11) 전면상에 게이트 절연막(13)을 형성한다.In the TFT manufacturing method according to the embodiment of the present invention, first, as shown in FIG. 2A, the gate electrode 12 is formed on the glass substrate 11, and the glass substrate 11 is covered so that the gate electrode 12 is covered. ) A gate insulating film 13 is formed on the entire surface.
그다음, 전체 상부에 반도체층을 형성하기 위한 제1 비정질실리콘층(14)과 에치 스톱퍼를 형성하기 위한 금속층(15)을 순차적으로 형성한다.Subsequently, the first amorphous silicon layer 14 for forming the semiconductor layer and the metal layer 15 for forming the etch stopper are sequentially formed on the whole.
이어서, 도 2b에 도시된 바와 같이, 금속층(15)을 패터닝하여 제1 비정질실리콘층(14)상에 에치 스톱퍼(15a)를 형성한다음 에치 스톱퍼(15a) 양측의 노출된 제1 비정질실리콘층(14) 표면을 수소 및 SiF4가스로 플라즈마 처리하여 상기 제1비정질실리콘층 표면을 미세 결정질화시킨 후, 연속적으로 미세 결정질화된 제1비정질시리콘층(14) 표면에 플라즈마 방식으로 불순물을 도핑시킨다.Subsequently, as shown in FIG. 2B, the metal layer 15 is patterned to form an etch stopper 15a on the first amorphous silicon layer 14, and then the exposed first amorphous silicon layer on both sides of the etch stopper 15a. (14) The surface of the first amorphous silicon layer 14 is subjected to plasma treatment with hydrogen and SiF 4 gas to microcrystallize the impurities, and then impurities are continuously applied to the surface of the first amorphous silicon layer 14 which is subsequently microcrystalline. Doping
그다음, 전체 상부에 오믹 접촉층을 형성하기 위한 제2 비정질실리콘층 (16)을 10 내지 1,000Å 두께로 형성하고, 이러한 제2 비정질실리콘층(16)을 이전 공정과 동일하게 수소 및 SiF4가스로 플라즈마 처리하여 미세 결정질화시킨 후, 플라즈마 방식으로 불순물을 도핑시킨다.Next, a second amorphous silicon layer 16 for forming an ohmic contact layer on the whole is formed to a thickness of 10 to 1,000 mm 3, and the second amorphous silicon layer 16 is formed of hydrogen and SiF 4 gas in the same manner as in the previous process. After plasma crystallization to fine crystallization, impurities are doped in a plasma manner.
이어서, 도 2c에 도시된 바와 같이, 제2 및 제1 비정질실리콘층을 동시에 식각하여 오믹 접촉층(16a) 및 반도체층(14a)을 형성한 후, 공지된 방법으로 오믹 접촉층(16a) 상에 소오스/드레인 전극(17a, 17b)을 형성하여 TFT를 완성한다.Subsequently, as shown in FIG. 2C, the second and first amorphous silicon layers are simultaneously etched to form the ohmic contact layer 16a and the semiconductor layer 14a, and then, on the ohmic contact layer 16a by a known method. Source / drain electrodes 17a and 17b are formed in the TFT to complete the TFT.
전술된 바와 같이, 본 발명은 비정질실리콘층의 형성, 미세 결정질화를 위한 플라즈마 처리 및 플라즈마 방식에 의한 불순물 도핑 공정을 순차적으로 실시하여 오믹 접촉층을 형성하기 때문에 종래보다는 불순물의 도핑 효율을 최소한 10배 이상 향상시킬 수 있다. 따라서, 오믹 접촉층의 면저항을 효과적으로 감소시킬 수 있게 된다.As described above, in the present invention, since the ohmic contact layer is formed by sequentially performing the formation of the amorphous silicon layer, the plasma treatment for fine crystallization, and the impurity doping process by the plasma method, the doping efficiency of the impurity is at least 10. It can be improved more than twice. Therefore, the sheet resistance of the ohmic contact layer can be effectively reduced.
또한, 오믹 접촉층을 형성하기 이전에 오믹 접촉층과 콘택될 반도체층 부분을 미세 결정질화시키기 때문에 오믹 접촉층의 저항을 더욱 감소시킬 수 있으며, 아울러, 이동도를 향상시킬 수 있게 된다.In addition, since the portion of the semiconductor layer to be contacted with the ohmic contact layer is microcrystalline before forming the ohmic contact layer, the resistance of the ohmic contact layer can be further reduced, and the mobility can be improved.
이상에서 설명된 같이, 본 발명은 비정질실리콘층을 플라즈마 처리한후 연이어서 플라즈마 방식으로 불순물을 도포하는 방법으로 오믹 접촉층을 형성함으로써, 반도체층과 소오스/드레인 전극 사이에 개재되는 오믹 접촉층의 저항을 현격하게 감소시킬 수 있어 고이동도 및 저 누설전류를 갖는 박막 트랜지스터를 구현할 수 있다.As described above, the present invention provides an ohmic contact layer interposed between a semiconductor layer and a source / drain electrode by forming an ohmic contact layer by plasma treatment of an amorphous silicon layer and subsequently applying impurities in a plasma manner. Since the resistance can be significantly reduced, a thin film transistor having high mobility and low leakage current can be realized.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8198657B2 (en) | 2009-09-21 | 2012-06-12 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
| KR101447998B1 (en) * | 2013-11-22 | 2014-10-14 | 삼성디스플레이 주식회사 | Method for manufacturing display device |
| US9070718B2 (en) | 2007-12-18 | 2015-06-30 | Samsung Display Co., Ltd. | Thin film transistor having semiconductor with different crystallinities and manufacturing method thereof |
| US9093540B2 (en) | 2012-06-04 | 2015-07-28 | Samsung Display Co., Ltd. | Oxide semicondutor thin film transistor |
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| KR20020034582A (en) * | 2000-11-02 | 2002-05-09 | 전주범 | Key device for microwave oven using change of capacitance thereof |
| KR101006439B1 (en) * | 2003-11-12 | 2011-01-06 | 삼성전자주식회사 | Method for manufacturing of Thin film transistor array panel |
| KR101642271B1 (en) * | 2015-03-31 | 2016-07-25 | 주식회사 디씨티 | Method for Manufacturing Dopant Doped Silicon Nano Material and Local Doping Method thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9070718B2 (en) | 2007-12-18 | 2015-06-30 | Samsung Display Co., Ltd. | Thin film transistor having semiconductor with different crystallinities and manufacturing method thereof |
| US8198657B2 (en) | 2009-09-21 | 2012-06-12 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and method for manufacturing the same |
| US9093540B2 (en) | 2012-06-04 | 2015-07-28 | Samsung Display Co., Ltd. | Oxide semicondutor thin film transistor |
| US9455333B2 (en) | 2012-06-04 | 2016-09-27 | Samsung Display Co., Ltd. | Thin film transistor array panel |
| US9793377B2 (en) | 2012-06-04 | 2017-10-17 | Samsung Display Co., Ltd. | Thin film transistor, thin film transistor array panel including the same, and manufacturing method thereof |
| USRE48290E1 (en) | 2012-06-04 | 2020-10-27 | Samsung Display Co., Ltd. | Thin film transistor array panel |
| KR101447998B1 (en) * | 2013-11-22 | 2014-10-14 | 삼성디스플레이 주식회사 | Method for manufacturing display device |
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