KR100707010B1 - Method for manufacturing tft-lcd - Google Patents

Abstract

The present invention discloses a method of manufacturing a TFT-LCD. The disclosed invention includes depositing a metal film on an insulating substrate and patterning the metal film by a first photolithography process to form a gate electrode and a storage electrode; Defining a thin film transistor region by sequentially forming a gate insulating film, an amorphous silicon layer for a channel, and a doped semiconductor layer on an insulating substrate on which the gate electrode and the storage electrode are formed, and patterning the films by a second photolithography process; A source / drain metal film is deposited on a substrate resultant in which the thin film transistor region is limited, and the source / drain metal film is patterned by a third photolithography process to form source / drain electrodes disposed on both sides of the channel amorphous silicon layer. Making; Etching the exposed doped semiconductor layer portion using the source / drain electrodes as a mask; Primary annealing the amorphous silicon layer for the channel; Depositing a passivation film on an insulating substrate on which the source / drain electrodes are formed, and patterning the passivation film by a fourth photolithography process to form a via hole exposing a drain electrode; Depositing a transparent conductive material to contact the drain electrode exposed on the passivation layer, and patterning the transparent conductive material by a fifth photolithography process to form a pixel electrode; And second annealing the substrate resultant on which the pixel electrode is formed.

Description

Method of manufacturing thin film transistor-liquid crystal display device {METHOD FOR MANUFACTURING TFT-LCD}

1A to 1E are cross-sectional views of respective processes for explaining a method of manufacturing a conventional thin film transistor liquid crystal display device.

2A to 2F are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing a liquid crystal display device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

11: insulated substrate 12a: gate electrode

13 gate insulating film 14 amorphous silicon layer

15 doped semiconductor layer 16a source electrode

16b: drain electrode 17: passivation film

18: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor-liquid crystal display element (hereinafter, TFT-LCD), and more particularly, to a method for manufacturing a TFT-LCD which can reduce leakage current.

Generally, in the liquid crystal display element, the active matrix liquid crystal display element has a high speed response and has a large number of pixels. As a result, the display screen has high characteristics such as high image quality, large size, and color screen, and is used in portable TVs, notebook PCs, automobile navigation systems, and the like.

In such an active matrix liquid crystal display device, switching elements such as diodes or thin film transistors are arranged and designed at intersections of gate lines and data lines to selectively turn on / off the pixel electrodes.

A method of manufacturing a conventional liquid crystal display device including such a thin film transistor will be described with reference to FIGS. 1A to 1E.

First, as shown in FIG. 1A, a metal layer for gate electrode wiring is deposited to a predetermined thickness on the surface of the insulating substrate 1. Then, the metal film is partially patterned through the first photolithography process to form the gate electrode 2a and the storage electrode 2b.

As shown in FIG. 1B, a gate insulating film 3 is deposited to a predetermined thickness on the insulating substrate 1 on which the gate electrode 2a and the storage electrode 2b are formed, and then serve as a channel of the thin film transistor. The amorphous silicon layer 4 and the doped semiconductor layer 5 are sequentially deposited. Thereafter, in the second photolithography process, the doped semiconductor layer 5 and the amorphous silicon layer 4 are patterned to exist in the thin film transistor predetermined region.

Next, as shown in FIG. 1C, a source and drain metal film is deposited on the resultant of the insulating substrate 1, and then the third film is etched so that the metal film is present on both sides of the amorphous silicon layer 4. Patterning is performed to form source and drain electrodes 6a and 6b. At this time, during the patterning process of the source and drain electrodes 6a and 6b, the doped semiconductor layer 5 is also patterned in the form of the source and drain electrodes 6a and 6b.

Thereafter, as shown in FIG. 1D, the passivation film 7 is formed of a silicon nitride film on the insulating substrate 1 on which the source and drain electrodes 6a and 6b are formed. Then, the passivation film 7 is etched through the fourth photolithography process so that the predetermined portion of the drain electrode 6b is opened to form the via hole h.

Subsequently, as shown in FIG. 1E, an indium tin oxide (ITO) film is deposited on the passivation film 7 so as to contact the drain electrode 6b exposed through the via hole h. Through this, the ITO film is partially etched to form the pixel electrode 8. The resultant is then annealed.

However, in the method of forming the TFT-LCD using the above-described conventional five times photolithography process, the amorphous silicon layer for the channel is likely to be partially lost or damaged during patterning to form the source and drain electrodes. For this reason, the leakage current Ioff is much larger than that of the TFT-LCD having the etch stopper, about 100 PA.

In addition, if a subsequent passivation film is deposited on the channel amorphous silicon layer damaged by the patterning of the source and drain electrodes, the defect becomes gradually larger, and the surface of the amorphous silicon layer becomes rough, and the optical sensitivity is also increased. In addition, it is difficult to produce a high quality TFT-LCD.                         

In addition, in order to reduce such leakage current, the formation of an etch stopper on the upper part of the channel layer adds another step to the photolithography process, thereby increasing the manufacturing cost.

Accordingly, an object of the present invention is to provide a method of manufacturing a TFT-LCD, which can reduce leakage current without adding a photolithography process, to solve the above-described conventional problems.

In order to achieve the above object of the present invention, the present invention comprises the steps of depositing a metal film on an insulating substrate, patterning the metal film by a first photolithography process to form a gate electrode and a storage electrode; A thin film transistor is formed by sequentially forming a gate insulating layer, an amorphous silicon layer for a channel, and a doped semiconductor layer on an insulating substrate on which the gate electrode and the storage electrode are formed, and patterning the doped semiconductor layer and the amorphous silicon layer by a second photolithography process. Defining an area; A source / drain metal film is deposited on a substrate resultant in which the thin film transistor region is limited, and the source / drain metal film is patterned by a third photolithography process to form source / drain electrodes disposed on both sides of the channel amorphous silicon layer. Making; Etching the exposed doped semiconductor layer portion using the source / drain electrodes as a mask; First annealing the amorphous silicon layer for the channel so that damage to the surface of the amorphous silicon layer for the channel generated during the etching of the doped semiconductor layer is cured; Depositing a passivation film on an insulating substrate on which the source / drain electrodes are formed, and patterning the passivation film by a fourth photolithography process to form a via hole exposing a drain electrode; Depositing a transparent conductive material to contact the drain electrode exposed on the passivation layer, and patterning the transparent conductive material by a fifth photolithography process to form a pixel electrode; And secondary annealing the substrate resultant on which the pixel electrode is formed.

Here, the first and second annealing step is characterized in that the progress for 50 to 70 minutes at a nitrogen gas (N ₂ ) atmosphere and a temperature of 270 to 290 ℃.

According to the present invention, an annealing process is performed between the process of forming the source and drain electrodes and the process of forming the passivation film in the process of manufacturing the TFT-LCD by the five photolithography processes. Accordingly, the damage of the amorphous silicon layer for the channel can be healed, and the leakage current can be reduced while improving the operating current without forming an etch stopper. Thus, the operating characteristics of the TFT-LCD are improved.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing a liquid crystal display device according to the present invention.

First, as shown in FIG. 2A, a metal layer for gate electrode wiring is deposited on a surface of an insulating substrate 11, for example, a transparent glass substrate, to a predetermined thickness. Then, the metal film is partially patterned through the first photolithography process to form the gate electrode 12a and the storage electrode 12b.

As shown in FIG. 2B, the gate insulating layer 13 is deposited on the insulating substrate 11 on which the gate electrode 12a and the storage electrode 2b are formed to a predetermined thickness, and then serve as a channel of the thin film transistor. The amorphous silicon layer 14 and the doped semiconductor layer 15 are sequentially deposited. Thereafter, in the second photolithography process, the doped semiconductor layer 15 and the amorphous silicon layer 14 are patterned into an active form of a thin film transistor.

Next, as shown in FIG. 2C, a source and drain metal film is deposited on the resultant of the insulating substrate 11, and then the third film is etched so that the metal film exists on both sides of the amorphous silicon layer 14. Patterning is performed to form source and drain electrodes 16a and 16b. At this time, the exposed doped semiconductor layer 15 is patterned using the source and drain electrodes 16a and 16b as a mask to expose the amorphous silicon layer 14. In this case, damage to the surface of the amorphous silicon layer 14 may occur due to the formation of the source, the drain electrodes 16a and 16b and the semiconductor layer 15.

Then, referring to FIG. 2D, the exposed channel amorphous silicon layer 14 is annealed to cure damage to the exposed channel amorphous silicon layer 14. At this time, the annealing process is performed in a nitrogen gas (N ₂ ) atmosphere at a temperature of about 270 to 290 ° C. for about 50 to 70 minutes.

Next, as shown in FIG. 2E, a passivation film 17 is formed of a silicon nitride film on the insulating substrate 11 on which the source and drain electrodes 16a and 16b are formed. Thereafter, the passivation film 17 is etched through the fourth photolithography process so that the predetermined portion of the drain electrode 16b is opened to form the via hole h.

Next, as shown in FIG. 2F, an ITO film is deposited on the passivation film 17 so as to contact the drain electrode 16b exposed through the via hole h. Subsequently, the ITO film is partially etched through the fifth photolithography process to form the pixel electrode 8.

Thereafter, in order to secure the reliability of the amorphous silicon layer, annealing is performed again in the same process as the annealing conditions.

Thus, the results after annealing between the steps of forming the source and drain electrodes 16a and 16b and the step of forming the passivation film 17 are shown in Table 1 below.

(table)

Prior art The present invention Threshold voltage Mobility Operating current Leakage Current (-8V) Threshold voltage Mobility Operating current Leakage Current (-8V) Single measurement 1.093 0.288 0.935 13.6 1.157 0.406 1.32 2.38 2 measurements 1.137 0.284 0.917 15.0 1.848 0.412 1.19 2.36 3 measurements 1.097 0.273 0.895 14.1 1.452 0.391 1.23 2.41 Average 1.109 0.281 0.916 14.2 1.486 0.403 1.247 2.4

According to the above table, when the annealing process is performed before the passivation film is formed as in the present invention, the operating current is increased while the leakage current is considerably reduced, thereby improving the operating characteristics of the TFT-LCD.

As described in detail above, according to the present invention, an annealing process is performed between a process of forming a source and a drain electrode and a process of forming a passivation film in a process of manufacturing a TFT-LCD by five photolithography processes. Accordingly, the damage of the amorphous silicon layer for the channel can be healed, and the leakage current can be reduced while improving the operating current without forming an etch stopper. Thus, the operating characteristics of the TFT-LCD are improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

Depositing a metal film on an insulating substrate and patterning the metal film by a first photolithography process to form a gate electrode and a storage electrode; A thin film transistor is formed by sequentially forming a gate insulating layer, an amorphous silicon layer for a channel, and a doped semiconductor layer on an insulating substrate on which the gate electrode and the storage electrode are formed, and patterning the doped semiconductor layer and the amorphous silicon layer by a second photolithography process. Defining an area; A source / drain metal film is deposited on a substrate resultant in which the thin film transistor region is limited, and the source / drain metal film is patterned by a third photolithography process to form source / drain electrodes disposed on both sides of the channel amorphous silicon layer. Making; Etching the exposed doped semiconductor layer portion using the source / drain electrodes as a mask; First annealing the amorphous silicon layer for the channel so that damage to the surface of the amorphous silicon layer for the channel generated during the etching of the doped semiconductor layer is cured; Depositing a passivation film on an insulating substrate on which the source / drain electrodes are formed, and patterning the passivation film by a fourth photolithography process to form a via hole exposing a drain electrode; Depositing a transparent conductive material to contact the drain electrode exposed on the passivation layer, and patterning the transparent conductive material by a fifth photolithography process to form a pixel electrode; And And second annealing the substrate resultant on which the pixel electrode is formed. The method of claim 1, wherein the first and second annealing steps are performed for 50 to 70 minutes at a nitrogen gas (N ₂ ) atmosphere and at a temperature of 270 to 290 ° C.

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