KR20010003189A - Method For Manufacturing The Thin Film Transistor Of Semiconductor Device - Google Patents
Method For Manufacturing The Thin Film Transistor Of Semiconductor Device Download PDFInfo
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- KR20010003189A KR20010003189A KR1019990023383A KR19990023383A KR20010003189A KR 20010003189 A KR20010003189 A KR 20010003189A KR 1019990023383 A KR1019990023383 A KR 1019990023383A KR 19990023383 A KR19990023383 A KR 19990023383A KR 20010003189 A KR20010003189 A KR 20010003189A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 71
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims abstract description 54
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 230000000873 masking effect Effects 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 35
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000003317 industrial substance Substances 0.000 claims 1
- 238000000137 annealing Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229920000936 Agarose Polymers 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78627—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 폴리실리콘층으로 된 게이트의 좌,우 양측에 소오스/드레인영역의 극성과 같은 카운터 도핑영역을 형성하여 트랜지터를 작동할 때, 누설전류를 줄여주도록 하거나, 또는, 게이트의 드레인영역 방향으로 카운터 도핑영역을 형성하여 소오스영역은 게이트와 오버랩 영역을 주고 드레인영역은 게이트와 일정하게 간격을 두는 오프셋영역을 주어서 공급 전류는 늘려주고 차단전류는 줄여주도록 하는 반도체소자의 박막트랜지스터(Thin Film Transistor ; TFT) 형성방법에 관한 것이다.The present invention forms counter-doped regions, such as the polarity of the source / drain regions, on the left and right sides of the gate made of polysilicon to reduce leakage current when the transistor is operated, or in the direction of the drain region of the gate. The thin film transistor of the semiconductor device is formed to increase the supply current and reduce the cutoff current by forming a counter doping region so that the source region provides an overlap region with the gate and the drain region has an offset region spaced from the gate. ; TFT) forming method.
일반적으로, SRAM반도체장치에서 Load Device에 따라 크게 HLR(High Load Resister)타입과, 풀 CMOS 타입과, 박막트랜지스터(TFT; Thin Film Transistor)타입등과 같이 세가지로 분류가 되며, 박막트랜지스터 구조를 갖는 SRAM에서 게이트를 형성하는 상태를 살펴 보도록 한다.In general, SRAM semiconductor devices are classified into three types, such as HLR (High Load Resister) type, Full CMOS type, and Thin Film Transistor (TFT) type, depending on the load device. Let's take a look at the state of gate formation in SRAM.
우선, 반도체기판 상에 게이트전극의 역할을 하는 폴리실리콘층을 적층한 후 마스킹식각으로 패터닝한다. 그리고, 게이트 폴리층에 이온을 주입하여 도핑시킨다.First, a polysilicon layer serving as a gate electrode is stacked on a semiconductor substrate and then patterned by masking etching. Then, ions are implanted into the gate poly layer to be doped.
그리고, 게이트 폴리층 상부면에 게이트산화막을 적층한 후 연속하여 비정질실리콘층을 적층하여 마스킹으로 게이트와 겹쳐지는 부위를 제외한 부위의 비정질실리콘층 노출시킨 상태에서 이온을 주입하여 소오스/드레인영역을 형성한 후 그 부위에 이온을 주입하여 박막트랜지스터를 형성 한다.After stacking the gate oxide layer on the upper surface of the gate poly layer and subsequently laminating the amorphous silicon layer, the source / drain regions are formed by implanting ions while exposing the amorphous silicon layer in a portion other than the portion overlapping the gate by masking. After that, ions are implanted into the site to form a thin film transistor.
이와 같이, SRAM 반도체장치의 로드(Load)부분으로 스탠바이 커런트(Stand By Current ; 출력의 부하나 기준 전압의 부하가 없는 경우에 제어 소자에 흘러들어가는 전원 전류)를 줄이기 위하여 저 전력과 낮은 스탠바이 커런트를 만들기 위하여 많은 연구가 이루어 져서, 최근에는 FCMOS 트랜지스터를 채용하고 있다.As such, low power and low standby current may be used to reduce standby current as a load portion of an SRAM semiconductor device, to reduce a standby current flowing into a control element when there is no load of an output or a reference voltage. Much research has been done to make this, and recently, FCMOS transistors have been adopted.
그러나, FCMOS 기술의 경우에는 NMOC/PMOS가 각각 4개와 2개를 사용하고 되므로 셀의 면적이 커져서 네트 다이(Net Die)감소에 의한 생산성이 저하되는 단점을 지니고 있었다.However, in the case of FCMOS technology, four and two NMOC / PMOS are used, respectively, which has a disadvantage in that productivity is reduced due to the reduction of the net die due to the large cell area.
이와는 반대로 TFT기술을 이용한 셀의 구조로는 박막트랜지스터 부분을 적층(Stack)구조로 쌓을 수 있으므로 네트다이 및 네트 사이즈 측면에서 유리하지만 스탠바이 커런트가 나빠지고 누설전류가 커지므로 소자의 전기적인 특성이 저하되는 문제점을 지니고 있었다.On the contrary, in the cell structure using TFT technology, thin film transistor parts can be stacked in a stack structure, which is advantageous in terms of net die and net size, but the standby current is worsened and the leakage current is increased, thereby deteriorating the electrical characteristics of the device. Had the problem of becoming.
본 발명의 목적은, 폴리실리콘층으로 된 게이트의 좌,우 양측에 소오스/드레인영역의 극성과 같은 카운터 도핑영역을 형성하여 트랜지터를 작동할 때, 누설전류를 줄여주도록 하거나, 또는, 게이트의 드레인영역 방향으로 카운터 도핑 (Counter Dopping)영역을 형성하여 소오스영역은 게이트와 오버랩 영역을 주고 드레인영역은 게이트와 일정하게 간격을 두는 오프셋(Off set)영역을 주어서 공급 전류는 늘려주고 차단전류는 줄여주어 소자의 전기적인 특성을 향상시키는 것이 목적이다.An object of the present invention is to form a counter-doped region, such as the polarity of the source / drain regions, on the left and right sides of a gate made of polysilicon layer so as to reduce the leakage current when operating the transistor, or A counter doping area is formed in the direction of the drain area, so that the source area provides an overlap area with the gate, and the drain area gives an offset area that is spaced at a constant distance from the gate, thereby increasing the supply current and reducing the blocking current. The purpose is to improve the electrical characteristics of the subject device.
도 1(a) 내지 도1(f)는 본 발명의 제1실시예에 따른 박막트랜지스터 제조방법을 순차적으로 보인 도면이고,1 (a) to 1 (f) are views sequentially showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention,
도 2(a) 내지 도2(f)는 본 발명의 제2실시예에 따른 박막트랜지스터 제조방법을 순차적으로 보인 도면이며,2 (a) to 2 (f) are views sequentially showing a thin film transistor manufacturing method according to a second embodiment of the present invention,
도 3은 본 발명의 제3실시예에 따른 박막트랜지스터의 구성을 보인 도면이며,3 is a view showing the configuration of a thin film transistor according to a third embodiment of the present invention,
도 4는 본 발명의 제2실시예에 따른 박막트랜지스터에서 길이에 따른 도즈량의 분포를 보인 도면이다.4 is a view showing a distribution of doses along lengths in a thin film transistor according to a second exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10,110 : 반도체기판 20,120 : 게이트폴리실리콘층10,110 semiconductor substrate 20,120 gate polysilicon layer
30,130 : 감광막 40,140 : 감광막30,130 photosensitive film 40,140 photosensitive film
50,150 : 게이트산화막 60,160 : 비정질실리콘층50,150: gate oxide film 60,160: amorphous silicon layer
62,162 : 소오스영역 64,164 : 채널영역62,162 Source area 64,164 Channel area
66,166 : 드레인영역 70,170 : 감광막66,166 Drain region 70,170 Photosensitive film
a ; 오버랩영역 b : 오프셋영역a; Overlap area b: Offset area
이러한 목적은 제1실시예로서, 반도체기판 상에 게이트폴리실리콘층을 적층한 후 마스킹 식각으로 패턴을 형성하는 단계와; 상기 게이트폴리실리콘층의 양측 끝단부분을 차단하도록 감광막을 적층하여 개방된 게이트폴리실리콘층에 P+혹은 N+이온을 도핑하여 주입하는 단계와; 상기 게이트폴리실리콘층에 P+혹은 N+이온이 도핑된 부위를 차단하도록 감광막을 적층하여 게이트폴리실리콘층에 주입된 이온의 반대의 이온을 카운터 도핑영역에 주입하는 단계와; 상기 결과물 상에 게이트산화막 및 비정질실리콘층을 연속하여 적층하는 단계와; 상기 비정질실리콘층 상에 게이트폴리실리콘층과 같은 너비로 감광막을 적층하여 상기 카운터 도핑영역에 주입된 이온과 같은 이온을 도핑하여 채널영역 양측으로 소오스/드레인영역을 형성하는 단계를 포함한 반도체소자의 박막 트랜지스터 제조방법을 제공함으로써 달성된다.This object is a first embodiment, comprising: forming a pattern by masking etching after stacking a gate polysilicon layer on a semiconductor substrate; Stacking photoresist to block both ends of the gate polysilicon layer, and implanting P + or N + ions into the open gate polysilicon layer; Stacking a photoresist film on the gate polysilicon layer to block a region doped with P + or N + ions and injecting ions opposite to the ions injected into the gate polysilicon layer into a counter doping region; Sequentially depositing a gate oxide film and an amorphous silicon layer on the resultant product; Forming a source / drain region on both sides of the channel region by stacking a photoresist on the amorphous silicon layer with the same width as the gate polysilicon layer and doping ions such as ions injected into the counter doping region. It is achieved by providing a transistor manufacturing method.
그리고, 제2실시예로서, 반도체기판 상에 게이트폴리실리콘층을 적층한 후 마스킹 식각으로 패턴을 형성하는 단계와; 상기 게이트폴리실리콘층에서 드레인 영역에 있는 끝단부분을 차단하도록 감광막을 적층하여 개방된 게이트폴리실리콘층에 P+혹은 N+이온을 도핑하여 주입하는 단계와; 상기 게이트폴리실리콘층에 P+혹은 N+이온이 도핑된 부위를 차단하도록 감광막을 적층하여 게이트폴리실리콘층에 주입된 이온의 반대의 이온을 카운터 도핑영역에 주입하는 단계와; 상기 결과물 상에 게이트산화막 및 비정질실리콘층을 연속하여 적층하는 단계와; 상기 비정질실리콘층 상에 소오스영역이 게이트폴리실리콘층과 오버랩되고, 드레인영역은 게이트폴리실리콘층과 일정거리 벗어나도록 감광막을 적층하여 상기 카운터 도핑영역에 주입된 이온과 같은 이온을 소오스/드레인영역의 오버랩영역에 주입하는 단계; 상기 결과물의 감광막이 적층된 영역에서 비정질실리콘층의 오버랩영역을 차단하도록 감광막을 적층하여 소오스/드레인영역에 주입되는 이온 보다 더 강한 이온을 주입하는 단계를 포함한 반도체소자의 박막 트랜지스터 제조방법을 제공함으로써 달성된다.In another embodiment, the method may further include forming a pattern by masking etching after stacking a gate polysilicon layer on a semiconductor substrate; Stacking a photoresist film so as to block an end portion of the drain region in the gate polysilicon layer, and implanting P + or N + ions into the open gate polysilicon layer; Stacking a photoresist film on the gate polysilicon layer to block a region doped with P + or N + ions and injecting ions opposite to the ions injected into the gate polysilicon layer into a counter doping region; Sequentially depositing a gate oxide film and an amorphous silicon layer on the resultant product; A source region overlaps with the gate polysilicon layer on the amorphous silicon layer, and a drain photoresist layer is stacked so as to deviate by a predetermined distance from the gate polysilicon layer, thereby depositing ions such as ions injected into the counter doping region of the source / drain region. Implanting in an overlap area; By providing a method of manufacturing a thin film transistor of a semiconductor device comprising the step of injecting a stronger photovoltaic layer than the ions injected into the source / drain region by stacking the photosensitive film to block the overlap region of the amorphous silicon layer in the region of the resulting photoresist film Is achieved.
그리고, 상기 게이트폴리실리콘층은 저압화학기상증착법(Low Pressure Chemical Vapor Deposition Process)으로 800 ∼ 1200Å의 두께로 형성하고, 상기 게이트산화막은 HTO산화막을 사용하여, 750 ∼ 800℃의 온도범위에서 300 ∼ 500Å의 두께로 형성하도록 한다.The gate polysilicon layer is formed to a thickness of 800 to 1200 kPa by a Low Pressure Chemical Vapor Deposition Process, and the gate oxide film is 300 to 300 ° C. in a temperature range of 750 to 800 ° C. using an HTO oxide film. The thickness should be 500Å.
또한, 상기 비정질실리콘층은 500 ∼ 600℃의 온도범위에서, 저압화학기상증착법으로 Si2H6가스를 사용하여 300 ∼ 500Å의 두께로 형성하도록 하고, 이 비정질실리콘층을 500 ∼ 700℃의 온도범위에서 4 내지 10시간동안 어닐링(Annealing)하여 그레인 사이즈(Grain Size)를 조대화시키도록 한다.In addition, the amorphous silicon layer is formed to a thickness of 300 ~ 500 600 by using a Si 2 H 6 gas in a low pressure chemical vapor deposition method in the temperature range of 500 ~ 600 ℃, this amorphous silicon layer is a temperature of 500 ~ 700 ℃ Annealing for 4 to 10 hours in the range to coarse the grain size.
그리고, 상기 소오스영역의 오버랩영역에 주입되는 이온은 BF2이고, 30Kev의 에너지로 1.0E13의 도오스량(Dose)으로 주입하고, 상기 오버랩영역을 제외한 소오스/드레인영역에 주입되는 이온은 BF2이고, 30Kev의 에너지로 1.0E15의 도오스량으로 주입하도록 한다.Then, ion is injected to the overlap area of the source region is ion implanted with agarose amount (Dose) diagram of 1.0E13 to a BF 2, 30Kev of energy, and implanted into the source / drain region other than the overlap area is BF 2 And a dose of 1.0E15 at an energy of 30 Kev.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 제1실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1(a)는 반도체기판(10) 상에 게이트폴리실리콘층(20)을 적층한 후 마스킹 식각으로 게이트 패턴을 형성하는 상태를 도시하고 있다.FIG. 1A illustrates a state in which a gate pattern is formed by masking etching after stacking the gate polysilicon layer 20 on the semiconductor substrate 10.
도 1(b)는 상기 게이트폴리실리콘층(20)의 양측 끝단부분을 차단하도록 감광막(30)을 적층하여 개방된 게이트폴리실리콘층(20)에 PMOS인 경우에는 P+이온을 주입하고, NMOS인 경우에는 N+이온을 주입하는 상태를 도시하고 있다.FIG. 1 (b) shows that P + ions are implanted into the gate polysilicon layer 20, which is formed by stacking the photoresist layer 30 so as to block both ends of the gate polysilicon layer 20. In the case of, the state in which N + ions are implanted is shown.
도 1(c)는 상기 게이트폴리실리콘층(20)에 P+이온 혹은 N+이온이 주입된 부위를 차단하도록 감광막(40)을 적층하여 게이트폴리실리콘층(20)에 주입된 이온의 반대의 이온(즉, P+이온이 주입된 경우에는 N+이온을 주입하고, N+이온이 주입된 경우에는 P+이온을 주입함)을 카운터 도핑영역(25)에 주입하는 상태를 도시하고 있다.FIG. 1 (c) shows the opposite of the ions injected into the gate polysilicon layer 20 by stacking the photosensitive film 40 to block a portion where P + ions or N + ions are injected into the gate polysilicon layer 20. ion shows the state of injecting (if that is, P + if the ions are implanted, the implanted N + ions, N + ions are implanted is also injected into the P + ion) to the counter-doped region (25).
도 1(d) 및 상기 결과물 상에 게이트산화막(50)을 적층한 상태를 도시하고 있다.1 (d) and a state in which the gate oxide film 50 is stacked on the resultant.
도 1(e)는 상기 결과물 상에 비정질실리콘층(60)을 적층한 후 상기 비정질실리콘층(60) 상에 게이트폴리실리콘층(20)과 같은 너비로 감광막(70)을 적층하여 상기 카운터 도핑영역(25)에 주입된 이온과 같은 이온(즉, P+이온이 주입된 경우에는 P+이온을 주입하고, N+이온이 주입된 경우에는 N+이온을 주입함)을 도핑하여 채널영역(64) 양측으로 소오스/드레인영역(62)(66)을 형성하는 상태를 도시하고 있다.FIG. 1 (e) illustrates that the counter doping is performed by stacking an amorphous silicon layer 60 on the resultant and then laminating a photoresist film 70 on the amorphous silicon layer 60 to the same width as the gate polysilicon layer 20. Ions such as ions implanted into the region 25 (i.e., P + ions are implanted when P + ions are implanted, and N + ions are implanted when N + ions are implanted) to do the channel region ( 64. The state in which the source / drain regions 62 and 66 are formed on both sides is shown.
도 1(f)는 상기 비정질실리콘층(60)에 잔류되어 있는 감광막(70)을 제거한 상태를 도시하고 있다.FIG. 1 (f) shows a state in which the photosensitive film 70 remaining in the amorphous silicon layer 60 is removed.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 제2실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a second preferred embodiment of the present invention.
도 2(a)는 반도체기판(110) 상에 게이트폴리실리콘층(120)을 적층한 후 마스킹 식각으로 패턴을 형성하는 상태를 도시하고 있다.2A illustrates a state in which a pattern is formed by masking etching after stacking the gate polysilicon layer 120 on the semiconductor substrate 110.
상기 게이트폴리실리콘층(120)은 저압화학기상증착법으로 800 ∼ 1200Å의 두께로 형성하도록 한다.The gate polysilicon layer 120 is formed to a thickness of 800 ~ 1200Å by low pressure chemical vapor deposition.
도 2(b)는 상기 게이트폴리실리콘층(120)에서 드레인(Drain) 영역이 형성될 부위 방향의 끝단부분을 차단하도록 감광막을 적층하여 개방된 게이트폴리실리콘층 (120)에 PMOS인 경우에는 P+이온을 주입하고, NMOS인 경우에는 N+이온을 주입하는 상태를 도시하고 있다.FIG. 2 (b) shows that the PMOS is formed on the gate polysilicon layer 120 opened by stacking a photosensitive film to block the end portion of the gate polysilicon layer 120 where the drain region is to be formed. In the case of NMOS, N + ions are implanted.
도 2(c)는 상기 게이트폴리실리콘층(120)에 P+혹은 N+이온이 도핑된 부위를 차단하도록 감광막(140)을 적층하여 게이트폴리실리콘층(120)에 주입된 이온의 반대의 이온(즉, P+이온이 주입된 경우에는 N+이온을 주입하고, N+이온이 주입된 경우에는 P+이온을 주입함)을 카운터 도핑영역(125)에 주입하는 상태를 도시하고 있다.FIG. 2 (c) shows a photosensitive film 140 stacked on the gate polysilicon layer 120 so as to block a region doped with P + or N + ions, so that ions opposite to the ions implanted into the gate polysilicon layer 120 are formed. shows a state in which the injection (that is, P + ions are implanted when the injection has the N + ions, N + ions are implanted, if the implantation is also a P + ion) to the counter-doped region 125.
도 2(d)는 상기 결과물 상에 게이트산화막(150)을 적층하는 상태를 도시하고 있다.2 (d) illustrates a state in which the gate oxide film 150 is stacked on the resultant product.
이때, 상기 게이트산화막(150)은 HTO산화막을 사용하여, 750 ∼ 800℃의 온도범위에서 300 ∼ 500Å의 두께로 형성 한다.At this time, the gate oxide film 150 is formed to a thickness of 300 ~ 500Å in the temperature range of 750 ~ 800 ℃ using an HTO oxide film.
도 2(e)는 상기 게이트산화막(150) 상에 비정질실리콘층(160)을 적층한 후에 이 비정질실리콘층(160) 상에 소오스영역이 형성될 부위가 게이트폴리실리콘층 (120)과 오버랩 (Over Lap)되고, 드레인영역이 형성될 부위는 게이트폴리실리콘층 (120)과 일정거리 벗어나도록 오프 셋(Off Set)되는 상태로 감광막(170)을 적층 한다.FIG. 2 (e) shows a portion where the source region is to be formed on the amorphous silicon layer 160 after the amorphous silicon layer 160 is stacked on the gate oxide film 150 and overlaps with the gate polysilicon layer 120 ( Over Lap), the photoresist layer 170 is laminated in a state where the drain region is to be formed so as to be offset from the gate polysilicon layer 120 by a predetermined distance.
그런 후에 상기 카운터 도핑영역(125)에 주입된 이온과 같은 이온을 소오스/드레인영역(162)(166)의 오버랩영역(a)에 주입 한다.Thereafter, ions such as ions implanted into the counter doped region 125 are implanted into the overlap region a of the source / drain regions 162 and 166.
상기 비정질실리콘층(160)은 500 ∼ 600℃의 온도범위에서, 저압화학기상증착법으로 Si2H6가스를 사용하여 300 ∼ 500Å의 두께로 형성하도록 하고, 상기 비정질실리콘층(160)을 500 ∼ 700℃의 온도범위에서 4 내지 10시간 동안 어닐링(Annealing)하도록 한다.The amorphous silicon layer 160 is formed in a temperature range of 500 to 600 ° C. by using a low pressure chemical vapor deposition method to form a thickness of 300 to 500 kPa using Si 2 H 6 gas, and forms the amorphous silicon layer 160 to 500 to 600 ° C. Annealing for 4 to 10 hours in the temperature range of 700 ℃.
이 때, 상기 소오스영역(162)의 오버랩영역(a)에 주입되는 이온은 BF2이고, 30Kev의 에너지로 1.0E13의 도오스량으로 주입한 후 감광막(170)을 제거한다.At this time, the ion implanted into the overlap region a of the source region 162 is BF 2, and the photoresist film 170 is removed after implanting at a dose of 1.0E13 with energy of 30 Kev.
도 2(f)는 상기 결과물의 감광막(170)이 적층된 영역에서 비정질실리콘층 (160)의 오버랩영역(a)을 차단하도록 감광막(180)을 적층하여 소오스/드레인영역 (162)(166)에 주입되는 이온 보다 더 강한 에너지로 이온을 주입하는 상태를 도시하고 있다.FIG. 2 (f) shows the source / drain regions 162 and 166 by stacking the photoresist layer 180 to block the overlap region a of the amorphous silicon layer 160 in the region where the resultant photoresist layer 170 is stacked. A state in which ions are implanted with stronger energy than ions implanted in is illustrated.
이 때, 상기 오버랩영역(a)을 제외한 소오스/드레인영역 (162)(164)에 주입되는 이온은 BF2이고, 30Kev의 에너지로 1.0E15의 도오스량으로 주입하도록 한다.At this time, the ions implanted into the source / drain regions 162 and 164 except for the overlap region a are BF 2 and are implanted at a dose of 1.0E15 at an energy of 30 Kev.
도 2(g)는 상기 비정질실리콘층(160) 상에 잔류된 감광막(164)를 제거한 상태를 도시하고 있다.2G illustrates a state in which the photosensitive film 164 remaining on the amorphous silicon layer 160 is removed.
한편, 도 3은 본 발명의 제 3실시예를 도시한 도면으로서, 상기한 제2실시예와 같은 과정을 거치면서 형성되지만 단지 비정질실리콘층(160)의 채널영역(164)에 인접하여 형성되는 드레인영역(166)에 오프 셋(b) 영역이 형성되지 않으므로 소자의 디자인룰을 줄이도록 한다.3 is a view showing a third embodiment of the present invention, which is formed through the same process as the second embodiment, but is formed adjacent to the channel region 164 of the amorphous silicon layer 160. Since the offset (b) region is not formed in the drain region 166, the design rule of the device is reduced.
도 4는 본 발명의 제2실시예의 경우에 비정질실리콘층(160)의 소오스영역 (162), 채널영역(164) 및 드레인영역(166)에 주입되는 이온의 도오즈(Dose)량을 나타내 주고 있다.4 illustrates the dose of ions implanted into the source region 162, the channel region 164, and the drain region 166 of the amorphous silicon layer 160 in the case of the second embodiment of the present invention. have.
상기한 바와 같이, 본 발명에 따른 반도체소자의 박막 트랜지스터 제조방법을 이용하게 되면, 제1실시예의 경우에는 폴리실리콘층으로 된 게이트의 좌,우 양측에 소오스/드레인영역의 극성과 같은 카운터 도핑영역을 형성하여 트랜지터를 작동할 때, 전류의 흐름을 조절하여 누설전류를 줄여주도록 한다.As described above, in the case of using the method of manufacturing a thin film transistor of a semiconductor device according to the present invention, in the first embodiment, a counter-doped region such as polarity of a source / drain region is formed on both left and right sides of a gate made of a polysilicon layer. When operating the transistor by forming a circuit to regulate the flow of current to reduce the leakage current.
또는, 제2실시에의 경우에는 게이트의 드레인영역 측에 카운터 도핑(Counter Dopping)영역을 형성하여 소오스영역은 게이트와 오버랩 영역을 주고 드레인영역은 게이트와 일정하게 간격을 두는 오프셋(Off set)영역을 주어서 공급 전류(On Current)는 늘려주고 차단전류(Off Current)는 줄여주어 전계효과를 향상시켜 누설전류를 저하시키므로 스탠바이 커런트를 약화시켜 소자의 전기적인 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Alternatively, in the second embodiment, a counter doping region is formed on the drain region side of the gate, so that the source region provides an overlap region with the gate, and the drain region is an offset region spaced at a constant distance from the gate. Increasing the On Current and reducing the Off Current to improve the electric field effect to reduce the leakage current, thereby weakening the standby current to improve the electrical characteristics of the device. to be.
그리고, 제3실시예의 경우에는 제2실시예의 효과를 지니면서도 오프 셋 영역을 없애주어 소자의 크기를 줄여주도록 한다.In the case of the third embodiment, the size of the device is reduced by eliminating the offset region while having the effect of the second embodiment.
Claims (8)
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| KR1019990023383A KR20010003189A (en) | 1999-06-22 | 1999-06-22 | Method For Manufacturing The Thin Film Transistor Of Semiconductor Device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100707010B1 (en) * | 1999-12-29 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing tft-lcd |
| US8785922B2 (en) | 2011-04-06 | 2014-07-22 | Samsung Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
-
1999
- 1999-06-22 KR KR1019990023383A patent/KR20010003189A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100707010B1 (en) * | 1999-12-29 | 2007-04-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for manufacturing tft-lcd |
| US8785922B2 (en) | 2011-04-06 | 2014-07-22 | Samsung Display Co., Ltd. | Thin film transistor, organic luminescence display including the same, and method of manufacturing the organic luminescence display |
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