KR19990062210A - Method of forming interlayer insulating film in semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming an interlayer insulating film of a semiconductor device in which a film is prevented from being lifted by removing protrusions of SOG generated during an EBR process in a method for applying a metal wiring interlayer insulating film using SOG in a semiconductor device. Patterning the first conductive layer, and then planarizing the first interlayer insulating film and the liquid insulating film, and forming a second interlayer insulating film after the planarization process, and removing the via holes and the edges of the substrate for the first conductive layer and the multilayer wiring. And forming a second conductive layer by etching the second interlayer insulating film, the liquid insulating film, and the first interlayer insulating film by anisotropic etching through the mask, and forming a second conductive layer. By removing the protrusions of the insulating film together, the problem of lifting the film can be solved without further processing.

Description

Method of forming interlayer insulating film in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device. More particularly, in a method for applying a metallization interlayer insulating film using SOG in a semiconductor device, a semiconductor is prevented from being lifted by removing protrusions of SOG generated during an EBR process. A method of forming an interlayer insulating film of a device.

Since metal wiring of a semiconductor device has a big influence on the speed, yield, and reliability of a semiconductor device, the metal wiring formation process of a semiconductor device occupies a very important position in the semiconductor device manufacturing process. In general, semiconductor devices have a multi-layered wiring structure in response to the trend of increasing their integration and increasing internal circuit complexity.

The method of forming the multilayer metallization involves a planarization process in order to improve the resolution and depth of focus in a photolithography process. In particular, the planarization process using a spin on glass (SOG) film has advantages such as low cost and simple process, and thus is widely used in the planarization process.

1 to 2 are cross-sectional views illustrating a method of forming an interlayer insulating film of a general semiconductor device.

FIG. 1 illustrates a state in which a first conductive layer 20 is deposited on a semiconductor substrate 10 by a conductive layer pattern, a first interlayer insulating layer 30 is deposited, and then an SOG film 40 is deposited for planarization. It is sectional drawing shown.

The planarization process using the SOG film 40 includes applying a liquid SOG film 40 and baking at about 150 to 400 ° C. to remove the solvent and water. In this process, a condensation phenomenon of the SOG film 40 is generated, and tensile stress is generated in the SOG film 40.

However, after applying the SOG film 40, the SOG film 40 is pushed back when the solvent is sprayed to the edge to remove the SOG film 40 at the edge of the semiconductor substrate 10 for subsequent processing. It will form a protrusion such as'.

2 shows a first conductive layer 20, a first interlayer insulating film 30, an SOG film 40, and a second interlayer insulating film 50 on a semiconductor substrate 10 in turn, and then a second conductive layer ( 60 shows a clamp 70 for holding a wafer when forming 60.

As shown in FIG. 2, after the deposition of the second interlayer insulating film 50, the clamp 70 for processing the wafer during the formation of the via hole and the deposition of the second conductive layer 60 may be used to hold the edge of the wafer. There is a problem that the fixed state is not stabilized by the protrusions and cracks may occur.

SUMMARY OF THE INVENTION The present invention was created to solve the above problems, and an object of the present invention is to effectively remove the protrusions generated during application of the SOG film, which is a liquid insulating film, during the interlayer insulating film forming process of the semiconductor device. A method of forming an insulating film is provided.

1 to 2 are cross-sectional views illustrating a method of forming an interlayer insulating film of a general semiconductor device.

3 to 5 are cross-sectional views illustrating a method of forming an interlayer insulating film of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: substrate 20: first conductive layer

30: first interlayer insulating film 40: SOG film

50: second interlayer insulating film 60: second conductive layer

70: clamp 85: via hole

The present invention for achieving the above object is a step of forming a first conductive layer on a semiconductor substrate and then patterning, planarizing by a first interlayer insulating film, a liquid insulating film, and after the planarization process between the second layer Forming an insulating film and forming a mask for removing edges of the substrate and via holes for the first conductive layer and the multilayer wiring; and etching the second interlayer insulating film, the liquid insulating film, and the first interlayer insulating film by anisotropic etching through the mask. After that, the step of forming a second conductive layer.

As described above, the protrusion of the edge of the substrate generated during the planarization process using the liquid insulating film is also etched along the edge of the substrate when the via hole is formed. Can be lifted.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

3 to 5 are cross-sectional views illustrating a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

FIG. 3 illustrates the patterning of the first conductive layer 20 for lower wiring on the semiconductor substrate 10, and then patterning the SOG film 40 and the second interlayer insulating film 30 for planarization. 50 is a cross-sectional view illustrating a state in which a mask 80 for removing protrusions generated at an edge of a substrate is formed when the via hole 85 and the SOG film 40, which is a liquid insulating film for planarization, are formed.

FIG. 4 etches the second interlayer insulating film 50, the liquid insulating film 40, and the first interlayer insulating film 30 by anisotropic etching through the mask 80 formed in FIG. 3 to expose the first conductive layer 20. In this case, the via hole 85 is formed and the protrusion of the SOG film 40 generated at the edge of the substrate 10 is also removed.

As described above, the via hole 85 is formed in one step by etching the mask 80 and the etching depth to form the via hole 85 without a separate etching process for removing protrusions generated at the edges of the substrate. The protrusion of the SOG film 40 generated at the edge of 10 can also be removed.

5 illustrates a state in which a clamp 70 for fixing the substrate 10 is fixed to the substrate 10 for the process of forming the second conductive layer 60 for the multilayer wiring in the via hole formed in FIG. 4. It is sectional drawing which shows the state in which the 2nd conductive layer 60 was formed.

When the substrate 10 is fixed by the clamp 70, all the protrusions at the edges are removed, so that the subsequent process may be performed in a state where the substrate 10 is stably fixed.

As described above, the present invention has the advantage that the protrusions can be removed without the addition of the process by removing the protrusions of the liquid insulating film generated at the edge of the substrate during the interlayer insulating film forming process of the semiconductor device during the via hole forming process.

In addition, it is possible to eliminate the cause of defects in multi-layer wiring by solving the problem of lifting the SOG film, which is a liquid insulating film due to mechanical contact with the clamp for fixing the substrate by removing the protrusion.

Claims (3)

Forming a first conductive layer on the semiconductor substrate and then patterning the same; Forming a first interlayer insulating film and a liquid insulating film on the entire upper part in order to planarize; Forming a second interlayer insulating film on the liquid insulating film, and forming a mask for removing edges of the via hole and the substrate for the first conductive layer and the multilayer wiring; Anisotropically etching through the mask to etch the second interlayer insulating film, the liquid insulating film, and the first interlayer insulating film; Forming a second conductive layer on the entire structure An interlayer insulating film forming method of a semiconductor device, characterized in that consisting of. The method of claim 1, wherein the liquid insulating film An interlayer insulating film forming method for a semiconductor device, characterized in that the SOG film. The method of claim 1, wherein forming the liquid insulating film to planarize Etching the entire liquid insulating film to expose a first interlayer insulating film Method for forming an interlayer insulating film of a semiconductor device comprising a.