KR19990030755A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR19990030755A KR19990030755A KR1019970051153A KR19970051153A KR19990030755A KR 19990030755 A KR19990030755 A KR 19990030755A KR 1019970051153 A KR1019970051153 A KR 1019970051153A KR 19970051153 A KR19970051153 A KR 19970051153A KR 19990030755 A KR19990030755 A KR 19990030755A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- manufacturing
- ammonia
- ions
- target temperature
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000002019 doping agent Substances 0.000 claims abstract description 21
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- 239000007789 gas Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims 1
- 238000004151 rapid thermal annealing Methods 0.000 abstract description 13
- -1 nitrogen ions Chemical class 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 접합층을 형성한 다음에 급속열처리(rapid thermal annealing, 이하 RTA 라 함) 공정시 목적온도까지 가열하는 동안에는 암모니아 가스를 흘려보내고, 목적온도에 도달한 후에는 암모니아 가스또는 암모니아/질소 혼합가스를 흘려보냄으로써 가열하는 동안 및 열처리온도 유지시 상기 암모니아 가스의 질소이온으로 인한 도펀트의 확산을 최소화하여 얕은 접합을 형성하는 동시에 접합누설전류를 최소화하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein after forming a junction layer, ammonia gas is flowed while heating to a target temperature during a rapid thermal annealing (RTA) process, and the target temperature is reached. Later, by flowing ammonia gas or ammonia / nitrogen mixed gas, the diffusion of dopants due to nitrogen ions of the ammonia gas during heating and at the heat treatment temperature is minimized to form a shallow junction while minimizing the junction leakage current and thereby It is a technology that enables high integration of semiconductor devices.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체소자의 제조공정 중 얕은 접합을 형성한 후, RTA 공정을 실시하여 도펀트를 활성화시키는 동시에 접합누설전류를 최소화하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of minimizing a junction leakage current while activating a dopant by performing a RTA process after forming a shallow junction in a semiconductor device manufacturing process.
반도체소자의 집적도가 증가함에 따라 소오스/드레인의 접합깊이는 점점 더 줄어들게 되어 초저접합 형성의 중요성이 증대되고 있다.As the degree of integration of semiconductor devices increases, the source / drain junction depth decreases more and more, and thus the importance of ultra low junction formation is increasing.
이하, 첨부된 도면을 참고로 하여 종래기술을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the prior art.
도 1a 내지 도 1c 는 본 발명에 따른 반도체소자의 제조방법을 도시한 도면들로서, 도 1a 는 반도체기판 상부에 게이트 산화막 및 게이트 전극을 형성한 것을 도시한 단면도이고, 도 1b 는 소오스와 드레인 접합이 형성됨을 도시한 단면도이며, 도 1c 는 접합층 형성후 열처리 실시조건을 도시한 그래프도이다.1A to 1C are views illustrating a method of manufacturing a semiconductor device according to the present invention. FIG. 1A is a cross-sectional view illustrating a gate oxide film and a gate electrode formed on a semiconductor substrate, and FIG. 1B is a source and drain junction. Figure 1c is a cross-sectional view showing the formation, Figure 1c is a graph showing the heat treatment conditions after forming the bonding layer.
먼저, 반도체기판(11) 위에 소자분리 산화막(도시안됨), 게이트산화막(13), 게이트 전극(15)을 순차적으로 형성한다. (도 1a)First, an element isolation oxide film (not shown), a gate oxide film 13, and a gate electrode 15 are sequentially formed on the semiconductor substrate 11. (FIG. 1A)
다음, 노출된 반도체기판(11)에 도펀트를 이온주입하여 접합층(17)을 형성한다. (도 1b)Next, a dopant is implanted into the exposed semiconductor substrate 11 to form a bonding layer 17. (FIG. 1B)
그 다음, RTA 공정을 실시하여 상기 도펀트를 활성화시키는 동시에 상기 열처리 공정에 의한 도펀트의 확산을 최소화한다.An RTA process is then performed to activate the dopant and to minimize diffusion of the dopant by the heat treatment process.
상기 RTA 공정을 실시하기 위한 목적온도(T)까지 가열하는 시간(S1)과, 목적온도에서 열처리하는 시간(S2) 및 상온으로 냉각시키는 시간(S3)까지 산화막의 생성을 방지하기 위해 질소(N2) 가스를 흘려보낸다. (도 1c)Nitrogen (N2) to prevent the formation of an oxide film until the time (S1) of heating to the target temperature (T) for performing the RTA process, the time of heat treatment at the target temperature (S2) and the time of cooling to room temperature (S3) ) Flow gas. (FIG. 1C)
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 퍼니스에 의한 열처리에 비해 상기 RTA 공정에 의한 도펀트의 확산은 비교적 적지만 아직도 상당한 깊이로의 확산을 일으키게 되어 접합깊이가 증가함과 동시에 접합누설전류가 증가되므로 소자의 전기적 특성을 악화시키는 문제점을 발생시킨다.As described above, in the method of manufacturing a semiconductor device according to the prior art, the diffusion of the dopant by the RTA process is relatively small compared to the heat treatment by the furnace, but still causes diffusion to a considerable depth, resulting in increased junction depth and junction leakage. As the current increases, a problem arises that deteriorates the electrical characteristics of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기위하여, 얕은 접합을 형성하고 도펀트를 활성화시키는 동시에 열처리에 의한 확산을 최소화하기 위한 RTA 공정으로 접합누설전류를 최소화시키는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention provides a method for manufacturing a semiconductor device that minimizes the junction leakage current in the RTA process to form a shallow junction, activate the dopant and minimize diffusion by heat treatment to solve the above problems of the prior art. There is a purpose.
도 1a 는 반도체기판 상부에 게이트 산화막 및 게이트 전극을 형성한 것을 도시한 단면도.1A is a cross-sectional view of a gate oxide film and a gate electrode formed on a semiconductor substrate.
도 1b 는 소오스와 드레인 접합이 형성됨을 도시한 단면도.1B is a cross-sectional view illustrating that a source and a drain junction are formed.
도 1c 는 접합층 형성후 열처리 실시조건을 도시한 그래프도.Figure 1c is a graph showing the heat treatment execution conditions after forming the bonding layer.
도 2a 는 반도체기판 상부에 게이트 산화막 및 게이트 전극을 형성한 것을 도시한 단면도.FIG. 2A is a cross-sectional view of a gate oxide film and a gate electrode formed on a semiconductor substrate; FIG.
도 2b 는 소오스와 드레인 접합이 형성됨을 도시한 단면도.2B is a cross-sectional view illustrating that a source and a drain junction are formed.
도 2c 는 접합층 형성후 열처리 실시조건을 나타내는 그래프도.Figure 2c is a graph showing the heat treatment execution conditions after forming the bonding layer.
도 2d 는 본 발명에 따른 열처리 조건에 의한 접합깊이를 나타낸 그래프.Figure 2d is a graph showing the junction depth by the heat treatment conditions in accordance with the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>
11, 21 : 반도체기판 13, 33 : 게이트 산화막11, 21: semiconductor substrate 13, 33: gate oxide film
15, 25 : 게이트 전극 17, 27 : 접합층15, 25: gate electrode 17, 27: bonding layer
T : 목적온도 S1 : 목적온도까지 가열하는 시간T: Target temperature S1: Time to heat to target temperature
S2 : 목적온도에서 열처리하는 시간 S3 : 상온으로 냉각시키는 시간S2: Time to heat treatment at the target temperature S3: Time to cool to room temperature
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은, 반도체기판에 게이트 산화막, 게이트 전극 및 접합층을 형성하는 공정과,In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes the steps of forming a gate oxide film, a gate electrode, and a bonding layer on a semiconductor substrate;
상기 접합층의 도펀트를 활성화시키며 열처리에 의한 확산을 최소화시키는 RTA 공정을 실시하되, 목적온도까지의 승온시는 암모니아 가스를 플로우시키고, 목적온도에 도달한 다음부터 상온까지 냉각시에는 암모니아 또는 암모니아/질소 혼합가스를 플로우시키는 공정을 포함하는 것을 특징으로 한다.RTA process for activating the dopant of the bonding layer and minimizing the diffusion by heat treatment, but ammonia gas flows when the temperature rises to the target temperature, and ammonia or ammonia / when cooled to room temperature after reaching the target temperature It characterized in that it comprises a step of flowing a nitrogen mixed gas.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는, 열처리전의 이온주입공정으로 인해 반도체기판에는 격자변형(lattice distortion)과 많은 결함(defect)이 존재하게 되나 질소가스에 비해 반응성이 뛰어난 암모니아 가스 분위기에서는 암모니아의 질소이온이 반도체기판 내로 쉽게 확산되어 들어가면서 도펀트의 확산 경로를 막는 역할을 함으로써 도펀트의 확산을 최소화하여 앝은 접합을 형성함과 동시에 접합누설전류를 최소화하는 것이다.On the other hand, the principle of the present invention to achieve the above object, the lattice distortion (lattice distortion) and a lot of defects (defect) in the semiconductor substrate due to the ion implantation process before heat treatment, but ammonia gas atmosphere that is more reactive than nitrogen gas Nitrogen ion of ammonia is easily diffused into the semiconductor substrate to block the diffusion path of the dopant, thereby minimizing the diffusion of the dopant, forming a thin junction and minimizing the junction leakage current.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c 는 본 발명에 따른 반도체소자의 제조방법을 도시한 도면들로서, 도 2a 는 반도체기판 상부에 게이트 산화막 및 게이트 전극을 형성한 것을 도시한 단면도이고, 도 2b 는 소오스와 드레인 접합이 형성됨을 도시한 단면도이며, 도 2c 는 접합층 형성후 열처리 실시조건을 나타내는 그래프도이다.2A to 2C are diagrams illustrating a method of manufacturing a semiconductor device according to the present invention, and FIG. 2A is a cross-sectional view illustrating a gate oxide film and a gate electrode formed on a semiconductor substrate, and FIG. 2B is a source and drain junction. It is sectional drawing which shows that it is formed, and FIG. 2C is a graph which shows the conditions of heat processing after forming a bonding layer.
먼저, 반도체기판(21) 위에 소자분리 산화막(도시안됨), 게이트산화막(23), 게이트 전극(25)을 순차적으로 형성한다. (도 2a)First, an element isolation oxide film (not shown), a gate oxide film 23, and a gate electrode 25 are sequentially formed on the semiconductor substrate 21. (FIG. 2A)
다음, 노출된 반도체기판(21)에 도펀트를 이온주입하여 접합층(27)을 형성한다.Next, a dopant is implanted into the exposed semiconductor substrate 21 to form a bonding layer 27.
여기서, 상기 도펀트는 p형 불순물을 주입하여 p형 소오스와 드레인 접합을 형성한다. 이때, 상기 도펀트가 B+이온인 경우에는 1 ∼ 50keV로 1×1015 ∼ 1×1016 ions/㎠를 주입하고, 상기 도펀트가 BF2+ 이온인 경우에는 5 ∼ 100keV로 1×1015 ∼ 1×1016 ions/㎠를 주입한다. (도 2b)Here, the dopant implants p-type impurities to form a drain junction with the p-type source. In this case, when the dopant is B + ion, 1 × 10 15 to 1 × 10 16 ions / cm 2 is injected at 1 to 50 keV, and when the dopant is BF 2+ ion, 1 × 10 15 to 1 × 10 16 ions / cm 2 at 5 to 100 keV Inject (FIG. 2B)
그 다음, RTA 공정을 실시하여 상기 도펀트를 활성화시키는 동시에 상기 열처리 공정에 의한 도펀트의 확산을 최소화시킨다.An RTA process is then performed to activate the dopant and to minimize diffusion of the dopant by the heat treatment process.
이때, 상기 RTA 공정은 800 ∼ 1150 ℃ 온도에서 5 ∼ 30초정도 실시한다.At this time, the RTA step is performed at 800 to 1150 ° C. for about 5 to 30 seconds.
상기 RTA 공정이 실시되는 목적온도(T)까지의 승온속도는 30 ∼ 150℃/sec이고, 가열하는 동안(S1)에는 암모니아(NH3)가스를 1 ∼ 5slpm(standard liter per minute)정도의 유량으로 흘려보낸다.The temperature increase rate to the target temperature (T) at which the RTA process is performed is 30 to 150 ° C / sec, and during heating (S1), ammonia (NH3) gas is flowed at a flow rate of 1 to 5 slm (standard liter per minute). Let it flow.
그런 후, 목적온도(T)에서 열처리하는 시간(S2) 및 상온으로 냉각시키는 동안(S3)에는 암모니아 가스 또는 암모니아/질소 혼합가스를 흘려보낸다. 이때, 상기 암모니아 단일가스를 플로우시키는 경우에는 1 ∼ 5slpm, 암모니아/질소 혼합가스를 플로우시키는 경우에는 암모니아 가스 1 ∼ 5slpm, 질소 가스 1 ∼ 5slpm 정도의 유량을 유지시킨다. (도 2c)Thereafter, ammonia gas or ammonia / nitrogen mixed gas flows during the time S2 of heat treatment at the target temperature T and the cooling to room temperature (S3). At this time, when the ammonia single gas is flowed, the flow rate is about 1 to 5 slm, and when the ammonia / nitrogen mixed gas is flowed, the flow rate is about 1 to 5 slm and nitrogen gas is about 1 to 5 slm. (FIG. 2C)
참고로, 도 2d 는 본 발명에 따른 열처리 조건에 의한 접합깊이를 나타낸 그래프로서, 하기와 같은 특징을 나타낸다.For reference, Figure 2d is a graph showing the depth of the joint by the heat treatment conditions according to the present invention, showing the following characteristics.
이온주입 공정으로 인하여 반도체기판(21)에는 격자변형(lattice distortion)과 많은 결함(defect)이 존재하게 되지만, 질소 가스에 비해 반응성이 뛰어난 암모니아 가스 분위기에서는 암모니아의 질소 이온이 반도체기판(21) 내로 쉽게 확산되어 들어가면서 도펀트의 확산경로를 막는 역할을 함으로써 상기 도펀트의 확산을 최소화시켜 얕은 접합을 형성함과 동시에 접합누설전류를 최소화시켜 소자의 전기적 특성을 향상시킨다.Due to the ion implantation process, lattice distortion and many defects exist in the semiconductor substrate 21. However, nitrogen ions of ammonia are introduced into the semiconductor substrate 21 in an ammonia gas atmosphere that is more reactive than nitrogen gas. As it diffuses easily, it blocks the diffusion path of the dopant, thereby minimizing diffusion of the dopant, forming a shallow junction, and minimizing the junction leakage current, thereby improving the electrical characteristics of the device.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 접합층을 형성한 다음에 급속열처리(rapid thermal annealing, 이하 RTA 라 함) 공정시 목적온도까지 가열하는 동안에는 암모니아 가스를 흘려보내고, 목적온도에 도달한 후에는 암모니아 가스 또는 암모니아/질소 혼합가스를 흘려보냄으로써 가열하는 동안 및 열처리온도 유지시 상기 암모니아 가스의 질소이온으로 인한 도펀트의 확산을 최소화시켜 얕은 접합을 형성하는 동시에 접합누설전류를 최소시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming a bonding layer, ammonia gas is caused to flow while heating to a target temperature during a rapid thermal annealing (RTA) process. After reaching the temperature, the ammonia gas or the ammonia / nitrogen mixed gas is flowed to minimize the diffusion of dopants due to nitrogen ions of the ammonia gas during heating and when the heat treatment temperature is maintained to form a shallow junction, while simultaneously forming a junction leakage current. There is an advantage to minimize and thereby improve the characteristics and reliability of the semiconductor device.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970051153A KR100474542B1 (en) | 1997-10-06 | 1997-10-06 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970051153A KR100474542B1 (en) | 1997-10-06 | 1997-10-06 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990030755A true KR19990030755A (en) | 1999-05-06 |
| KR100474542B1 KR100474542B1 (en) | 2005-05-19 |
Family
ID=37302685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970051153A KR100474542B1 (en) | 1997-10-06 | 1997-10-06 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100474542B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100694971B1 (en) * | 2002-07-16 | 2007-03-14 | 주식회사 하이닉스반도체 | Method for forming a Junction region of a semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291181A (en) * | 1992-04-07 | 1993-11-05 | Sharp Corp | Manufacture of semiconductor device |
| JPH0645352A (en) * | 1992-07-24 | 1994-02-18 | Sharp Corp | Manufacture of semiconductor device |
| KR100197120B1 (en) * | 1995-12-22 | 1999-06-15 | 김영환 | Method for manufacturing shallow junction of semiconductor device |
-
1997
- 1997-10-06 KR KR1019970051153A patent/KR100474542B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100694971B1 (en) * | 2002-07-16 | 2007-03-14 | 주식회사 하이닉스반도체 | Method for forming a Junction region of a semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100474542B1 (en) | 2005-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH08181085A (en) | Manufacture of semiconductor device | |
| US5024962A (en) | Method for preventing auto-doping in the fabrication of metal gate CMOS devices | |
| US6475868B1 (en) | Oxygen implantation for reduction of junction capacitance in MOS transistors | |
| KR100474542B1 (en) | Manufacturing method of semiconductor device | |
| US20050142821A1 (en) | Methods of forming halo regions in NMOS transistors | |
| US6423601B1 (en) | Retrograde well structure formation by nitrogen implantation | |
| KR100607317B1 (en) | Method of forming junction part of semiconductor device | |
| JPH0366165A (en) | Diffusion of impurities to semiconductor substrate | |
| JPH0346238A (en) | Manufacture of semiconductor device | |
| JP2586000B2 (en) | Method for manufacturing semiconductor device | |
| KR100334965B1 (en) | Formation method of device of mos field effect transistor | |
| KR19990004563A (en) | Manufacturing method of semiconductor device | |
| KR100671594B1 (en) | Method of manufacturing a transistor having a shallow junction in a semiconductor device | |
| KR100325596B1 (en) | Method of suppressing the formation of crystal defects in silicon wafers after arsenic ion injection | |
| KR100338820B1 (en) | Method For Forming The Source And Drain Of MOS - Transitor | |
| KR100806139B1 (en) | Method for manufacturing semiconductor device using plasma doping | |
| KR100468695B1 (en) | Method for fabricting high performance MOS transistor having channel doping profile to improve short channel effect | |
| KR101128699B1 (en) | Method for manufacturing a semiconductor device | |
| KR20010003691A (en) | Method of forming shallow junction of semiconductor device | |
| KR100422325B1 (en) | Fabricating method of semiconductor device | |
| KR100319873B1 (en) | Low Temperature Activation Method of High Ion Implantation Layer | |
| JPH03265131A (en) | Manufacture of semiconductor device | |
| KR100642386B1 (en) | Method of forming a silicide layer and manufacturing a semiconductor device using the same | |
| JPH06151348A (en) | Manufacture of semiconductor device | |
| JPS6356916A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |