KR100642386B1 - Method of forming a silicide layer and manufacturing a semiconductor device using the same - Google Patents

Abstract

The present invention relates to a method of forming a silicide layer and a method of manufacturing a semiconductor device using the same, wherein ion is implanted into a junction in a state in which a metal layer is first formed so that ion implantation damage to be generated in the semiconductor substrate is generated in the metal layer. By preventing the occurrence of injection damage and by performing an ion implantation process that can improve the thermal stability of the silicide layer before the annealing process, suppressing the occurrence of leakage current in the semiconductor substrate and agglomeration of the silicide layer during the subsequent heat treatment process By preventing agglomeration, process reliability and device electrical characteristics can be improved.

Silicide layer, aggregation phenomenon, leakage current, ion implantation damage, metal buffer layer

Description

Method of forming a silicide layer and a method of manufacturing a semiconductor device using the same {Method of forming a silicide layer and manufacturing a semiconductor device using the same}             

1A and 1B are cross-sectional views of a device for explaining a silicide layer forming method of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a silicide layer forming method according to the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device using the silicide layer forming method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101, 201, 301: semiconductor substrate 102, 303: gate oxide film

103, 304: Gate 104, 312: Source / drain

105, 307: insulating film spacer 106: metal layer

107: salicide layer 202: active region, junction

203: device isolation region 204, 308: metal layer

205 and 309 capping layers 206 and 310 thermally stabilized ion implantation layers

207, 311: high concentration impurity implantation layer 208, 313: silicide layer

209 and 314: silicide layer 302: device isolation film

305: first low concentration ion implantation layer 306: second low concentration ion implantation layer

The present invention relates to a method of forming a silicide layer and a method of manufacturing a semiconductor device using the same, and more particularly, to a method of forming a silicide layer capable of improving thermal stability of the silicide layer and a method of manufacturing a semiconductor device using the same.

Generally, silicide layers are formed on top of junctions such as gates and sources / drains of transistors to reduce connection resistance. The silicide layer is formed by forming a metal layer on the entire upper portion of the semiconductor substrate on which the junction portion is formed, and then performing a heat treatment process while the junction portion and the metal layer react only in the region where the junction portion is formed. The self-aligned silicide layer thus formed is called a salicide layer.

1A and 1B are cross-sectional views of a device for explaining a silicide layer forming method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a transistor including a gate oxide film 102, a gate polysilicon layer 103, a source / drain 104, and an insulating film spacer 105 is formed on a semiconductor substrate 101 through a predetermined process. . Thereafter, the entire surface of the semiconductor substrate 101 including the polysilicon layer 103 and the source / drain 104 is cleaned.

Subsequently, the metal layer 106 is formed over the whole. At this time, the metal layer 106 is formed by depositing TiN or cobalt.

Referring to FIG. 1B, the polysilicon layer 103 and the source / drain 104 are reacted with a metal layer (106 in FIG. 1A) by a rapid thermal annealing process to induce the first phase transition of the silicide, and then the polysilicon layer 103 ) And the metal layer not reacted with the source / drain 104. Subsequently, a second rapid thermal annealing process is performed to obtain a stable silicide phase. As a result, the salicide layer 107 is formed.

In the above method, the source / drain 104 of the NMOS transistor is mainly formed by injecting As. When a large amount of As is injected at a high concentration, the semiconductor substrate 101 is greatly damaged and many defects are generated. This also causes leakage current. In addition, in implementing a shallow junction, an ion implantation apparatus capable of simultaneously performing low energy and high current ion implantation is required. This is inefficient in terms of equipment utilization.

In the case of forming the cobalt silicide layer by a conventional method, agglomeration of silicide occurs by a subsequent thermal process having a high temperature. This increases the contact resistance and changes the gate electrode, polysilicon layer and active resistance. In this way, the agglomeration of the silicide is generated by a subsequent heat treatment process, and after forming the silicide layer in the current semiconductor manufacturing process, it is expected that a lot of facility investment and time will be required to proceed the subsequent heat process at low temperature.

In contrast, the silicide layer forming method and the method of manufacturing a semiconductor device using the same according to the present invention are performed by implanting ions into a junction in a state in which a metal layer is first formed so as to cause ion implantation damage to be generated in the semiconductor substrate. The ion implantation process is performed to prevent the ion implantation damage from occurring and to improve the thermal stability of the silicide layer before the annealing process, thereby suppressing the leakage current generation in the semiconductor substrate and the silicide layer during the subsequent heat treatment process. By preventing agglomeration, the process reliability and device electrical characteristics can be improved.

The silicide layer forming method according to the embodiment of the present invention comprises the steps of forming a metal layer on a semiconductor substrate divided into a junction portion and an insulating portion, forming a thermally stabilized ion implantation layer at the interface of the metal layer and the junction portion, and Forming a silicide layer on the junction by a heat treatment process.

In the above, the metal layer may be formed of Ti, Ta, W or Co.

After forming the metal layer, and before forming the thermal stabilization ion implantation layer, it may further comprise the step of forming a capping layer over the entire. In this case, the capping layer may be formed of a TiN film.

In the ion implantation process, N ₂ ions are implanted, and ions of 5E14 atoms / cm _² to 2E15 atoms / cm _² are implanted with ion implantation energy of 5 KeV to 30 KeV so that ions for thermal stabilization are implanted at the metal layer and the metal layer interface. In addition, in the ion implantation process, it is preferable to inject ions evenly in various directions at an inclination angle of 0 to 30 degrees.

After the thermal stabilization ion implantation layer is formed, the method may further include performing an impurity ion implantation process on the junction before forming the silicide layer.

The silicide layer forming step includes performing a first rapid thermal annealing process to form a metastable silicide layer, removing a metal layer that has not reacted with the junction, and performing a second rapid thermal annealing process to perform a metastable silicide layer. Forming a stable silicide layer.

At this time, the first rapid heat treatment annealing process may be performed for 50 seconds to 90 seconds at 500 ℃ to 580 ℃ in a nitrogen gas atmosphere, the second rapid heat treatment annealing process is carried out for 20 seconds to 50 seconds at 800 ℃ to 850 ℃ can do.

A method of manufacturing a semiconductor device according to an embodiment of the present invention comprises the steps of forming a gate oxide film and a gate on a semiconductor substrate, forming a low concentration ion implantation layer on the semiconductor substrate of the gate edge, Forming an insulating layer spacer on the sidewalls, forming a metal layer over the entire surface, forming a thermally stabilized ion implantation layer on an interface between the metal layer and the gate, and on the crab surfaces of the metal layer and the low concentration ion implantation layer; Forming a high concentration ion implantation layer on the semiconductor substrate at the edge of the insulating film spacer; and forming a silicide layer on the junction part by a heat treatment process.

In the above, the metal layer may be formed of Ti, Ta, W or Co.

After forming the metal layer and before forming the high concentration ion implantation layer, the method may further include forming a capping layer over the whole, and the capping layer may be formed of a TiN film.

The ion implantation process injects N ₂ ions, and the ion implantation process injects ions of 5E14 atoms / cm _² to 2E15 atoms / cm _² at 5KeV to 30 KeV so as to inject ions for thermal stabilization into the metal layer and the metal layer interface. Can be. At this time, in the ion implantation process, it is preferable to inject ions evenly in various directions at an inclination angle of 0 to 30 degrees.

The silicide layer forming step includes performing a first rapid thermal annealing process to form a metastable silicide layer, removing a metal layer not reacted with a gate or a low concentration ion implantation layer, and performing a second rapid thermal annealing process. Thereby forming a metastable silicide layer into a stable silicide layer.

At this time, the first rapid heat treatment annealing process may be performed for 50 seconds to 90 seconds at 500 ℃ to 580 ℃ in a nitrogen gas atmosphere, the second rapid heat treatment annealing process is carried out for 20 seconds to 50 seconds at 800 ℃ to 850 ℃. can do.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

2A to 2E are cross-sectional views illustrating a silicide layer forming method according to the present invention.

Referring to FIG. 2A, various elements (not shown) for forming a semiconductor device such as a transistor or a unit memory cell are formed, and a semiconductor substrate defined by an active region 202 and an isolation region 203 as a junction portion ( The metal layer 204 and the capping layer 205 are formed to form a silicide layer on 201). In this case, before forming the metal layer 204 and the capping layer 205, a cleaning process may be performed to remove the natural oxide film remaining on the active region 202. The cleaning process can be performed for 100 seconds to 200 seconds using the diluted HF solution.

In the above, the metal layer 204 may be formed of Ti, Ta, W, Co, and the like, and preferably formed of Co. In this case, the metal layer 204 is formed of 70 kPa to 150 kPa, the oxygen component is removed from the deposition chamber to prevent abnormal oxidation of the metal layer 204. On the other hand, the capping layer 205 is formed to prevent abnormal oxidation in the annealing process for forming the silicide layer, it is preferable to form a thickness of 200 kV to 250 kV by depositing TiN. In addition, the capping layer 205 is preferably formed within 5 minutes after forming the metal layer 204 without a time delay.

Referring to FIG. 2B, an ion implantation process is performed to make the silicide layer thin and uniform during the annealing process for forming the silicide layer, and to secure the thermal stability of the silicide layer for subsequent thermal processes.

In the ion implantation process, it is preferable to inject N ₂ ions, and in the low energy ion implantation apparatus, 5E14 atoms / cm at an ion implantation energy of 5KeV to 30KeV so that ions are implanted at a high concentration at the interface between the metal layer 204 and the active region 202. It is preferable to implant ions of _² to 2E15 atoms / cm _² . In addition, ions are implanted at an inclination angle of 0 degrees to 30 degrees, and it is preferable not to be limited to one direction but evenly injected from various directions.

As a result, a thermal stabilization ion implantation layer 206 is formed at the interface between the metal layer 204 and the active region 202 by an ion implantation process.

Referring to FIG. 2C, impurities may be injected at a high concentration into the active region 202 according to the type of semiconductor device manufactured in the semiconductor substrate 201. For example, in the case of forming a source / drain having an LDD structure, a high concentration of impurities may be implanted into the active region 202 by an ion implantation process to form a high concentration ion implantation layer. At this time, even if a large amount of impurity ions are implanted at a high concentration, since the metal layer 204 formed on the active region 202 serves as a buffer layer, ion implantation damage due to ion implantation is hardly generated in the semiconductor substrate 201. Generated in the metal layer 204. Therefore, generation of ion implantation damage to the semiconductor substrate 201 can be suppressed as much as possible.

Here, the ion implantation process implants ions at a high concentration of 1E15 atoms / cm ² to 1E15 atoms / cm ² , and since the metal layer 204 is formed, it is preferable to increase the ion implantation energy by about 10%. In addition, an ion implantation process is carried out to have a projection range of about 400 microseconds from the silicon surface so that further diffusion of about 50 microseconds is achieved by subsequent annealing.

On the other hand, when forming a source / drain of an NMOS transistor by an ion implantation process, an N-type high-concentration ion implantation layer is formed by implanting As or P, and a P-type high-concentration ion is implanted when a source / drain of a PMOS transistor is formed An injection layer can be formed.

Referring to FIG. 2D, first rapid thermal annealing is performed to form a silicide layer. At this time, the metastable silicide layer 208 is formed of a metal layer at a temperature of 30 ° C. to 70 ° C. higher than a general case by the thermal stabilization ion implantation layer (206 of FIG. 2C) injected between the metal layer 204 and the active region 202. 204 and the active region 202. In consideration of this, the first rapid heat treatment annealing is preferably performed at 500 ° C. to 580 ° C. for 50 seconds to 90 seconds in a nitrogen gas atmosphere.

Referring to FIG. 2E, after the first rapid thermal annealing, the capping layer (309 in FIG. 2D) and the unreacted metal layer (204 in FIG. 2D) are removed. Subsequently, a secondary rapid thermal annealing process is performed to form a metastable silicide layer (208 in FIG. 2D) as a stable silicide layer 209. At this time, the second rapid thermal annealing process is preferably carried out for 20 seconds to 50 seconds at 800 ℃ to 850 ℃.

As a result, a thin and uniform silicide layer 209 is formed while preventing agglomeration from occurring.

Thereafter, although not shown in the drawing, rapid thermal annealing is performed at 920 ° C. to 990 ° C. for 5 to 10 seconds to form an interlayer insulating film over the whole and to activate impurities implanted at a high concentration.

Hereinafter, an embodiment in which a semiconductor device is manufactured by applying the silicide layer forming method described above to a transistor manufacturing process will be described.

3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device using the silicide layer forming method according to the present invention.

Referring to FIG. 3A, an isolation layer 302 is formed in the isolation region of the silicon substrate 301. Subsequently, the gate oxide film 303 and the polysilicon layer are sequentially formed on the active region of the semiconductor substrate 301, and then the polysilicon layer and the gate oxide film 303 are patterned by an etching process using a gate mask. As a result, the gate 304 made of the polysilicon layer is formed in a predetermined pattern.

Thereafter, a low concentration ion implantation process is performed to form a first low concentration ion implantation layer 305 for forming a source / drain. At this time, the low-concentration ion implantation process to form a first low-concentration ion implantation layer 305 by implanting impurities of 8E14atoms / cm ² to 2E15atoms / cm ² in energy 500eK to 5KeV. In the case of the NMOS transistor, As can be injected, and in the case of the PMOS transistor, BF can be injected. The above conditions are for minimizing ion implantation damage generated in the semiconductor substrate 301 in consideration of diffusion by a subsequent thermal process.

Referring to FIG. 3B, the second low concentration ion implantation layer 306 may be formed by implanting impurities into the lower region of the edge of the first low concentration ion implantation layer 305 and the gate 304 in a low concentration ion implantation process having a predetermined incident angle. Form.

In this case, the first and second low concentration ion implantation layers 305 and 306 are formed at a low concentration and a shallow depth, thereby solving a problem in which a hot carrier effect occurs as the size of the device decreases. This reduces the concentration of local electric fields. In addition, as the length of the gate (channel length) is reduced, the gap between the source and the drain is narrowed, thereby reducing the short channel effect of reducing the threshold voltage of the device.

Referring to FIG. 3C, an insulating film spacer 307 is formed on sidewalls of the gate oxide film 303 and the gate 304 through an entire surface etching process after forming an insulating film over the entire surface.

Referring to FIG. 3D, the metal layer 308 and the capping layer 309 are formed over the entire surface. In this case, before the metal layer 308 and the capping layer 309 are formed, a cleaning process may be performed to remove the natural oxide film remaining on the semiconductor substrate 301. The cleaning process can be performed for 100 seconds to 200 seconds using the diluted HF solution.

In the above, the metal layer 308 may be formed of Ti, Ta, W, Co, and the like, and preferably formed of Co. In this case, the metal layer 308 is formed to 70 ~ 150Å, and remove the oxygen component in the deposition chamber to prevent abnormal oxidation of the metal layer 308. On the other hand, the capping layer 309 is formed in order to prevent the abnormal oxidation in the annealing process for forming the silicide layer, it is preferable to form a thickness of 200 ~ 250Å by depositing TiN. In addition, the capping layer 309 is preferably formed within 5 minutes after the metal layer 308 without a time delay.

Referring to FIG. 3E, while the annealing process for forming the silicide layer is made thin and uniform, the ion implantation process is performed to secure the thermal stability of the silicide layer for the subsequent thermal process.

In the ion implantation process, it is preferable to inject N ₂ ions. In a low energy ion implantation apparatus, 5E14 atoms / cm at an ion implantation energy of 5 KeV to 30 KeV so that ions are implanted at a high concentration at the interface between the metal layer 308 and the semiconductor substrate 301. It is preferable to implant ions of _² to 2E15 atoms / cm _² . In addition, ions are implanted at an inclination angle of 0 degrees to 30 degrees, and it is preferable not to be limited to one direction but evenly injected from various directions.

As a result, a thermally stabilized ion implantation layer 310 is formed at the interface between the metal layer 308 / gate 304 and the metal layer 308 / first low concentration ion implantation layer 305 by an ion implantation process.

Referring to FIG. 3F, the high concentration ion implantation layer 311 is deeper than the first low concentration ion implantation layer 305 through a high concentration ion implantation process using the gate 304 and the insulating film spacer 307 as an ion implantation mask. Form. As a result, the source / drain 312 formed of the high concentration ion implantation layer 311 and the first and second low concentration ion implantation layers 305 and 306 are formed.

At this time, even if a large amount of impurity ions are implanted at a high concentration, since the metal layer 308 formed on the semiconductor substrate 301 serves as a buffer layer, ion implantation damage due to ion implantation is hardly generated in the semiconductor substrate 301. Generated in the metal layer 308. Therefore, the generation of ion implantation damage to the semiconductor substrate 301 can be suppressed as much as possible.

Here, in the ion implantation process, ions are implanted at a high concentration of 1E15 atoms / cm ² to 1E15 atoms / cm ² , and since the metal layer 308 is formed, it is preferable to increase the ion implantation energy by about 10%. In addition, an ion implantation process is carried out to have a projection range of about 400 microseconds from the silicon surface so that further diffusion of about 50 microseconds is achieved by subsequent annealing.

On the other hand, when forming a source / drain of an NMOS transistor by an ion implantation process, an N-type high-concentration ion implantation layer is formed by implanting As or P, and a P-type high-concentration ion is implanted when a source / drain of a PMOS transistor is formed An injection layer can be formed.

Referring to FIG. 3G, first rapid thermal annealing is performed to form a silicide layer. At this time, the thermostable ion implantation layer (310 in FIG. 3E) injected between the metal layer 308 and the semiconductor substrate 301 formed in FIG. 313 is formed at the interface of the metal layer 308 and the gate 304 and the interface of the metal layer 308 and the source / drain 312 in a self-aligning manner. In consideration of this, the first rapid heat treatment annealing is preferably performed at 500 ° C. to 580 ° C. for 50 seconds to 90 seconds in a nitrogen gas atmosphere.

Referring to FIG. 3H, after performing the first rapid thermal annealing, the capping layer (309 in FIG. 3G) and the unreacted metal layer (308 in FIG. 3G) are removed. Subsequently, a secondary rapid thermal annealing process is performed to form a metastable silicide layer (313 in FIG. 3G) as a stable silicide layer 314. At this time, the second rapid thermal annealing process is preferably carried out for 20 seconds to 50 seconds at 800 ℃ to 850 ℃.

As a result, a thin and uniform silicide layer 314 is formed while preventing agglomeration from occurring.

In the above, an example in which the silicide layer forming method of the present invention is applied to a transistor manufacturing process has been described. However, the silicide layer forming method is not limited to a transistor manufacturing process, but may be applied to a process of forming a lower electrode or an upper electrode of a capacitor. It can be applied to any process of forming a silicide layer on top of a conductive layer containing a silicon component.

As described above, the present invention prevents ion implantation damage from occurring in the semiconductor substrate by performing ion implantation at the junction in a state where the metal layer is formed first so that ion implantation damage to the semiconductor substrate is generated in the metal layer, and an annealing process By performing the ion implantation process to improve the thermal stability of the silicide layer, the generation of leakage current in the semiconductor substrate can be suppressed and the agglomeration of the silicide layer can be prevented during the subsequent heat treatment process. The electrical characteristics of the device can be improved.

Claims (21)

Forming a metal layer on the semiconductor substrate divided into a junction and an insulator; Performing a ion implantation process with a predetermined energy and an implantation amount to form a thermally stabilized ion implantation layer only at an interface between the metal layer and the junction; And A silicide layer forming method comprising forming a silicide layer on the junction portion by a heat treatment process. The method of claim 1, The metal layer is a silicide layer forming method formed of Ti, Ta, W or Co. The method of claim 1, wherein after forming the metal layer, before forming the thermal stabilization ion implantation layer, And forming a capping layer over the entire surface. The method of claim 3, wherein And the capping layer is formed of a TiN film. The method of claim 1, The ion implantation process is a silicide layer forming method of implanting N ₂ ions. The method of claim 5, The ion implantation process is a silicide layer forming method of implanting ions of 5E14 atoms / cm _² to 2E15 atoms / cm _² with ion implantation energy of 5 KeV to 30 KeV so that ions for thermal stabilization are injected into the metal layer and the junction interface. The method according to claim 1 or 6, The ion implantation process is a silicide layer forming method of implanting ions evenly in various directions at an inclination angle of 0 to 30 degrees. The method of claim 1, After forming the heat stabilized ion implantation layer, before forming the silicide layer, And performing an impurity ion implantation process on the junction. The method of claim 1, wherein the silicide layer forming step, Performing a first rapid thermal annealing process to form a metastable silicide layer; Removing the metal layer that has not reacted with the junction; And And performing a second rapid heat treatment annealing process to form the metastable silicide layer into a stable silicide layer. The method of claim 9, The first rapid heat treatment annealing process is a method for forming a silicide layer is carried out for 50 seconds to 90 seconds at 500 ℃ to 580 ℃ in a nitrogen gas atmosphere. The method of claim 9, The second rapid heat treatment annealing process is a silicide layer forming method carried out at 800 ℃ to 850 ℃ for 20 seconds to 50 seconds. Forming a gate oxide film and a gate on the semiconductor substrate; Forming a low concentration ion implantation layer in the semiconductor substrate at the gate edge; Forming insulating film spacers on sidewalls of the gate and the gate oxide film; Forming a metal layer on the whole; Forming a thermally stabilized ion implantation layer at an interface between the metal layer and the gate and at an interface between the metal layer and the low concentration ion implantation layer by performing an ion implantation process with a predetermined energy and implantation amount; And Forming a high concentration ion implantation layer on the semiconductor substrate at the edge of the insulating film spacer; Forming a silicide layer on the gate and the low concentration ion implantation layer by a heat treatment process. The method of claim 12, The metal layer is a method of manufacturing a semiconductor device formed of Ti, Ta, W or Co. The method of claim 12, After forming the metal layer, before forming the high concentration ion implantation layer, The method of manufacturing a semiconductor device further comprising the step of forming a capping layer over the entire. The method of claim 14, The capping layer is a manufacturing method of a semiconductor device formed of a TiN film. The method of claim 12, The ion implantation process is a semiconductor device manufacturing method for implanting N ₂ ions. The method of claim 16, In the ion implantation process, 5E14 atoms / cm _² to 2E15 atoms / cm _² of ions are implanted in an amount of 5 KeV to 30 KeV so that ions for thermal stabilization are injected into the interface between the metal layer and the gate and the interface between the metal layer and the low concentration ion implantation layer. A method of manufacturing a semiconductor device which is injected with energy. The method according to claim 12 or 17, The ion implantation process is a semiconductor device manufacturing method for implanting ions evenly in various directions at an inclination angle of 0 to 30 degrees. The method of claim 12, wherein the silicide layer forming step, Performing a first rapid thermal annealing process to form a metastable silicide layer; Removing the metal layer that has not reacted with the gate or the low concentration ion implantation layer; And And forming a metastable silicide layer into a stable silicide layer by performing a second rapid thermal annealing process. The method of claim 19, The first rapid thermal annealing process is a method of manufacturing a semiconductor device performed for 50 seconds to 90 seconds at 500 ℃ to 580 ℃ in a nitrogen gas atmosphere. The method of claim 19, The second rapid thermal annealing process is a method of manufacturing a semiconductor device performed for 20 seconds to 50 seconds at 800 ℃ to 850 ℃.

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