KR19990002492A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19990002492A KR19990002492A KR1019970026109A KR19970026109A KR19990002492A KR 19990002492 A KR19990002492 A KR 19990002492A KR 1019970026109 A KR1019970026109 A KR 1019970026109A KR 19970026109 A KR19970026109 A KR 19970026109A KR 19990002492 A KR19990002492 A KR 19990002492A
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- oxide film
- field oxide
- semiconductor device
- etching
- photoresist
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 20
- 210000003323 beak Anatomy 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000000206 photolithography Methods 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 description 8
- 238000002955 isolation Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 종래의 반도체 소자 제조방법은 사진식각공정에 있어서, 노광시에 필드산화막의 새부리 부분에 의한 단차의 발생으로 광이 입사각과 다른 반사각을 가지고 반사되어 포토레지스트를 과도하게 노광함으로써, 이후에 형성되는 게이트 전극이 염원하는 값보다 작게 형성되어 최종적으로 반도체 소자의 문턱전압값이 설정치 보다 작아져 소자의 특성이 열화 되는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 필드산화막(2)을 증착하는 단계 후에 포토레지스트를 도포 및 패턴을 형성하여 필드산화막의 새부리영역을 선택적으로 식각하는 단계를 더 포함하여 필드산화막(2)의 새부리영역을 식각한 후 반도체 소자의 게이트(3,4)를 제조함으로써, 새부리영역에서 광이 입사각과 다른 반사각을 갖고 반사됨을 방지하여 용이하게 염원하는 특성의 반도체 소자를 제조할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the conventional method for manufacturing a semiconductor device, in a photolithography process, light is reflected at a different angle of incidence than a incident angle due to generation of a step caused by a beak portion of a field oxide film during exposure. Excessive exposure to the gate electrode formed later than the desired value is formed, the threshold voltage value of the semiconductor device is finally smaller than the set value has a problem that the characteristics of the device deteriorated. In view of the above problems, the present invention further includes a step of selectively etching a new beak area of the field oxide film by applying a photoresist and forming a pattern after the step of depositing the field oxide film 2, and the new beak area of the field oxide film 2. After etching, the gates 3 and 4 of the semiconductor device are manufactured, thereby preventing the light from being reflected at the beak region with a reflection angle different from that of the incident angle.
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 기판에 필드산화막을 증착한 후 상기 필드산화막의 에지인 새부리영역을 선택적으로 식각한 후, 게이트산화막 및 다결정실리콘을 증착하고 사진식각 공정으로 게이트를 형성함으로써, 염원하는 문턱전압을 갖는 반도체 소자를 제조하는데 적당하도록 한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, after depositing a field oxide film on a substrate, selectively etching a bird beak region, which is an edge of the field oxide film, depositing a gate oxide film and polycrystalline silicon, and forming a gate by a photolithography process. Thereby, the present invention relates to a semiconductor device manufacturing method which is suitable for manufacturing a semiconductor device having a desired threshold voltage.
일반적으로, 반도체 소자 제조에 있어서, 포토레지스트를 도포하고 마스크를 사용하여 노광 및 식각하는 사진식각공정은 중요한 공정이며, 반도체 소자의 집적도 향상과 소자특성을 결정 짓게 된다. 기판의 상부에 소자가 형성될 영역을 정의하며, 소자간의 분리를 위해 주로 사용되는 필드산화막은 질화막 사이에 노출된 기판에 형성되며, 그 질화막과 기판의 접합면의 일부에도 성장되어 그 필드산화막의 양 끝은 새부리 모양을 갖게 됨은 공지된 바와 같다. 이와 같은 새부리 모양의 끝을 갖는 필드산화막은 사진식각공정에 있어서, 노광시 사용되는 빛을 반사하여 포토레지스트를 과도하게 노광 하게 되어 포토레지스트를 마스크로 하는 식각 공정으로 제조되는 게이트가 작아져 단채널효과로 인해 문턱전압이 낮아지게 된다. 즉 할래이션(halation)이 발생하여 염원하는 문턱전압값을 갖는 게이트의 제조가 용이하지 않게 되며, 이와 같은 종래의 반도체 소자 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, in the fabrication of semiconductor devices, a photolithography process of applying photoresist and exposing and etching using a mask is an important process, and the integration of semiconductor devices is improved and device characteristics are determined. A field oxide film, which is mainly used for isolation between devices, is formed on a substrate exposed between nitride films. The field oxide film is formed on a substrate exposed between nitride films, and is also grown on a part of a junction surface of the nitride film and the substrate, Both ends are known to have a beak shape. In the photolithography process, the field oxide film having the beak-shaped tip reflects the light used during the exposure and excessively exposes the photoresist, so that the gate manufactured by the etching process using the photoresist as a mask becomes small and thus short-channel. The effect is to lower the threshold voltage. That is, halation occurs, so that the manufacture of a gate having a desired threshold voltage value is not easy, and such a conventional semiconductor device manufacturing method will be described in detail with reference to the accompanying drawings.
도1a 내지 도1d는 종래 반도체 소자 제조방법 일실시예의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 성장시키는 단계(도1a)와; 상기 기판(1)과 필드산화막(2)의 상부전면에 게이트산화막(3)과 다결정실리콘(4)을 순차적으로 증착하는 단계(도1b)와; 상기 다결정실리콘(4)의 상부에 포토레지스트(P/R)를 도포하고 노광 하는 단계(도1c)와; 상기 포토레지스트(P/R)를 식각마스크로 하는 선택적 식각으로 상기 다결정실리콘(4)을 식각하여 게이트 전극(5)을 형성하는 단계(도1d)를 포함하여 구성된다.1A to 1D are cross-sectional views of a manufacturing process of one embodiment of a conventional semiconductor device manufacturing method, as shown in this step, by growing a field oxide film 2 on top of a substrate 1 (FIG. 1A); Sequentially depositing a gate oxide film 3 and a polysilicon 4 on the upper surface of the substrate 1 and the field oxide film 2 (FIG. 1B); Applying and exposing photoresist (P / R) on top of the polysilicon (4) (FIG. 1C); And etching the polysilicon 4 to form a gate electrode 5 by selective etching using the photoresist P / R as an etching mask (FIG. 1D).
이하, 상기와 같이 구성된 종래 반도체 소자 제조방법을 좀 더 상세히 설명한다.Hereinafter, a conventional semiconductor device manufacturing method configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이, 기판(1)의 상부에 패드산화막과 질화막을 증착하고, 기판(1)의 상부를 소자가 형성될 액티브영역과 각 액티브영역을 분리하는 분리영역을 설정하여 분리영역에 증착된 상기 질화막 및 패드산화막을 식각하여 기판(1)의 분리영역을 노출시킨다. 상기 노출된 분리영역을 산화시켜 필드산화막(2)을 형성한다. 이와 같은 공정을 로코스(LOCOS)공정이라고 하며, 상기 필드산화막(2)은 성장하는 과정에서 질화막과 기판(1)의 사이에 증착된 패드산화막 측으로도 성장하여 결국 기판(1)의 상부와 접속되는 필드산화막(2)의 끝 부분은 새부리 모양을 갖게 된다.First, as shown in FIG. 1A, a pad oxide film and a nitride film are deposited on the substrate 1, and the active region where the device is to be formed is separated from the active region on which the device 1 is formed. The nitride layer and the pad oxide layer deposited in the isolation region are etched to expose the isolation region of the substrate 1. The exposed isolation region is oxidized to form a field oxide film 2. Such a process is called a LOCOS process, and the field oxide film 2 also grows toward the pad oxide film deposited between the nitride film and the substrate 1 during the growth process and eventually connects to the upper portion of the substrate 1. The end portion of the field oxide film 2 to be formed has a beak shape.
그 다음, 도1b에 도시한 바와 같이 상기 기판(1)과 필드산화막(2)의 상부에 게이트산화막(3)과 다결정실리콘(4)을 순차적으로 증착한다. 이는 다결정실리콘 게이트 전극과 게이트산화막을 포함하는 반도체 소자의 게이트를 형성하기 위함이다.Next, as shown in FIG. 1B, the gate oxide film 3 and the polysilicon 4 are sequentially deposited on the substrate 1 and the field oxide film 2. This is to form a gate of a semiconductor device including a polysilicon gate electrode and a gate oxide film.
그 다음, 도1c에 도시한 바와 같이 상기 다결정실리콘(4)의 상부에 포토레지스트(P/R)를 도포하고 노광 하여 게이트 패턴을 형성한다. 도1c에는 설명의 편이를 위해 이미 게이트 패턴이 형성된 포토레지스트(P/R)를 도시하였으나, 실제로는 상기 다결정실리콘(4)의 상부전면에 포토레지스트(P/R)를 도포하고, 그 포토레지스트(P/R)를 구워 마스크를 사용하여 노광 한다. 이에 따라 광에 노출된 포토레지스트(P/R)와 노출되지 않은 포토레지스트(P/R)의 성질이 다르게 되고, 이 성질의 차에 의해 선택적인 식각을 하며, 식각되지 않은 포토레지스트(P/R)를 식각마스크로 하여 다결정실리콘(4)을 식각하게 된다. 사진식각공정에서 노광시에 상기 필드산화막(2)의 새부리의 영향으로 그 상부에 증착되는 게이트산화막(3)과 다결정실리콘(4)은 선형의 단차를 갖게 되며, 그 선형 단차구간에서 광은 입사각과 다른 반사각을 갖으며 반사된다. 이에 따라 노광하지 않을 포토레지스트(P/R)의 일부분, 즉 게이트 패턴에 반사광이 인가된다.Then, as shown in FIG. 1C, a photoresist (P / R) is applied and exposed on the polycrystalline silicon 4 to form a gate pattern. Although FIG. 1C shows a photoresist P / R having a gate pattern already formed for ease of explanation, in practice, a photoresist P / R is coated on the upper surface of the polysilicon 4, and the photoresist is formed. (P / R) is baked and exposed using a mask. As a result, the properties of the photoresist (P / R) exposed to the light and the photoresist (P / R) not exposed to the light are different, and selective etching is performed according to the difference of the properties. The polysilicon 4 is etched using R) as an etching mask. During exposure in the photolithography process, the gate oxide film 3 and the polysilicon 4 deposited thereon have a linear step due to the influence of the beak of the field oxide film 2, and light is incident at the linear stepped section. Reflected at different angles of reflection. Accordingly, reflected light is applied to a portion of the photoresist P / R that is not to be exposed, that is, the gate pattern.
그 다음, 도1d에 도시한 바와 같이 상기 식각되지 않은 포토레지스트(P/R)를 식각 마스크로 하는 식각공정으로 다결정실리콘(4)을 부분적으로 식각하여 게이트 전극(5)을 형성하며, 이때 형성되는 게이트 전극(5)은 상기 선형 단차부분의 반사광에 따라 과도하게 노광된 포토레지스트(P/R)의 영향으로 염원하는 값보다 작게 형성되며, 이에 따라 그 게이트 전극(5)을 이용하는 반도체 소자의 문턱전압값이 낮아지게 된다.Next, as shown in FIG. 1D, the gate electrode 5 is formed by partially etching the polysilicon 4 by an etching process using the non-etched photoresist P / R as an etching mask. The gate electrode 5 is formed to be smaller than the desired value under the influence of the photoresist P / R which is excessively exposed according to the reflected light of the linear stepped portion, and thus the semiconductor device using the gate electrode 5 The threshold voltage value is lowered.
상기한 바와 같이 종래의 반도체 소자 제조방법은 사진식각공정에 있어서, 노광시에 필드산화막의 새부리 부분에의한 단차의 발생으로 광이 입사각과 다른 반사각을 가지고 반사되어 포토레지스트를 과도하게 노광함으로써, 이후에 형성되는 게이트 전극이 염원하는 값보다 작게 형성되어 최종적으로 반도체 소자의 문턱전압값이 설정치보다 작아져 소자의 특성이 열화되는 문제점이 있었다.As described above, in the conventional method of manufacturing a semiconductor device, in the photolithography process, light is reflected at an angle different from the incident angle due to the generation of a step by the beak portion of the field oxide film, resulting in excessive exposure of the photoresist. Thereafter, the gate electrode formed is smaller than the desired value, and finally, the threshold voltage value of the semiconductor device is smaller than the set value, thereby deteriorating characteristics of the device.
이와 같은 문제점을 감안한 본 발명은 반도체 소자의 게이트 형성시 필드 산화막의 새부리를 식각하여 난반사에 의한 게이트의 과도노광을 방지하는 반도체 소자 제조방법의 제공에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for fabricating a semiconductor device which prevents overexposure of a gate due to diffuse reflection by etching the beak of the field oxide film during gate formation of the semiconductor device.
도1a 내지 도1d는 종래 반도체 소자 제조공정 수순단면도.1A to 1D are cross-sectional views of a conventional semiconductor device manufacturing process.
도2a 내지 도2e는 본 발명에 의한 반도체 소자 제조공정 수순단면도.2A to 2E are cross-sectional views of a semiconductor device manufacturing process according to the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판2:필드산화막1: Substrate 2: Field oxide film
3:게이트산화막4:다결정실리콘3: gate oxide film 4: polycrystalline silicon
상기와 같은 목적은 필드산화막을 형성하여 반도체 기판상에 소자가 형성될 영역을 정의 한 후, 상기 필드산화막의 상부에 포토레지스트를 도포 및 패턴을 형성하고, 상기 필드산화막의 새부리영역을 선택적으로 식각함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to form a field oxide film to define a region on which a device is to be formed on a semiconductor substrate, and then apply a photoresist and a pattern on the field oxide film, and selectively etch the bird's beak region of the field oxide film. This is achieved by, when described in detail with reference to the accompanying drawings, the present invention as follows.
도2a 내지 도2e는 본 발명에 의한 반도체 소자 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 필드산화막(2)을 성장시키는 단계(도2a)와; 상기 기판(1)과 필드산화막(2)의 상부에 포토레지스트(P/R)를 도포하고 패턴을 형성하여 상기 필드산화막(2)의 에지부분인 새부리영역을 노출시키고, 상기 패턴이 형성된 포토레지스트(P/R)를 식각 마스크로 하는 식각공정으로 상기 필드산화막(2)의 새부리영역을 식각하는 단계(도2b)와; 상기 기판(1)과 필드산화막(2)의 상부전면에 게이트산화막(3)과 다결정실리콘(4)을 순차적으로 증착하는 단계(도2c)와; 상기 다결정실리콘(4)의 상부에 포토레지스트(P/R)를 도포하고 패턴을 형성하는 단계(도2d)와; 상기 포토레지스트(P/R)를 식각마스크로 하는 선택적 식각으로 상기 다결정실리콘(4)을 식각하다 게이트 전극(5)을 형성하는 단계(도2e)를 포함하여 구성된다.FIG. 2A to FIG. 2E are cross-sectional views of a semiconductor device manufacturing process according to the present invention, as shown in FIG. A photoresist (P / R) is coated on the substrate 1 and the field oxide film 2 and a pattern is formed to expose a beak region, which is an edge portion of the field oxide film 2, and the patterned photoresist. Etching the beak region of the field oxide film 2 by an etching process using (P / R) as an etching mask (FIG. 2B); Sequentially depositing a gate oxide film 3 and a polysilicon 4 on the upper surface of the substrate 1 and the field oxide film 2 (FIG. 2C); Applying photoresist (P / R) on top of the polysilicon 4 and forming a pattern (FIG. 2D); And etching the polysilicon 4 by selective etching using the photoresist P / R as an etching mask to form a gate electrode 5 (FIG. 2E).
이하, 상기와 같은 구성의 본 발명을 좀더 상세히 설명한다.Hereinafter, the present invention of the configuration as described above in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)의 상부에 패드산화막 및 질화막(도면생략)을 순차적으로 증착한 후, 패턴을 형성하여 기판(1)의 일부를 노출시킨 후, 그 노출된 기판(1)에 필드산화막(2)을 성장시키며, 패드산화막 및 질화막을 식각한다.First, as shown in FIG. 2A, a pad oxide film and a nitride film (not shown) are sequentially deposited on the substrate 1, and then a pattern is formed to expose a portion of the substrate 1, and then the exposed substrate. The field oxide film 2 is grown in (1), and the pad oxide film and the nitride film are etched.
그 다음, 도2b에 도시한 바와 같이, 상기 필드산화막(2)이 형성된 기판(1)의 상부에 포토레지스트(P/R)를 도포하고, 노광 하여 패턴을 형성한 후, 그 포토레지스트(P/R)를 식각하여 상기 필드산화막(2)의 에지인 새부리영역을 노출시킨다. 상기 노출된 필드산화막(2)의 새부리영역을 상기 패턴이 형성된 포토레지스트(P/R)를 식각 마스크로 하는 식각공정으로 식각한다.Then, as shown in Fig. 2B, a photoresist P / R is applied on the substrate 1 on which the field oxide film 2 is formed, exposed, and a pattern is formed, and then the photoresist P is formed. / R) is etched to expose the beak region that is the edge of the field oxide film 2. The new beak region of the exposed field oxide film 2 is etched by an etching process using the photoresist P / R having the pattern as an etching mask.
이때, 식각에 사용되는 식각장비는 TEL사와 LAM사의 알에프 스플릿 파워를 이용하는 산화막 식각장비를 사용하며, 압력은 500~700mTorr, 전력은 400~600W를 사용하는 공정조건에서 식각 가스로 CHF3, CF4, Ar가스를 사용한다. 이와 같은 방식으로 필드산화막(2) 새부리 영역이 식각된 부분은 수직단면을 갖게 된다.The etching device used for etching makes use of the oxide etching equipment using the RF split power company TEL Inc. LAM, the pressure is 500 ~ 700mTorr, power is CHF 3, CF 4 as an etching gas in the process conditions using the 400 ~ 600W Ar gas is used. In this manner, the portion where the field oxide film 2 beak region is etched has a vertical cross section.
그 다음, 도2c에 도시한 바와 같이, 상기 필드산화막(2)이 형성된 기판(1)의 전면에 게이트산화막(3)과 다결정실리콘(4)을 소정의 두께를 갖도록 순차적으로 증착한다.Then, as shown in FIG. 2C, the gate oxide film 3 and the polysilicon 4 are sequentially deposited on the entire surface of the substrate 1 on which the field oxide film 2 is formed to have a predetermined thickness.
그 다음, 도2d에 도시한 바와 같이, 포토레지스트(P/R)를 도포 및 게이트 패턴을 형성하고, 노광 한다. 이때, 광은 입사각과 동일한 반사각을 갖도록 반사되며, 이에 따라 포토레지스트(P/R) 패턴에 영향을 주지 않게 된다.Then, as shown in Fig. 2D, photoresist P / R is applied, a gate pattern is formed, and exposed. At this time, the light is reflected to have the same reflection angle as the incident angle, and thus does not affect the photoresist (P / R) pattern.
그 다음, 도2e에 도시한 바와 같이 상기 포토레지스트(P/R)를 식각 마스크로 하는 식각공정으로 상기 다결정실리콘(4)과 게이트산화막(3)을 식각하여 게이트를 형성하게 된다.Next, as shown in FIG. 2E, a gate is formed by etching the polysilicon 4 and the gate oxide layer 3 by an etching process using the photoresist P / R as an etching mask.
상기한 바와 같이 본 발명 반도체 소자 제조방법은 필드산화막의 새부리영역을 식각한 후 반도체 소자의 게이트를 제조함으로써, 새부리영역에서 광이 입사각과 다른 반사각을 갖고 반사됨을 방지하여 용이하게 염원하는 특성의 반도체 소자를 제조할 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention etches a new beak region of a field oxide film and then manufactures a gate of the semiconductor device, thereby preventing the light from being reflected at a different angle from the incident angle in the new beak region, thereby easily desired. There is an effect that can produce a device.
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