KR100198671B1 - Method of forming buried layer of bipolar transistor - Google Patents
Method of forming buried layer of bipolar transistor Download PDFInfo
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- KR100198671B1 KR100198671B1 KR1019960056445A KR19960056445A KR100198671B1 KR 100198671 B1 KR100198671 B1 KR 100198671B1 KR 1019960056445 A KR1019960056445 A KR 1019960056445A KR 19960056445 A KR19960056445 A KR 19960056445A KR 100198671 B1 KR100198671 B1 KR 100198671B1
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- Prior art keywords
- layer
- forming
- buried layer
- bipolar transistor
- type substrate
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
Abstract
매몰층의 정확한 한정과 결함을 방지하기에 적당한 바이폴라 트랜지스터의 매몰층 형성방법에 대한 것으로써 이와 같은 바이폴라 트랜지스터의 매몰층 형성방법은 제1도전형 기판 상에 소정 두께의 산화막과 질화막을 차례로 형성하는 단계, 제1도전형 기판의 소정 부분이 드러나도록 산화막과 질화막을 식각하는 단계, 드러난 제1도전형 기판에 제2도전형 불순물 영역을 형성하는 단계, 산화막과 질화막을 제거하는 단계, 전면에 제1도전형 에피층을 형성하는 단계를 포함하여 형성한다.A method of forming a buried layer of a bipolar transistor suitable for precisely defining a buried layer and preventing defects, wherein a buried layer of a bipolar transistor is formed by sequentially forming an oxide layer and a nitride layer of a predetermined thickness on a first conductivity type substrate Etching the oxide film and the nitride film so that a predetermined portion of the first conductive type substrate is exposed, forming a second conductive type impurity region in the exposed first conductive type substrate, removing the oxide film and the nitride film, 1 < / RTI > conductive epitaxial layer.
Description
본 발명은 바이폴라 트랜지스터에 대한 것으로 특히 매몰층의 정확한 한정과 결함을 방지하기에 적당한 바이폴라 트랜지스터의 매몰층 형성방법에 대한 것이다.The present invention is directed to a bipolar transistor, and in particular to a method for forming a buried layer of a bipolar transistor suitable for precise definition and prevention of defects in the buried layer.
이하 첨부 도면을 참조하여 종래의 바이폴라 트랜지스터의 매몰층 형성방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of forming a buried layer of a conventional bipolar transistor will be described with reference to the accompanying drawings.
제1도a 내지 1d는 종래의 바이폴라 트랜지스터의 매몰층 형성방법을 나타낸 공정단면도이다.1 (a) to 1 (d) are process cross-sectional views showing a buried layer forming method of a conventional bipolar transistor.
먼저 제1도a에 도시한 바와 같이 P형 기판(1)에 실리콘 산화막(2)을 7000Å 정도의 두께를 갖도록 증착한다.First, as shown in FIG. 1A, a silicon oxide film 2 is deposited on the P-type substrate 1 to have a thickness of about 7000 ANGSTROM.
다음으로 제1도b에 도시한 바와 같이 실리콘 산화막(2)에 감광막(3)을 도포한후 노광 및 현상 공정으로 선택적으로 패터닝 한후 패터닝된 감광막(3)을 마스크로 이방성 식각하여 상기 실리콘 산화막(2)을 제거한다. 이때 산화막의 두께가 너무 두꺼워서 식각한 후에 'b' 만큼 언더컷이 발생한다.Next, as shown in FIG. 1 (b), the silicon oxide film 2 is coated with a photoresist film 3, selectively patterned by an exposure and development process, and then anisotropically etched using the patterned photoresist film 3 as a mask to form the silicon oxide film 2) is removed. At this time, since the thickness of the oxide film is too thick, an undercut occurs by 'b' after etching.
그리고 제1도c에 도시한 바와 같이 감광막(3)을 제거한 후 실리콘 산화막(2)을 마스크로 이용하여 드러난 P형 기판(1)에 N+ 이온을 주입하고, 이후에 열 확산 공정을 통해 N+ 매몰층(4)을 형성한다.Then, as shown in FIG. 1C, N + ions are implanted into the exposed P-type substrate 1 using the silicon oxide film 2 as a mask after the photoresist film 3 is removed. Then, N + To form a layer (4).
그리고 제1도d에 도시한 바와 같이 상기 실리콘 산화막(2)을 제거한 후 전면에 N형 에피층(5)을 형성한다.Then, as shown in FIG. 1 (d), after the silicon oxide film 2 is removed, an N-type epitaxial layer 5 is formed on the entire surface.
다음에 도면에는 도시되지 않았지만 상기 N형 에피층(5)의 소정 영역에 베이스 영역을 형성하고 상기 베이스 영역의 소정 염역 내에 에미터 영역을 형성하고 상기 N형 에피층(5)의 소정 영역에 콜렉터 영역을 형성하여 바이폴라 트랜지스터를 제조한다.Although not shown in the figure, a base region is formed in a predetermined region of the N-type epitaxial layer 5, an emitter region is formed in a predetermined region of the base region, a collector region is formed in a predetermined region of the N-type epitaxial layer 5, Thereby forming a bipolar transistor.
이와 같이 제조되는 종래의 바이폴라 트랜지스터의 매몰층 형성방법은 다음과 같은 문제가 있다.The buried layer forming method of the conventional bipolar transistor thus manufactured has the following problems.
첫째, 초기 산화막이 너무 두꺼워서 매몰층의 사진 식각후에도 언더 컷이 너무 커서 매몰층의 정착한 한정이 불가능하다는 공정의 어려움이 있다.First, since the initial oxide film is too thick, the undercut is too large even after photolithography of the buried layer, so that it is difficult to process the buried layer.
둘째, 확산 공정시 전체 산화막이 너무 두꺼워져서 이후에 사진 식각시 공정 마진이 줄어든다.Second, the entire oxide film becomes too thick during the diffusion process, which reduces the process margin in photolithography.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로써 고집적 소자에 적당한 바이폴라 트랜지스터의 매몰층 형성방법을 제공하는 데 그 목적이 있다.It is an object of the present invention to provide a method of forming a buried layer of a bipolar transistor suitable for a highly integrated device.
제1도a 내지 1d은 종래 바이폴라 트랜지스터의 매몰층 형성방법을 나타낸 공정단면도.FIGS. 1A to 1D are process cross-sectional views illustrating a buried layer formation method of a conventional bipolar transistor.
제2도a 내지 2e는 본 발명 바이폴라 트랜지스터의 매몰층 형성방법을 나타낸 공정단면도.FIGS. 2A to 2E are process sectional views showing a method for forming a buried layer of a bipolar transistor according to the present invention. FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
21 : P형 기판 22 : 실리콘 산화막21: P-type substrate 22: Silicon oxide film
23 : 질화막 24 : 감광막23: nitride film 24: photosensitive film
25 : N+ 매몰층 26 : N형 에피층25: N + buried layer 26: N-type epitaxial layer
상기와 같은 목적을 달성하기 위한 본 발명 바이폴라 트랜지스터의 매몰층은 제1도전형 기판 상에 소정 두께의 산화막과 질화막을 차례로 형성하는 단계, 상기 제1도전형 기판의 소정 부분이 드러나도록 산화막과 질화막을 식각하는 단계, 상기 드러난 제1도전형 기판에 제2도전형 불순물 영역을 형성하는 단계, 상기 산화막과 질화막을 제거하는 단계, 상기 전면에 제1도전형 에피층을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a buried layer of a bipolar transistor, comprising: sequentially forming an oxide layer and a nitride layer of a predetermined thickness on a first conductive type substrate; forming an oxide layer and a nitride layer Forming a second conductive type impurity region on the exposed first conductive type substrate, removing the oxide film and the nitride film, and forming a first conductive type epilayer on the front surface .
이하 첨부 도면을 참조하여 본 발명 바이폴라 트랜지스터의 매몰층 형성방법에 대하여 설명하면 다음과 같다.Hereinafter, a method of forming a buried layer of a bipolar transistor according to the present invention will be described with reference to the accompanying drawings.
제2도a 내지 2e는 본 발명 바이폴라 트랜지스터의 매몰층 형성방법을 나타낸 공정단면도이다.FIGS. 2A to 2E are process sectional views showing a buried layer forming method of a bipolar transistor according to the present invention.
먼저 본 발명 바이폴라 트랜지스터의 매몰층 형성방법은 제2도a에 도시한 바와 같이 P형 기판(21)에 열산화 공정이나 화학 기상 증착법(CVD)으로 1000Å 정도 두께의 실리론 산화막(22)을 형성하고, 또한 실리콘 산화막(22) 전면에1000Å 정도 두께의 질화막(2))을 형성한다.First, as shown in FIG. 2 (a), a buried layer of a bipolar transistor of the present invention is formed by forming a silylon oxide film 22 having a thickness of about 1000 Å on a P-type substrate 21 by a thermal oxidation process or a chemical vapor deposition And a nitride film (2) having a thickness of about 1000 Å on the entire surface of the silicon oxide film 22).
다음으로 제2도b에 도시한 바와 같이 전면에 감광막(24)을 도포한 후 노광 및 현상 공정으로 소정부분의 감장막(24)을 선택적으로 패터닝한 후 패터닝된 감광막(24)을 마스크로 이용하여 상기 질화막(23)과 실리콘 산화막(22)을 사진 식각으로 이방성 식각한다. 이때 단차는 'a' 만큼 적게 형성된다.Next, as shown in FIG. 2 (b), a photoresist layer 24 is coated on the entire surface, and then a predetermined portion of the passivation layer 24 is selectively patterned by an exposure and development process. Then, the patterned photoresist layer 24 is used as a mask The nitride film 23 and the silicon oxide film 22 are anisotropically etched by photolithography. At this time, the step is formed as small as 'a'.
이어서 제2도c에 도시한 바와 같이 감광막(24)을 제거한 후 질화막(2))과 실리콘 산화막(22)을 마스크로 이용하여 드러난 P형 기판(21)에 N+ 이온을 주입한다.Subsequently, as shown in FIG. 2C, N + ions are implanted into the P-type substrate 21 exposed by using the nitride film 2 and the silicon oxide film 22 as a mask after removing the photoresist film 24.
이후에 제2도d에 도시한 바와 같이 열 확산 공정으로 N+ 매몰층(25)을 형성한다.Then, an N + buried layer 25 is formed by a thermal diffusion process as shown in FIG. 2 (d).
다음에 제2도e에 도시한 바와 같이 상기 질화막(23)과 실리콘 산화막(22)을 제거한 후에 전면에 N형 에피층(26)을 형성한다.Next, as shown in FIG. 2E, after the nitride film 23 and the silicon oxide film 22 are removed, an N-type epitaxial layer 26 is formed on the entire surface.
그리고 도면에는 도시하지 않았지만 상기 N형 에피층(26)의 소정 영역에 베이스 영역을 형성하고 상기 베이스 영역의 소정 영역 내에 에미터 영역을 형성하고 상기 N형 에피층(26)의 소정 영역에 콜렉터 영역을 형성하여 바이폴라 트랜지스터를 제조한다.Although not shown in the figure, a base region is formed in a predetermined region of the N-type epitaxial layer 26, an emitter region is formed in a predetermined region of the base region, and a collector region Thereby forming a bipolar transistor.
상기와 같이 제조되는 바이폴라 트랜지스터의 매몰층 형성방법은 다음과 같은 효과가 있다.The method of forming the buried layer of the bipolar transistor as described above has the following effects.
첫째, 질화막과 실리콘 산화막을 얇게 증착함에 따라 사진 식각 공정시 언더컷이 줄어들어 정확한 얼라인 공정이 가능하다.First, by thinly depositing nitride and silicon oxide films, the undercutting is reduced during the photolithography process, and a precise alignment process is possible.
둘째, 언더 컷이 줄어들게되므로 크리티컬(Critical)한 디자인을 요구하는 소자를 제조하기에 적당하다.Second, since the undercut is reduced, it is suitable for manufacturing a device requiring a critical design.
Claims (4)
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| KR1019960056445A KR100198671B1 (en) | 1996-11-22 | 1996-11-22 | Method of forming buried layer of bipolar transistor |
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| KR1019960056445A KR100198671B1 (en) | 1996-11-22 | 1996-11-22 | Method of forming buried layer of bipolar transistor |
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