KR19980069853A - Plasma display device and driving method thereof - Google Patents

Abstract

An object of the present invention is to realize a plasma display device and a driving method thereof capable of preventing a decrease in display contrast caused by priming discharge and reducing power consumption.

The first, second and third electrodes 51, 52o and 52e are alternately arranged in parallel on the first substrate, and the fourth electrode 53 is orthogonal to the first electrode on the first or second substrate. Plasma display panel, the first electrode selection driving means 62, 63, the second electrode driving means 61o, and the third electrode driving means 61e are arranged, and the first electrode and the second electrode are provided. The interlaced display which alternately repeats the light emission display is performed in the first display cell 55 formed and the second display cell 56 formed of the first electrode and the third electrode, and during the reset period, the second and third A voltage is applied between the electrodes to cause priming discharge in the third cell formed by the second electrode and the third electrode.

Description

Plasma display device and driving method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for driving a display panel constituted by a set of cells as display elements having a memory function, and in particular, an apparatus for performing interlaced display in an AC (Plasma Display Panel) plasma display panel. And a driving method thereof.

The AC PDP sustains discharge by displaying voltage waveforms alternately on two sustain electrodes to display light emission. One discharge ends immediately after pulse application from several microseconds. The ions that are electrostatic charges generated by the discharge accumulate on the surface of the insulating layer on the electrode to which the negative voltage is applied, and the electrons that are negatively charged on the surface of the insulating layer on the electrode to which the positive voltage is applied. Accumulate.

Therefore, after first discharging with a pulse of high voltage (write voltage) (write pulse) to generate wall charges, a pulse (maintenance pulse or sustain discharge pulse) of a voltage (maintenance voltage or sustain discharge voltage) lower than the previous time with different polarity is generated. Is applied, the previously accumulated wall charges are superimposed so that the voltage to the discharge space becomes large and discharge starts beyond the threshold of the discharge voltage. That is, a cell which has once been subjected to write discharge to generate wall charge has a characteristic that the discharge is continued by alternately applying sustain pulses in reverse polarity thereafter. This is called memory effect, or memory function. In general, an AC PDP performs display using this memory effect.

In the AC type PDP which performs full color display, the 3-electrode structure using surface discharge is generally used. Furthermore, even in this three-electrode type, the third electrode may be formed on a substrate on which the first electrode and the second electrode which perform the sustain discharge are arranged, and may be arranged on another substrate to face each other. Further, even when the above three kinds of electrodes are formed on the same substrate, the third electrode may be disposed on two electrodes for sustain discharge, and the third electrode may be disposed below the third electrode. In addition, there are cases where visible light generated from a phosphor is transmitted through the phosphor (transmissive type), and reflection from the phosphor is seen (reflective type). In addition, in the cell that discharges, spatial coupling with adjacent cells is blocked by barriers (ribs, barriers). These barriers are provided in all directions and completely sealed to surround the discharge cells, or are provided only in one direction, and the other is the bond is cut by the optimization of the gap (distance) between the electrodes.

In the present specification, a panel is provided in which a third electrode is formed on a substrate opposite to the substrate of the electrode for sustain discharge, and the barrier is perpendicular to the first electrode and the second electrode, and parallel to the third electrode. Will be described based on an example of a reflection type, which is formed of only a single electrode and a part of the sustain electrode is constituted by a transparent electrode.

As the above-described three-electrode surface discharge type PDP, it is known that a schematic plan view is shown in FIG. 2 is a schematic sectional drawing of these panels, and FIG. 3 is a schematic sectional drawing of a horizontal direction similarly.

The panel is composed of two glass substrates 21 and 28. The first substrate 21 includes first and second electrodes (X electrode, Y electrode) 11 and 12 which are parallel sustain electrodes, and these electrodes are transparent electrodes 22a and 22b and bus electrodes 23a, It is comprised by 23b). The transparent electrode transmits the reflected light from the phosphor, and the bus electrode is made of metal for the purpose of preventing voltage drop caused by the electrode resistance. Furthermore, these are covered with a dielectric layer 24, and an MgO (magnesium oxide) film 25 is formed on the discharge surface as a protective film. Moreover, the 3rd electrode (address electrode) 13 is formed in the form orthogonal to the sustain electrodes 11 and 12 in the 2nd board | substrate 28 which opposes the said 1st glass substrate 21. As shown in FIG. In addition, a barrier 14 is formed between the address electrodes 13, and a phosphor 27 having red, green, and blue light emission characteristics is formed between the barriers so as to cover the address electrodes 13. Two glass substrates are assembled in such a manner that the ridge line 14 of the barrier and the MgO surface 25 are in close contact with each other.

4 is a schematic block diagram showing a peripheral circuit for interlacing the PDP shown in FIGS. 1, 2 and 3. Each address electrode 13 is connected to the address driver 105, and an address pulse at the time of address discharge is applied by the address driver. The Y electrode 11 is individually connected to the scan driver 102. The scan driver 102 is divided into blocks for driving the odd Y electrode and for driving the even Y electrode, and a Y common driver for generating sustain discharge pulses and applying them to the Y electrode is also the first and second Y common drivers 103a. , 103b). Scan pulses at the address discharge are generated from the scan driver 102, sustain pulses, etc. are generated by the Y side common drivers 103a and 103b and applied to the Y electrode 11 via the scan driver 102. The X electrodes 12 are commonly connected across all the display lines of the panel. The X-side common driver 104 generates a write pulse, a sustain pulse, and the like. These driver circuits are controlled by the control circuit 106, which is controlled by the synchronization signals CLOCK, VSYNC, HSYNC and the display data signal DATA input from the outside of the apparatus.

Fig. 5 is a waveform diagram showing a conventional driving method in the case where the PDP shown in Figs. 1 to 3 is interlaced by the circuit shown in Fig. 4, and one subfield period of " address / sustain discharge discharge type / write address method " Indicates. In this example, one subfield is divided into a reset period and an address period or a sustain discharge period. In the reset period, first, all the Y electrodes are at the 0 V level, and at the same time, a front write pulse made up of the voltage Vs + Vw (about 300 V) is applied to the X electrodes. Further, sustain discharge is performed so that erase discharge is performed with an erase pulse. This reset period has the effect of bringing all the cells to the same state irrespective of the lighting state of the previous subfield, so that the next address (write) discharge can be stably performed.

Subsequently, in the address period, in order to turn ON / OFF the cells according to the display data, address discharge is performed in the order of the lines. First, a scan pulse is applied to the Y electrode, and an address pulse of voltage Va (approximately 50 V) is selectively applied to the address electrode corresponding to the cell causing sustain discharge, that is, the cell to be turned on, among the address electrodes to selectively light it. A discharge occurs between the address electrode and the Y electrode of the cell. This is then primed (ignition), and immediately proceeds to discharge between the X electrode and the Y electrode. As a result, an amount of wall charges capable of sustain discharge is accumulated on the Mg0 planes on the X electrode and the Y electrode of the selection cell of the selection line.

In the following, the same operation is performed on the other display lines sequentially, and new display data is recorded on all the display lines.

After that, in the sustain discharge period, sustain pulses having a voltage of Vs (about 180 V) are applied to the Y electrode and the X electrode alternately to perform sustain discharge, thereby performing image display of one subfield. In addition, because of the interlace display, the Y electrode corresponding to the display line which has not discharged is in a high impedance state, and the power consumption is kept low.

In this " address / sustain discharge discharge type / write address method ", the luminance is determined by the length and the duration of the sustain discharge period, that is, the number of sustain pulses.

Specifically, as an example of multi-gradation display, a driving method in the case of performing 256-gradation display is shown in FIG. In this example, one field is divided into eight subfields: SF1, SF2, SF3, SF4, SF5, SF6, SF7, SF8. In one field, one of the odd lines or the even lines is displayed, and in the subsequent field, the other display lines are displayed.

In these subfields SF1 to SF8, the reset period and the address period each have the same length. In addition, the length of the sustain discharge period is 1: 2: 4: 8: 16: 32: 64: 128. Therefore, by selecting the subfield to be lit, the difference in luminance in 256 steps from 0 to 255 can be displayed.

The present applicant discloses a plasma display device for performing interlace display in Japanese Patent Application No. Hei 8-194320. 7 to 11 show the configuration and driving waveforms of the plasma display device which performs the interlace driving disclosed in this patent application No. Hei 8-194320.

FIG. 7 is a diagram showing an outline of a panel and a circuit configuration of an interlace display utilizing slits on both sides of the Y electrode as discharge slits. 8 is a cross-sectional structure thereof. 9 is a drive waveform diagram of an electrode showing the drive method. The characteristic of this driving method is to select the voltage to be applied to the X electrode at the time of address to trigger the discharge generated between the address electrode and the Y electrode, and to select which slit on both sides of the Y electrode to cause the discharge. Thereby, wall charge can be formed in the cell of the slit on the side to perform sustain discharge. In addition, electrodes adjacent to the slits which do not discharge are applied with a sustain pulse in phase to prevent erroneous discharge from occurring. Therefore, the Y holding circuit serving as the discharge holding means is separated into the radix Y holding circuit 124 and the even Y holding circuit 125, respectively, and the X holding circuit is separated from the radix X holding circuit 126 and the even X holding circuit ( 127, pulses for the address operation and the sustain operation can be applied independently.

In the plasma display device shown here, since the display rows of the radix field and the even field do not influence each other, it is not necessary to provide a partition wall for defining the display cells in the vertical direction between the Y electrode and the X electrode, and thus the plasma display panel. It is possible to make high definition.

Moreover, Japanese Patent Application Laid-open No. Hei 8-194320 discloses providing a light shielding body in a slit portion not related to display in order to prevent the display contrast from being lowered due to discharge not related to display. 10 is a view showing a configuration in which a light shielding body disclosed in Japanese Patent Application No. Hei 8-194320 is provided. The plasma display panel shown in Fig. 10 is a conventional one in which a display slit 131 is formed between a pair of Y electrodes and an X electrode as shown in Figs. 1 and 2, and the Y electrodes and the X electrodes in columns other than the display slits are shown. The light shield 132 is provided in the slit between them. As a result, the reflected light from the slit that is not for display is reduced.

In the plasma display device, a discharge called priming discharge is performed so that address discharge and sustain discharge can be performed smoothly. In the conventional example, for example, a reset discharge performed in the reset period serves as this priming discharge. Such priming discharges reduce the contrast of the display irrespective of the display image. For example, when priming discharge is performed between the Y1 electrode and the X2 electrode, when the light shielding body 132 as described above is provided, unnecessary light irrelevant to this display is blocked.

As described above, since the partitions need not be provided in parallel with the Y electrode and the X electrode by using the configuration as shown in FIG. 7, the plasma display panel can be made high in definition, There is a problem that the connection between the scan driver and the Y holding circuit serving as the discharge holding means or the Y common driver becomes complicated. In the conventional examples of Figs. 4 and 7, the Y electrode is divided into odd and even and connected to the holding circuit. In general, a scan driver is composed of, for example, one chip by an integrated circuit having a 64-bit output. Therefore, the wiring becomes complicated when connected to different holding circuits for each bit. In the case where all of the outputs of one chip are used for the odd electrode or even electrode, the connection between the sustain circuit and the scan driver is simplified, but the connection between the scan driver and the electrode of the panel is complicated. In either case, the device became complicated and the cost increased. In addition, performance and reliability have been deteriorated due to the increase in scale and complexity of wiring. Patent application No. Hei 8-194320 discloses a plasma display device that can solve this problem.

FIG. 11 is a diagram showing another configuration example of the plasma display device disclosed in Patent Application No. Hei 8-194320. In this plasma display apparatus, as shown in Fig. 11, two electrodes are provided on both sides of each of the Y electrodes in such a manner that X1 and X2 electrodes are provided on both sides of the Y1 electrode, and X3 and X4 electrodes are provided on both sides of the Y2 electrode. Install the X electrode. In the odd field, a discharge is applied by applying a voltage between each Y electrode and the odd-numbered X electrode, and in the even field, an interlace display is performed by applying a voltage between each Y electrode and the even-numbered X electrode to perform a discharge. Although the even-numbered X electrode and the odd-numbered X electrode are completely non-displayed, since there is no partition, high definition is possible, and there is no need to separate the Y electrode into two lines, so the connection between the scan driver and the Y holding circuit is performed. In addition, the connection between the scan driver and the panel is simplified.

In the plasma display device disclosed in Japanese Patent Application Laid-open No. Hei 8-194320, in the reset period as in the prior art, when a large voltage is applied between the Y electrode and the X electrode to perform front recording, and the discharge is a priming discharge, the priming discharge This is done in the same part as the display cell. As described above, since the priming discharge lowers the contrast of the display regardless of the display image, it is preferable to shield the light. However, in the device disclosed in Japanese Patent Application No. Hei 8-194320, since the priming discharge is performed in the display cell portion, In this part, a light shield as shown in Fig. 10 cannot be provided. Therefore, there is a problem that the display contrast cannot be sufficiently high in the conventional apparatus disclosed in Japanese Patent Application No. Hei 8-194320.

In this way, when the driving method of FIG. 9 using the front write discharge and the front self-erasing discharge or the driving method of FIG. 5 performing the front write and sustain discharge or erasing are used as the reset discharge, the slit has not been discharged. Also in this case, since the reset discharge (priming discharge) is performed, the contrast is reduced. Moreover, in these examples, since the priming discharge is performed in the display cell, there is a problem that the magnitude of the discharge is as large as that of the sustain discharge and consumes a large amount of power.

SUMMARY OF THE INVENTION An object of the present invention is to realize a plasma display device and a driving method thereof, which can prevent a decrease in display contrast caused by priming discharge and reduce power consumption.

1 is a schematic plan view of a conventional three electrode, surface discharge, AC type PDP.

2 is a schematic cross-sectional view of a conventional three electrode, surface discharge, AC type PDP.

3 is a schematic cross-sectional view of a conventional three electrode, surface discharge, AC type PDP.

4 is a schematic block diagram of a conventional PDP apparatus with interlaced display;

5 is a waveform diagram according to a conventional driving method.

Fig. 6 is a diagram showing continuation of gradation display.

7 is a configuration diagram of a panel and a driving circuit of a conventional interlaced display device in which barrier ribs parallel to the Y electrode and the X electrode are removed.

8 is a panel sectional view of the conventional example of FIG.

9 is a drive waveform diagram of a conventional device of FIG. 7;

Fig. 10 is a diagram showing a configuration of a conventional example in which a light shielding body for contrast enhancement is provided.

Fig. 11 is a diagram showing a configuration of another conventional example of the plasma display device for interlaced display.

12 is a view showing a light emitting position according to the present invention.

Fig. 13 is a configuration diagram of a plasma display panel and a driving circuit of the first embodiment of the present invention.

Fig. 14 is a diagram showing a panel structure and a light emitting position of the first embodiment.

Fig. 15 is a diagram showing the configuration of the X holding circuit of the first embodiment.

Fig. 16 is a drive waveform diagram (radix field) of the first embodiment.

Fig. 17 is a drive waveform diagram (excellent field) of the first embodiment.

18 is a panel structural diagram of a second embodiment of the present invention;

19 is a panel structure diagram of a third embodiment of the present invention.

20 is a panel structure diagram of a fourth embodiment of the present invention.

Fig. 21 is a drive waveform diagram of a fifth embodiment of the present invention.

Fig. 22 is a drive waveform diagram of a sixth embodiment of the present invention;

Explanation of symbols for main parts of the drawings

51: first electrode (Y electrode)

52o: second electrode (base X electrode)

52e: third electrode (excellent X electrode)

53: address electrode

54: bulkhead

55: first display cell

56: second display cell

57: third cell

61o: second electrode drive means (base X holding circuit)

61e: third electrode drive means (excellent X holding circuit)

62: first electrode drive means (scan driver)

63: first electrode drive means (Y holding circuit)

In the plasma display device of the present invention, the first, second and third electrodes are alternately arranged in parallel on the first substrate, and the plasma is arranged so as to be orthogonal to the first electrode on the first or second substrate. A display panel, first electrode selection driving means for selectively driving the first electrode, second electrode driving means for driving the second electrode, and third electrode driving means for driving the third electrode; A first display cell is formed at an intersection point of the fourth electrode including a second electrode and a second electrode, and a second display cell is formed at an intersection point of the fourth electrode including the first electrode and the third electrode. In a plasma display device in which an interlaced display is performed alternately of light emission display in a cell and a second display cell, the second electrode driving means and the third electrode driving means are provided with a voltage between the second and third electrodes during the reset period. And applying, to perform a priming discharge in the third cell, the is characterized in that a third cell for priming by the second electrode and the third electrode formation.

Moreover, the driving method of the plasma display apparatus of this invention is a driving method of the plasma display apparatus which performs interlace display as mentioned above, The reset process which makes the state of a display cell uniform, The address process which writes display data, A drive method for repeatedly performing a sustain discharge step of holding a discharge in a cell to be lit, wherein the sustain discharge step of performing a sustain discharge in a first display cell includes a sustain phase that is in phase with a sustain pulse applied to the first electrode. In the sustain discharge step of applying a discharge pulse to the second electrode and setting the potential of the third electrode to a predetermined value lower than the voltage of the sustain discharge pulse and performing discharge sustain in the second display cell, A sustain discharge pulse that is out of phase with the sustain pulse to be applied is applied to the third electrode and at the same time Is a predetermined voltage value lower than the voltage of the sustain discharge pulse, and in the reset step, priming discharge is performed by applying a voltage between the second and third electrodes, and the third and second electrodes for priming are performed by the second and third electrodes. Characterized in that the cell is formed.

12 is a view showing a light emission position in the present invention. 12, Y1, Y2,... Is the Y electrode, Xo is the second electrode, Xe is the third electrode, T1 in (1) is the third cell, T2 is the first display cell (odd display cell: odd display cell), T3 has shown the 2nd display cell (display cell of an excellent row: even cell), respectively. According to the present invention, since priming discharge is performed in the third cell T1 between the second and third electrodes instead of the display cell, it is possible to provide a light shield and to shield the display contrast. In addition, since the priming discharge is performed in the third cell T1 rather than the display cell, it is also possible to reduce the magnitude of the discharge and to reduce the power consumption.

Furthermore, a light shielding body is provided in a third slit which is a gap between the second and third electrodes.

In addition, during the sustain discharge period, the first electrode selection drive means applies the first sustain discharge pulse to the first electrode, and one of the second electrode drive means and the third electrode drive means is out of phase with the first sustain discharge pulse. The phosphorus sustain discharge pulse is applied, and the other side is applied with a predetermined constant voltage or the corresponding electrode is made high impedance. Therefore, since the voltage of the slit (cell) which does not discharge becomes less than the minimum discharge holding voltage, it does not generate an erroneous discharge.

In addition, the predetermined constant voltage is about half the voltage of the first sustain discharge pulse, and the voltage of the cell which does not discharge can be made smallest.

The first slit, which is a gap between the first and second electrodes, and the second slit, which is a gap between the first and third electrodes, are arranged at equal intervals.

Further, a third slit, which is a gap between the second and the third electrode, is formed in the middle of the adjacent first electrode.

The first to third electrodes are formed of a transparent electrode and a metal bus electrode.

The transparent electrode of the first electrode is wider than the bus electrode, and the bus electrode is formed at the center of the transparent electrode.

In addition, the transparent electrodes of the first and second electrodes are wider than the bus electrodes, and the bus electrodes are formed on the third slit side.

Further, the width of the bus electrode of the first electrode is set to be equal to the dimension from the end of the first slit side of the bus electrode of the second electrode to the end of the second slit side of the bus electrode of the third electrode in the adjacent row. do. As a result, the first display cell and the second display cell are balanced.

In addition, the thickness of the bus electrode of the first electrode is set to almost half of the thickness of the bus electrode of the second and third electrodes.

Further, the resistance values of the first to third electrodes are set to be the same. As a result, the luminance decrease caused by the voltage reduction due to the electrode resistance becomes equal at the left and right of the display.

Furthermore, a light shielding body is formed on the surface side on the first electrode. The light emission of the priming discharge in the third cell can be blocked and the invalid light emission can be reduced.

Further, the width of the light shielding body on the first electrode is set to be equal to the dimension from the end of the first slit side of the bus electrode of the second electrode to the end of the second slit side of the bus electrode of the third electrode in the adjacent row. . As a result, the cell arrangement is balanced.

Further, the width of the third slit is set to be narrower than the width of the first and second slits. Accordingly, even when the same voltage is applied between the first and second display cells and the electrodes forming the third cell, it is possible to generate discharge only in the third cell.

In addition, a fourth slit is formed in the center of the first electrode. As a result, excessive expansion of the discharge can be prevented, and the light emission shape becomes uniform, and the sustain discharge is stabilized.

Further, a light shielding body is formed in the fourth slit in the center of the first electrode. As a result, the reflected light can be prevented and the contrast can be improved.

In addition, in the reset step, priming discharge is performed in the third cell by applying a voltage between the second electrode and the third electrode, so that address discharge can be performed safely and reliably.

In the reset step, since the voltage of the first electrode at the time of applying the voltage between the second electrode and the third electrode applies a voltage approximately midway between the voltage between the second electrode and the third electrode, In the first and second cells, the discharge does not occur at the same time.

In addition, the voltage of the 1st electrode in a reset process is the same as the voltage of a sustain discharge pulse.

In addition, when the light emitting display is performed in the first display cell and the light emitting display is performed in the second display cell, the discharge can be efficiently generated by changing the polarity of the voltage application to generate the priming discharge.

In priming discharge, since a voltage having a reverse polarity to the last sustain discharge pulse of the last sustain discharge step is applied, priming discharge can be performed even if erase discharge is not performed before.

In addition, since the reverse polarity voltage is applied to the second or third electrode by setting the potential of the first electrode as the voltage at the last sustain discharge of the immediately preceding sustain discharge process, discharge can be efficiently generated.

In addition, the discharge is started to the third cell, and the priming discharge is performed by applying a pulse having a voltage such that the discharge is performed again after the pulse is removed. In addition, since the potential difference of all electrodes is set so that after removal of a pulse, it becomes a self-erasing discharge and can remove wall charge uniformly.

Further, the first or second discharge discharge was performed immediately before the discharge was performed by applying a voltage having a polarity reverse to that of the last sustain discharge in the last sustain discharge step. Since the discharge is generated at the same time in the display cell, the discharge which is erased can be generated together with the cell which is performing the sustain discharge of the first and second display cells.

In addition, immediately before the transition from the display in the first display cell to the display in the second display cell and immediately before the transition from the display in the second display cell to the display in the first display cell, discharge occurs in all cells. Apply a voltage pulse to make it work. In addition, immediately before the transition from the display in the first display cell to the display in the second display cell, the display shifts to the second display cell and the third cell and from the display in the second display cell to the display in the first display cell. Since the discharge is performed by applying a voltage pulse to generate the discharge to the first display cell and the third cell, respectively, immediately before, the cell for newly displaying light emission can be activated.

Further, at the end of the discharge sustaining step, an erase pulse is applied between the first electrode and the second electrode or the third electrode.

The configuration of the plasma display device of the first embodiment of the present invention is shown in FIG. In addition, the control part etc. which were shown in FIG. 4 are abbreviate | omitted.

The cross-sectional structure of the plasma display panel of this apparatus is shown in FIG. The electrode of this panel is composed of a wide Y electrode 51, an Xo electrode 52o, an Xe electrode 52e, and an address electrode 53 surrounding it. The Y electrode 51 is a transparent electrode 51a and a metal bus electrode 51b, the Xo electrode 52o is a transparent electrode 52ao and a metal bus electrode 52bo, and the Xe electrode 52e is a transparent electrode. 52ae and a metal bus electrode 52be. Metal bus electrodes are used to prevent voltage drops. As shown, the transparent electrode is wider than the bus electrode. In the Y electrode 51, the bus electrode 51b is formed in the center of the transparent electrode 51a. In the Xo electrode 52o and Xe electrode 52e, the bus electrodes 52bo and 52be are transparent electrodes 52ao and 52ae. ) Is provided on the side facing the X electrode of the adjacent row. The width of the bus electrodes 51b of the Y electrodes 51 is equal to the sum of the widths of the light shields 58 provided between the bus electrodes 52bo and 52be and the X electrodes in adjacent rows. In addition, the thickness of the bus electrode 51b of the Y electrode 51 is preferably about half of the thickness of the bus electrodes 52bo and 52be. As a result, the resistance value of each bus electrode becomes the same.

A first slit 71 is formed between the Xo electrode 52o and the Y electrode 51, and a first cell (odd cell) 55 which displays in the radix field at the first slit 71 portion. Is formed. Further, a second slit 72 is formed between the Xe electrode 52e0 and the Y electrode 51, and a second cell (evev cell) 56 which displays in the even field in the second slit 72 portion. Further, a third slit 73 is formed between the Xo electrode 52o and the Xe electrode 52e, and a third cell 57 for priming is formed in this portion. A light shield 58 is provided at 73 to prevent light emission from priming discharge from leaking out.

The Y electrode is connected to a scan driver 62 which is a selecting means, and is connected to a Y holding circuit 63 which collectively applies a signal for sustaining discharge. The scan driver 62 generates a scan pulse, and the Y holding circuit 63 generates a sustain discharge pulse and applies it to the Y electrode 51. On the other hand, the Xo electrode 52o and the Xe electrode 52e are connected to the radix X holding circuit 61o and the even X holding circuit 61e which collectively apply a signal for sustaining discharge. In addition, since the drive circuit of an address electrode is the same as that of a conventional example, it abbreviate | omits.

FIG. 15 is a diagram showing details of the radix X holding circuit 61o and the even X holding circuit 61e. The voltage Vs is the voltage of the sustain discharge pulse, Vm is the voltage applied to the electrode which does not discharge during the discharge sustain period, and is about half of Vs.

Fig. 16 is a drive waveform diagram of each electrode showing the operation of the apparatus, showing the timing of one subfield in the odd field. First, a pulse consisting of a voltage Vw (about 300 V) is applied to the Xo electrode 52o. By this pulse, discharge occurs in the third cell 57 between the Xo electrode 52o and the Xe electrode 52e. On the other hand, since the voltage Vs is applied to the Y electrode 51, no discharge occurs in the first and second cells 55 and 57. By this discharge, wall charges are accumulated on the surfaces of the dielectric layers on the Xo electrode 52o and the Xe electrode 52e. The pulse is removed at about 10 mu s, and discharge occurs again by the voltage of the wall charge itself at the timing when all the electrodes become 0V. This discharge is terminated by neutralizing the space charge without accumulating wall charges because the potential difference between the electrodes is OV. However, some of the space charge floats in the space without being neutralized, and therefore works effectively as an ember (priming) during address discharge.

In the address period, scan pulses (-150V) are sequentially applied to the Y electrode 51, and address pulses 50V are selectively applied to the address electrodes 53 corresponding to the cells to be turned on. As a result, discharge is performed between the address electrode and the Y electrode. At this time, since the Xe electrode 52e is 0V in the radix field, VX (50V) is applied to the Xo electrode 52o. Thus, Xo is triggered by the discharge of the address electrode 53 and the Y electrode 51. The discharge proceeds between the electrode 52o and the Y electrode 51, that is, in the first cell 55. By this discharge, wall charges capable of performing sustain discharge in the sustain discharge period are formed. The above operation is repeated sequentially, and the recording of display data on the zone screen is completed.

In the sustain discharge period, sustain discharge is repeated in the cell in which the sustain discharge pulse is alternately applied to the Y electrode 51 and the Xo electrode 52o, where writing is performed. At this time, since the intermediate voltage Vm of the sustain discharge pulse is applied to the Xe electrode 52e, no false discharge occurs in the second cell 56. Finally, an erase pulse of fine width is applied to the Y electrode 51 to erase the wall charges.

17 is a drive waveform diagram of an even field. The pulse at reset is applied to the Xe electrode 52e. Further, at the address, VX is applied to the Xe electrode 52e to form wall charges in the second cell 56. In the sustain discharge period, the Vm voltage is applied to the Xo electrode 52e to prevent erroneous discharge in the first cell 55.

18 is a panel structure of a second embodiment of the present invention. The device configuration and driving method are the same as in the first embodiment. In this panel, a light shield 59 is provided on the Y electrode side 51. The width is the same as the width including the bus electrodes 52bo, 52be of the Xe electrode 52e, the Xo electrode 52o, and the light shield 58, and the width of the first cell 55 and the second cell 56. When the luminescent shape is seen from the center of the first and second slits, they are equally spaced and the balance is good.

19 is a panel structure of a third embodiment of the present invention. The device configuration and driving method are the same as in the first embodiment. In this panel, the width of the bus electrode 51b on the Y electrode side 51 is equal to the width including the Xe electrode and Xo electrode bus electrodes 52bo and 52be and the light shield 58 in adjacent rows. have. Therefore, as in the second embodiment, when the light emission shapes of the first cell and the second cell are viewed from the center of the first and second slits, they are equally spaced and the balance is improved.

20 is a panel structure of the fourth embodiment of the present invention. The device configuration and driving method are the same as in the first embodiment. This panel is provided with a fourth slit at the center of the Y electrode 51 side. By this slit, it is possible to prevent the discharge from spreading only to the Y electrode side, and when the light emission shapes of the first cell and the second cell are viewed from the center of the first and second slits, they are equally spaced and balanced. . In addition, the discharge can be stabilized.

Fig. 21 is a view showing drive waveforms of the fifth embodiment of the present invention, except that the drive waveforms are different, the apparatus of the fifth embodiment is the same as that of the first embodiment. Fig. 21 shows the timing of one subfield in the odd field. In this embodiment, the last sustain discharge pulse is applied to the Y electrode to finish the sustain discharge process. Therefore, in the lit cell, negative wall charges are formed on the Y electrode side, and positive wall charges are formed on the Xo electrode side. Entering the reset process, a pulse consisting of the voltage Vw is applied to the Xo electrode. Discharge is started in the third cell, but the sustain charge is performed immediately before the load charge of the Y electrode of the cell holding the wall charge is neutralized by the movement of the space charge by this discharge. After the pulse is removed, self-erase discharge is performed in the third cell as in the first embodiment.

Fig. 22 is a diagram showing drive waveforms according to the sixth embodiment of the present invention, showing the timing of one subfield in the odd field. In the panel to be applied in this embodiment, the width of the third slit is approximately half that of the panel of the former embodiment. In this embodiment, the last sustain discharge pulse is applied to the Y electrode to finish the sustain discharge process. In the lit cell, negative wall charges are formed on the Y electrode side, and positive wall charges are formed on the Xo electrode side. Entering the reset process, a pulse of voltage Vw is applied to the Xo electrode. This voltage is set to a value lower than the value of Vw in the former embodiment. Since the width of the third slit is narrow even at a low voltage, the discharge can be sufficiently initiated. Discharge is initiated in the third cell, wall charges are accumulated, and self-erase discharge is performed at the time of pulse removal. The cell which has just performed sustain discharge and accumulated negative wall charge charge on the Y electrode generates self-erasing discharge and performs erasure.

Also in the panel of the first embodiment, a reset operation of the display cell can be performed by applying this pulse having a high voltage at the time of field switching.

As described above, according to the present invention, the plasma display device can be realized in which the driving circuit is simplified, low cost, low emission, low contrast, and high contrast interlace display.

Claims (33)

A plasma display panel in which the first, second, and third electrodes are alternately arranged in parallel on the first substrate, and the fourth electrode is orthogonal to the first electrode on the first substrate or the second substrate; First electrode selection driving means for selectively driving the first electrode; Second electrode driving means for driving the second electrode; A third electrode driving means for driving the third electrode; A first display cell is formed at an intersection of the first electrode, the second electrode and the fourth electrode, and a second display cell is formed at an intersection of the first electrode, the third electrode and the fourth electrode; In the first display cell and the second display cell, interlaced display is performed to alternately emit light emission display, During a reset period, the second electrode driving means and the third electrode driving means apply a voltage to the second and third electrodes, thereby priming discharge in a third cell formed by the second electrode and the third electrode. Plasma display device, characterized in that performed. The plasma display device according to claim 1, wherein a light shield is provided in a third slit which is a gap between the second and third electrodes. 3. The method according to claim 2, wherein during the sustain discharge period, the first electrode select drive means applies a first sustain discharge pulse to the first electrode, wherein one of the second electrode drive means and the third electrode drive means And a sustain discharge pulse that is in phase out of phase with the first sustain discharge pulse, and the other applies a predetermined constant voltage or maintains the corresponding electrode at high impedance. 4. The plasma display device of claim 3, wherein the predetermined constant voltage is about half of the voltage of the first sustain discharge pulse. The first slit as the gap between the first and second electrodes and the second slit as the gap between the first and third electrodes are arranged at equal intervals according to any one of claims 2 to 4. Plasma display device. The plasma display apparatus according to claim 5, wherein the third slit is formed in the middle of the adjacent first electrode. The plasma display device according to any one of claims 2 to 5, wherein the first to third electrodes are formed of a transparent electrode and a metal bus electrode. The plasma display apparatus of claim 7, wherein the transparent electrode of the first electrode is wider than the bus electrode, and the bus electrode is formed at the center of the transparent electrode. The plasma display apparatus of claim 7 or 8, wherein the transparent electrodes of the second and third electrodes are wider than the bus electrode, and the bus electrode is formed on the third slit side. 6. The width of the bus electrode of the first electrode is defined by the second slit side of the bus electrode of the third electrode in a row adjacent from the end of the first slit side of the bus electrode of the second electrode. Plasma display device characterized in that the same dimensions as the end. 11. The plasma display apparatus of claim 10, wherein the thickness of the bus electrodes of the first electrode is approximately half the thickness of the bus electrodes of the second and third electrodes. The plasma display device according to claim 10, wherein the resistance values of the first to third electrodes are the same. The plasma display apparatus of claim 2, wherein a light shield is formed on the first electrode. The plasma display apparatus of claim 6, wherein a light shield is formed on the first electrode. 15. The second slit side of the bus electrode of the third electrode in an adjacent row from the end of the first slit side of the bus electrode of the second electrode. And a dimension up to the end of the plasma display device. The plasma display apparatus of claim 5, wherein the width of the third slit is narrower than the width of the first and second slits. The plasma display apparatus of claim 5, wherein a fourth slit is formed at the center of the first electrode. 18. The plasma display apparatus of claim 17, wherein a light shield is formed in a fourth slit in the center of the first electrode. And a plasma display panel in which the first, second, and third electrodes are alternately arranged in parallel on the first substrate, and the fourth electrode is orthogonal to the first electrode on the first substrate or the second substrate. A first display cell is formed at the intersection of the first electrode, the second electrode and the fourth electrode, and a second display cell is formed at the intersection of the first electrode, the third electrode and the fourth electrode. A method of driving a plasma display apparatus for performing interlaced display in which the light emitting display is alternately repeated in the first cell and the second cell, In the driving method which repeats the reset process which makes the state of a display cell uniform, the address process which writes display data, and the sustain discharge process which hold | maintains discharge in the cell to light up, In a sustain discharge step of holding a discharge in the first display cell, a sustain discharge pulse that is in phase with a sustain discharge pulse applied to the first electrode is applied to the second electrode and at the same time the potential of the third electrode. Is a predetermined value lower than the voltage of the sustain discharge pulse, In a sustain discharge step of holding a discharge in the second display cell, a sustain discharge pulse that is in phase with a sustain discharge pulse applied to the first electrode is applied to the third electrode and at the same time the potential of the second electrode. Is a predetermined voltage value lower than the voltage of the sustain discharge pulse, In the reset step, a priming discharge is performed by applying a voltage between the second and third electrodes so that a third cell for priming is formed by the second and third electrodes. Driving method. 20. The method of driving a plasma display apparatus according to claim 19, wherein light from a third slit which is a gap between the second and third electrodes is shielded. 21. The method of claim 20, wherein the predetermined voltage value is applied to the third electrode when sustain discharge is performed in the first display cell, and the predetermined voltage value is applied to the second electrode when sustain discharge is performed in the second display cell. And about half of the voltage applied between the first and second electrodes or between the first and third electrodes during discharge. 21. The plasma display device as claimed in claim 20, wherein the second electrode or the third electrode is in a high impedance state when sustain discharge is performed in the first display cell and when sustain discharge is performed in the second display cell. How to drive a display device. 23. The voltage applied to the first electrode when the priming discharge is being performed in the reset step, wherein the voltage applied to the first electrode is approximately an intermediate voltage of the potential between the second and third electrodes. A drive method of a plasma display device. 24. The method of driving a plasma display apparatus according to claim 23, wherein, when the priming discharge is performed in the reset process, the voltage applied to the first electrode is equal to the voltage of the sustain discharge pulse. 25. The method according to any one of claims 20 to 24, wherein the second and third devices are used to generate the priming discharge when the light emitting display is performed in the first display cell and when the light emitting display is performed in the second display cell. And a polarity of the voltage applied to the electrode is changed. 25. The method according to any one of claims 20 to 24, wherein the polarity of the voltage applied to the second electrode and the third electrode to generate the priming discharge is inverse to the last sustain discharge pulse of the sustain discharge process immediately before the priming discharge. A driving method of a plasma display device, characterized in that the polarity. 29. The method of claim 28, wherein when the priming discharge is generated, a reverse polarity voltage is applied to the second or third electrode with the potential of the first electrode as the potential at the last sustain discharge of the last sustain discharge process. A driving method of a plasma display device, characterized in that. 28. The pulse according to any one of claims 20 to 27, wherein when the priming discharge is generated, a pulse is applied to the third cell to start discharge, and after the pulse is removed, a pulse having a voltage of discharge is applied again. To generate a priming discharge. 29. The method of driving a plasma display apparatus according to claim 28, wherein the potential difference of all electrodes disappears after the removal of the pulse for generating the priming discharge. 28. The priming discharge according to any one of claims 20 to 27, wherein the priming discharge is generated by applying a pulse having a polarity opposite to the voltage applied during the last sustain discharge in the last sustain discharge process, and again upon removal of the pulse. And applying a voltage pulse so that discharge occurs simultaneously in the first or second display cells which have been sustaining discharge just before. 31. The first display cell according to any one of claims 20 to 30, wherein immediately before the transition from the display in the first display cell to the display in the second display cell and from the display in the second display cell. And a voltage pulse is applied so that discharge occurs in all cells immediately before the transition to the display in. 31. The method according to any one of claims 20 to 30, wherein immediately before the transition from the display in the first display cell to the display in the second display cell, the second display cell and the third cell are further selected. Driving of the plasma display device, characterized in that a voltage pulse is applied to the first display cell and the third cell immediately before the transition from the display in the second display cell to the display in the first display cell. Way. The plasma display device according to any one of claims 20 to 30, wherein an erase pulse is applied between the first electrode and the second electrode or the third electrode at the end of the sustain discharge process. Driving method.