JP3442852B2 - Driving method of plasma display panel - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method for driving a plasma display <br/> panel.

[0002]

2. Description of the Related Art As is well known, a plasma display panel has recently been variously studied as one of thin secondary screen displays, and one of them is an AC discharge type matrix system having a memory function. Plasma display panels are known. An outline of a driving device including such a plasma display panel will be described with reference to FIG.

Such a driving device comprises a signal processing unit 1 for processing a so-called composite video signal as an input signal and a display unit 2 for receiving a driving signal from the signal processing unit 1 and displaying a two-dimensional screen. . In the signal processing unit 1, the A / D converter 3 converts the input composite video signal into digital pixel data in synchronization with the timing pulse supplied from the timing pulse generation circuit 6 and supplies the digital pixel data to the frame memory 8. The sync separation circuit 5 extracts horizontal and vertical sync signals from the input composite video signal and supplies them to the timing pulse generation circuit 6. The timing pulse generation circuit 6 generates various timing pulses based on these horizontal and vertical synchronizing signals. The memory control circuit 7 supplies a write signal and a read signal synchronized with the timing pulse supplied from the timing pulse generation circuit 6 to the frame memory 8. Frame memory 8
The pixel data sequentially supplied from the A / D converter 3 according to the write signal. In addition, the frame memory 8 responds to the read signal by the frame memory 8
The pixel data stored therein is sequentially read and supplied to the output processing circuit 9 in the next stage.

The output processing circuit 9 corresponds to the brightness gradation of each field of the supplied pixel data for each of the first to eighth fields.
Mode pixel data is generated, and these are supplied to the pixel data pulse generation circuit 12 in synchronization with the timing pulse from the timing pulse generation circuit 6. The row electrode drive pulse generation circuit 10 responds to the timing pulse from the timing pulse generation circuit 6 to scan pulse for starting discharge light emission, sustain pulse for maintaining discharge state, and stop discharge light emission. Erase pulses are generated respectively and are supplied to the row electrodes Y _1, Y _2, Y ₃ ... Yn- _{1 and} Yn of the PDP (plasma display panel) 11 and X _1, X _2, X ₃ ... Xn- _{1 and} Xn. . Further, the row electrode drive pulse generation circuit 10 generates a forced write pulse for forcibly starting discharge light emission regardless of the pixel data and applies it to each of the row electrodes Y _{1 to} Yn of the PDP 11.

The pixel data pulse generation circuit 12 generates a pixel data pulse having a voltage value corresponding to the logic "1" or "0" of the pixel data of one field supplied from the output processing circuit 9 and generates it. Is divided for each row, and the divided pixel data pulse for each row is applied to the column electrodes D _1, D _2, D ₃ ... Dm- _1, Dm by time division. FIG. 2 shows such P
It is a figure which shows the structure of DP11.

In the figure, on the inner surface of the front glass substrate 110 (the surface facing the rear glass substrate 113), which is the display surface, the row electrodes Y _{1 to} Yn and the row electrode X are paired with each other.
_{1 to} Xn are formed respectively. These row electrodes are covered with a dielectric layer 111. A Mgo (magnesium oxide) layer 112 is vapor-deposited on the dielectric layer 111. On the rear glass substrate 113, column electrodes D _{1 to} Dm coated with phosphor are formed.

FIG. 3 is a schematic diagram of a drive system implemented by such a drive device.
It is a figure which shows a 56 gradation drive sequence. Take 256
In gradation driving, one frame is formed by eight subfields SF1 to SF8 whose relative ratio of luminance is 1: 2: 4: 8: 16: 32: 64: 128, respectively. Therefore, in order to execute these sub-fields SF1 to SF8 within one frame period, a high-speed driving operation is essential and there is a problem that power consumption increases.

Therefore, there has been proposed a PDP driving device capable of performing high-speed driving operation with low power consumption. FIG. 4 is a diagram showing a driving operation timing by the driving device. In such a driving device, an initial reset cycle RC, a write cycle WC and a discharge sustaining cycle IC are executed within one subfield.

First, in the initial reset cycle RC, an erase pulse EP is simultaneously applied to each of the row electrodes X _{1 to} Xn to bring all the pixel cells into an erased state. After such operation, to discharge all the pixel cells by applying a forced write pulse WP row electrodes Y ₁ -Yn respectively simultaneously. By this discharge operation, wall charges are accumulated on each row electrode. The row electrodes X ₁ erase pulses EP again after the execution of the discharging operation ~Xn
Apply to each simultaneously. By applying the erase pulse EP, the value of the wall charges accumulated in each row electrode drops to the extent that discharge sustaining light emission cannot be performed.

By such an initial reset cycle RC,
Wall charges are formed in each pixel cell to the extent that discharge sustaining light emission cannot be performed. That is, the preliminary discharge is performed in the above-mentioned initial reset cycle RC. Next, in the write cycle WC, pixel data pulses DP _{1 to} DPn
Is sequentially applied to the column electrodes D _{1 to} Dm, the scanning pulse SP is sequentially applied to the row electrodes Y _{1 to} Yn to perform the address discharge according to the pixel data for one field.

Next, in the discharge sustaining cycle IC,
The sustain pulse IA is simultaneously applied to each of the row electrodes X _{1 to} Xn every predetermined period, and the sustain pulse IA is applied to the row electrode X.
_The sustain pulse IB is simultaneously applied to each of the row electrodes Y _{1 to} Yn during the period in which the sustain pulse IB is not applied to _{1 to} Xn. By applying such a sustain pulse, the discharge light emission state of the pixels that have undergone the address discharge in the address cycle WC is maintained.

As described above, in such a drive device,
Before the address discharge according to the pixel data is performed, the preliminary discharge is performed to form the wall charges in each pixel cell in advance. Therefore, at the time of the writing discharge of the pixel data, since the wall charges are already formed in each pixel cell, the discharge occurs even if the pulse voltage value of the scan pulse as the writing trigger is a relatively low voltage value. It will be. That is, low power consumption is achieved by setting the pulse voltage value of the scan pulse low.

Here, in the driving device, when the preliminary discharge is performed, the forced write pulse WP is once applied to all the X-row electrodes at the same time to bring all the pixel cells into the discharge state at the same time. ing. However, as described above, in order to bring all the pixel cells into the discharge state at the same time, it is necessary to increase the pulse voltage value of the forced write pulse WP, and this preliminary discharge itself hinders the reduction of power consumption. There was a problem.

[0014]

[0008] The present invention has been made to solve the above problems, a driving <br/> dynamic method Help plasma display panel can realize low power consumption drive It was made for the purpose of providing.

[0015]

The driving method of the present invention to I Help plasma display panel Means for Solving the Problems] includes a plurality of row electrode pairs arranged so that two by two pairs of said row electrode pair each
Discharge arranged near the outside of the row electrode pair of the first array of
A method of driving a plasma display panel comprising: a row electrode pair for cleaning and a plurality of column electrodes arranged in a direction perpendicular to the row electrode pair , wherein a preliminary discharge pulse is applied to the preliminary discharge row.
Between the electrodes forming the pre-discharge row electrode pair by applying to the electrode pair
After a preliminary discharge is generated in the
Sequential application to each of the row electrode pairs according to the arrangement order of the electrode pairs
Pre-discharge between the electrodes of the row electrode pair by
It has a preliminary discharge step that is sequentially generated, and a writing step that sequentially applies pixel data pulses corresponding to pixel data to the column electrodes to write pixel data.

[0016]

[0017]

[Action] In'll Help plasma display panel driving method in the present invention, the row conductive first arrangement of the row electrode pair each
For the row electrode pair for pre-discharge placed near the outside of the pole pair
After initiating the pre-discharge, for each row electrode pair
A pair of row electrodes is paired while generating a preliminary discharge in the order of arrangement.
Then, the pixel data is written.

[0018]

FIG. 5 is a diagram showing the configuration of an AC discharge type matrix type plasma display panel driving device which is driven according to the driving method according to the present invention. The driving device includes a signal processing unit 1 that processes a so-called composite video signal as an input signal and a display unit 2 that receives a driving signal from the signal processing unit 1 and displays a two-dimensional screen.

In the signal processing unit 1 of FIG. 5, the A / D converter 3 converts the input composite video signal into digital pixel data in synchronization with the timing pulse supplied from the timing pulse generation circuit 6 and converts it into a frame memory. Supply to 8. The sync separation circuit 5 extracts horizontal and vertical sync signals from the input composite video signal and supplies them to the timing pulse generation circuit 6. The timing pulse generation circuit 6 generates various timing pulses based on these horizontal and vertical synchronizing signals. The memory control circuit 7
A write signal and a read signal synchronized with the timing pulse supplied from the timing pulse generation circuit 6 are supplied to the frame memory 8. The frame memory 8 sequentially takes in the pixel data supplied from the A / D converter 3 according to the write signal. Further, the frame memory 8 sequentially reads the pixel data stored in the frame memory 8 according to the read signal and supplies the pixel data to the output processing circuit 9 in the next stage.

The output processing circuit 9 corresponds to each of the supplied pixel data of one field and corresponds to the luminance gradation of the first to eighth areas.
Mode pixel data is generated, and these are supplied to the pixel data pulse generation circuit 12 in synchronization with the timing pulse from the timing pulse generation circuit 6. The row electrode drive pulse generation circuit 10 ′ responds to the timing pulse supplied from the timing pulse generation circuit 6 to generate sustain pulses IA and IB for maintaining a discharge state and an erase pulse EP for stopping discharge light emission. Occurrence of each, these PDP
Respectively applied to the row electrodes Y ₁ -Yn and X ₁ to Xn of 11 '.
In addition, the row electrode drive pulse generation circuit 10 'responds to the timing pulse supplied from the timing pulse generation circuit 6 by the preliminary discharge pulse PY and the preliminary discharge pulse PY for preliminary discharge in the dielectric layer 111 of the PDP 11'. PX respectively generated, respectively applies them to the preliminary discharge the row electrodes Y _P and the preliminary discharge the row electrodes X _P of the PDP 11 '. In addition, the row electrode drive pulse generation circuit 10 'generates a compulsory write pulse WP for forcibly exciting discharge light emission in response to the timing pulse supplied from the timing pulse generation circuit 6, and outputs this to the row of the PDP 11'. applying s to the electrodes Y ₁ -Yn or row electrodes X ₁ to Xn respectively. Further, the row electrode drive pulse generation circuit 10 'generates a selective erase pulse SEP for selectively erasing wall charges accumulated in the row electrodes when the charge value of the wall charges is a predetermined value or more. To PDP1
It applied to the row electrodes Y ₁ -Yn or row electrodes X ₁ to Xn of 1 '.

The pixel data pulse generation circuit 12 generates a pixel data pulse having a voltage value corresponding to the logic "1" or "0" of the pixel data for one field supplied from the output processing circuit 9, and generates the pixel data pulse. Is divided for each row, and the divided pixel data pulse for each row is applied to the column electrodes D _1, D _2, D _3, ... Dm- _1, Dm by time division. FIG. 6 is a view showing a structure of a PDP 11 'as an AC discharge type matrix type plasma display panel according to the present invention.

In FIG. 6, the inner surface of the front glass substrate 110, which is the display surface (the surface facing the rear glass substrate 113).
, Row electrodes Y _{1 to} Yn and row electrodes X _{1 to} Xn are formed so as to be paired with each other. Further, on the inner surface of such a front glass substrate 110, a pair of preliminary discharge for row electrodes Y _P and the preliminary discharge the row electrodes X _P is, the row electrode pairs Y ₁ -Yn and X ₁ to Xn and similar embodiments described above Is formed. Incidentally, such a priming discharge for row electrodes Y _P and X _P, the above row electrodes Y ₁ -Yn
And Yes to narrow the gap length as compared to the row electrodes X ₁ to Xn, has become capable discharged at a low voltage by such a configuration. Further, even if the pre-discharge row electrodes Y _P and X _P are not covered with the dielectric layer, they can be discharged at a low voltage. Also, such preliminary discharge the row electrodes Y _P and X _P is to reduce the electrode area as compared to the row electrodes Y ₁ -Yn and row electrodes X ₁ to Xn, discharge at low current This configuration It is possible.

Each of these row electrodes is covered with a dielectric layer 111. The dielectric layer 111 includes Mgo
A (magnesium oxide) layer 112 is deposited. A column electrode D ₁ coated with a phosphor is formed on the rear glass substrate 113.
~ Dm are formed. Here, a region where a pair of row electrodes and column electrodes intersect each other when viewed from the display surface of the front glass substrate 110 constitutes one pixel cell. A light-shielding mask 114 is formed on the surface of the front glass substrate 110 so as to block the emitted light from the discharge emission of the preliminary discharge row electrodes Y _P and X _P. The pixel data pulse supplied from the pixel data pulse generation circuit 12 is applied to the column electrode D from the side where the above-mentioned preliminary discharge row electrodes Y _P and X _P are formed, that is, from the direction shown by the arrow in FIG. _{1 to} Dm.

FIG. 7 illustrates the present invention implemented in such a device.
AC discharge type matrix plasma display
FIG. 7 is a drive operation timing chart showing a panel drive method.
Below, centering on the pixel cell related to the first row electrode,
The driving operation of will be described. First, step (a) in FIG.
In the row electrode drive pulse generation circuit 10 ',
Of the preliminary discharge pulse PX of the PDP 11 '
Pole X_PAt the same time that it is applied to
Y is a row electrode Y for preliminary discharge of the PDP 11 ' _PApply to.
At this time, the preliminary discharge row electrode X_PAnd Y_PApplied to
Positive discharge pulse PX and negative preliminary discharge pulse
Since the potential difference of the loose PY exceeds the discharge start voltage,
Pre-discharge row electrode X_PAnd Y_PElectric discharge occurs in the meantime. Take
Depending on the discharge, the pre-discharge row electrode X_PAnd Y_PSpace nearby
Electric charge is generated. The emitted light generated by this discharge
Is blocked by the light blocking mask 114 shown in FIG.
Then, the emitted light passes through the front glass substrate 110 and is emitted.
It will not be done. In other words, the actual situation in PDP11 '
The image display area of is the area surrounded by the broken line in FIG.

Next, in the step (b), the row electrode drive pulse generation circuit 10 'applies the sustain pulse IA having the positive polarity to the row electrode X ₁ and at the same time, the forced write pulse W having the negative polarity.
Apply P to the row electrode Y ₁ . At this time, the positive sustain pulse IA applied to each of the row electrode X ₁ and the row electrode Y ₁
Since the potential difference between the negative forced write pulse WP and the discharge start voltage exceeds the discharge start voltage, discharge occurs between the row electrode X ₁ and the row electrode Y ₁ . That is, in this step (b), PDP
All the pixel cells in the first row of 11 'discharge and emit light regardless of the pixel data. By such discharge light emission, wall charges having a predetermined charge value or more are formed near the electrodes of the row electrode X ₁ and the row electrode Y ₁ . That is, the preliminary discharge is performed in the step (b). In the forced writing of the first line in the process (b), the above process (a)
Due to the preliminary discharge performed in _1. , space charges remain on the preliminary discharge row electrodes X _P and Y _P formed adjacent to the row electrode X ₁ and the row electrode Y ₁ . Therefore, at this time, discharge light emission occurs between the row electrode X ₁ and the row electrode Y ₁ even if the pulse voltage value of the forced write pulse WP applied to the row electrode Y ₁ is a low voltage value. After performing the step (b), the step (c) is performed.

In the step (c), the pixel data pulse generation circuit 12 outputs m corresponding to the pixel data of the first row.
The pixel data pulse DP ₁ for bits is applied to the corresponding electrodes of the column electrodes D _{1 to} Dm of the PDP 11 ′. At the same time, the row electrode drive pulse generation circuit 10 ′ applies a positive sustain pulse IB to the row electrode Y ₁ . Although the positive sustain pulse IB and the pixel data pulse DP ₁ are applied at the same time in the figure, they need not be applied at the same time. That is, even if the pixel data pulse DP ₁ is applied at timings different from each other, the pixel data pulse DP ₁ may be applied at the rising or falling time of the sustain pulse IB.

In response to the application of the pixel data pulse DP ₁ and the sustain pulse IB, all the pixel cells in the first row discharge and emit light as in the step (b). At this time, a pixel data pulse having a voltage value based on the pixel data of the first row is applied to each of the column electrodes. For example, when the pixel data is logic "0", a pulse of 0 [V] is applied to the column electrode, while when the pixel data is logic "1", a positive voltage VD [V] is applied to the column electrode. Pulse is applied. That is, a pulse of 0 [V] or a positive polarity VD [V] corresponding to the supplied pixel data is applied to each pixel cell in the first row. Here, in the pixel cell to which the pulse of the positive voltage VD [V] is applied, the charge value of the wall charge accumulated in the above step (b) becomes a charge value smaller than the above predetermined charge value. Become. On the other hand, in the pixel cell to which the pulse of 0 [V] is applied, the charge value of the wall charge accumulated in the above step (b) remains as it is.

In FIG. 7, the step (c) is performed immediately after the step (b), but the step (c) does not necessarily have to be performed immediately after the step (b). Absent. For example, the step (c) may be performed by applying the pixel data pulse DP ₁ in synchronization with the second or third sustain pulse IB after the application of the forced write pulse WP. That is, the pixel data pulse D
It is not necessary to apply P ₁ in synchronization with the first sustain pulse IB applied immediately after the step (b).

Immediately after the step (c), the step (d) is immediately executed. In the step (d), the row electrode drive pulse generation circuit 10 'applies the negative selective erase pulse SEP to the row electrode Y1 of the PDP 11'. At this time, among the pixel cells in the first row, discharge light emission occurs only in the pixel cells in which the charge value of the wall charge is equal to or more than the above-mentioned predetermined charge value. That is, the selective erasing pulse SEP is a pulse having a voltage value that can cause discharge light emission when the charge value of the wall charges is equal to or more than the predetermined charge value. Furthermore, the selective erasing pulse SEP has a short pulse width such that wall charges cannot be formed after discharge light emission. Therefore, in the pixel cell in which discharge light emission occurs in response to the application of the selective erasing pulse SEP, the wall charge disappears after the discharge light emission. On the other hand, in the pixel cell in which the charge value of the wall charge is smaller than the above-mentioned predetermined charge value, since the charge value of the wall charge is lower than the above-mentioned predetermined charge value, even if the selective erase pulse SEP is applied. No discharge light emission occurs. Therefore, at this time, the wall charges remain in the pixel cell. That is, there is no wall charge in the pixel cell to which the pixel data pulse corresponding to the pixel data logic “0” is applied, and to the wall in the pixel cell to which the pixel data pulse corresponding to the pixel data logic “1” is applied. The electric charge remains.

By the series of operations of the steps (b) to (d), the information corresponding to the pixel data becomes 1 as the residual wall charge.
It is written in each pixel cell of the row. A series of writing operations such as the steps (b) to (d) are sequentially executed as shown in FIG. 7 in each row electrode of the second and subsequent rows. Here, the forced address discharge in the above-mentioned step (b) is sequentially executed in the order of 1st row to nth row. Therefore, in the "row" before the "row" to which the forced write pulse WP is applied, the forced write discharge has already finished, and the space charge generated by this forced write discharge is stored in the adjacent "row". It remains. Therefore, even if the pulse voltage value of the forced write pulse WP is set relatively low by utilizing the space charges remaining in the adjacent "rows", the row electrode X
It is possible to generate discharge light emission between Y and Y.
Therefore, a stable forced write operation can be performed with the forced write pulse WP having a low voltage value.

When the operations such as the above steps (b) to (d) are sequentially executed for each row and writing is completed up to the nth row, the discharge sustaining operation of the step (e) is restarted from the first row. To start. In the step (e), the row electrode drive pulse generation circuit 10 ′ alternately applies the positive sustain pulses IA and IB to the row electrodes X ₁ and Y ₁ . By applying the sustain pulse, only the pixel cell in which the above-mentioned residual wall charge exists among the pixel cells in the first row starts discharge light emission. At this time, the discharge light emission is repeatedly executed each time the sustain pulses IA and IB are alternately applied.

Next, in the step (f), the row electrode drive pulse generation circuit 10 'outputs the negative erase pulse EP to the PD.
It is applied to the row electrode X ₁ of P11 ′. Here, the erase pulse EP has a pulse width and a voltage value capable of extinguishing all the wall charges remaining in each pixel cell. Therefore, by applying the erase pulse EP, all the wall charges remaining in each pixel cell of the first row are extinguished and the discharge light emission is stopped.

The operations such as steps (e) and (f) are sequentially performed on the second and subsequent row electrodes as shown in FIG.
The address discharge for one subfield is performed by the series of operations in the steps (a) to (f). In the above embodiment, the preliminary discharge operation such as step (a) is performed once in one subfield, but it may be performed several times in one subfield.

[0034]

As above, according to the present invention, in the driving method by Help plasma display panel in the present invention, the row electrode pairs each
Discharge arranged near the outside of the first array of row electrode pairs in
After generating a preliminary discharge to the working electrode pair,
A preliminary discharge is generated for each of the pole pairs in the order of their arrangement.
Pixel data is written to each row electrode pair . At this time, space charges remain in the vicinity of the row electrodes after the preliminary discharge is completed . So adjacent to this row electrode
When a preliminary discharge is generated for the row electrode to be discharged, the space charge can be used to generate a discharge .
Pulse voltage of forced write pulse that triggers preliminary discharge
It is possible to set a low value and realize low power consumption.
To be done.

[0035]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a conventional AC discharge type matrix type plasma display panel driving device.

FIG. 2 is a diagram showing a structure of a PDP 11.

FIG. 3 is a diagram showing a 256 gradation driving sequence.

FIG. 4 is a diagram showing a driving operation by a driving device of a conventional AC discharge type matrix type plasma display panel.

FIG. 5 is a diagram showing a configuration of a driving device of an AC discharge type matrix type plasma display panel which performs a driving operation according to the driving method of the present invention.

FIG. 6 is a view showing a structure of a PDP 11 ′ as an AC discharge type matrix type plasma display panel according to the present invention.

FIG. 7 is a driving operation timing chart showing a driving method of an AC discharge type matrix type plasma display panel of the present invention.

[Explanation of symbols for main parts]

X _P , Y _P pre-discharge row electrode 10 'Row electrode drive pulse generation circuit 11' Plasma display panel

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01J 11/00 H01J 11/02 B 11/02 H04N 5/66 101B H04N 5/66 101 G09G 3/28 E H (56) Reference References JP-A 63-151997 (JP, A) JP-A 55-46471 (JP, A) JP-A 4-309993 (JP, A) JP-A 5-314910 (JP, A) JP-A 7- 199858 (JP, A) JP 61-198291 (JP, A) Actual development S55-1285 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/28 G09G 3 / 20 611 G09G 3/20 621 G09G 3/20 624 G09G 3/20 680 H01J 11/00 H01J 11/02 H04N 5/66 101

Claims (4)

(57) [Claims] 1. A plurality of row electrode pairs arranged to form pairs, and a row electrode of a first array in each of the row electrode pairs.
And the preliminary discharge row electrode pairs arranged near the outside of the pole pairs, and a plurality of column electrodes are arranged in a direction orthogonal to the row electrode pairs
A method of driving a plasma display panel comprising: applying a preliminary discharge pulse to the pair of preliminary discharge row electrodes;
A preliminary discharge is generated between the electrodes forming the row electrode pair for preliminary discharge.
After that, a compulsory write pulse is arranged in the order of arrangement of the row electrode pairs.
By sequentially applying to each of the row electrode pairs at
A preliminary discharge step for sequentially generating a preliminary discharge between electrodes of each row electrode pair, and a writing step for writing pixel data by sequentially applying pixel data pulses according to pixel data to the column electrodes. features and to pulp plasma display panel driving method that has a. 2. The surface of the plasma display panel
The upper part of the row electrode pair for the preliminary discharge is generated by the preliminary discharge.
It is characterized in that a light blocking means for blocking the light is formed.
The driving method of the plasma display panel according to claim 1 . 3. The pre-discharge row electrode pair is the electrode pair.
Gap length is narrower or electrode area is smaller than
The plasma display according to claim 1, characterized in that
How to drive the panel . 4. The row electrode pair and the pre-discharge row electrode
Only the row electrode pair of the pair is covered with the dielectric layer
The plasma display according to claim 1, characterized in that
How to drive the panel .