KR19980063715A - 반도체집적회로장치 - Google Patents
반도체집적회로장치 Download PDFInfo
- Publication number
- KR19980063715A KR19980063715A KR1019970065442A KR19970065442A KR19980063715A KR 19980063715 A KR19980063715 A KR 19980063715A KR 1019970065442 A KR1019970065442 A KR 1019970065442A KR 19970065442 A KR19970065442 A KR 19970065442A KR 19980063715 A KR19980063715 A KR 19980063715A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- mosfet
- input
- output
- gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 230000003071 parasitic effect Effects 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 abstract description 7
- 230000006872 improvement Effects 0.000 abstract description 2
- 239000000872 buffer Substances 0.000 description 51
- 230000015654 memory Effects 0.000 description 42
- 238000010586 diagram Methods 0.000 description 17
- 101150046174 NIP2-1 gene Proteins 0.000 description 15
- 101000894525 Homo sapiens Transforming growth factor-beta-induced protein ig-h3 Proteins 0.000 description 13
- 102100021398 Transforming growth factor-beta-induced protein ig-h3 Human genes 0.000 description 13
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 description 12
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 description 12
- 101100075513 Oryza sativa subsp. japonica LSI3 gene Proteins 0.000 description 12
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 description 12
- 230000000295 complement effect Effects 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 101100272964 Arabidopsis thaliana CYP71B15 gene Proteins 0.000 description 5
- 101150030164 PADI3 gene Proteins 0.000 description 5
- 102100035734 Protein-arginine deiminase type-3 Human genes 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 5
- 101100406797 Arabidopsis thaliana PAD4 gene Proteins 0.000 description 4
- 101150094373 Padi4 gene Proteins 0.000 description 4
- 102100035731 Protein-arginine deiminase type-4 Human genes 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000010365 information processing Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 description 2
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 description 2
- 101100075512 Oryza sativa subsp. japonica LSI2 gene Proteins 0.000 description 2
- 101150092599 Padi2 gene Proteins 0.000 description 2
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 102100021568 B-cell scaffold protein with ankyrin repeats Human genes 0.000 description 1
- 101000971155 Homo sapiens B-cell scaffold protein with ankyrin repeats Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
- H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (7)
- 전원전압에 대해 작은 신호진폭으로 된 수신신호가 외부단자를 거쳐서 게이트에 공급된 제 1 도전형의 제 1 MOSFET, 게이트에 상기 수신신호의 중간값에 대응한 기준전압이 인가된 제 1 도전형의 제 2 MOSFET 및 상기 제 1과 제2 MOSFET의 드레인에 마련되고 전류미러형태로 된 제 2 도전형의 제 3 과 제 4 MOSFET를 포함하고, 상기 제 1 MOSFET와 제 2 MOSFET의 드레인전류의 차전류에 대응한 출력신호를 형성하는 입력회로,상기 수신신호가 입력되는 외부단자에 마련된 실질적인 정전보호회로 및상기 제 2 MOSFET의 게이트에 마련되고 상기 실질적인 정전보호회로를 통해서 상기 제 1 MOSFET의 게이트에 전달되는 전원노이즈에 대해서 실질적으로 동일한 전원노이즈를 상기 제 2 MOSFET의 게이트에 전달하는 더미회로를 구비해서 이루어지는 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항에 있어서,상기 제 1 MOSFET와 제 2 MOSFET는 그의 소오스가 공통 접속되어 차동형태로 되는 것이고, 상기 공통화된 소오스에는 동작전류를 흐르게 하는 제 1 도전형의 MOSFET가 마련되는 것인 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항에 있어서,상기 정전보호회로는 전원전압단자와 상기 외부단자 사이에 역바이어스상태로 마련된 제 1 다이오드수단 및 상기 외부단자와 회로의 접지전위 사이에 역바이어스상태로 마련된 제 2 다이오드수단을 포함하는 것이고, 상기 더미회로는 상기 제1과 제2 다이오드수단의 사이즈가 동일하게 축소된 제3과 제4 다이오드수단에서 구성되는 것인 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항 또는 제 3 항에 있어서,상기 외부단자에는 출력회로의 출력단자가 공통으로 접속되는 것이고, 상기 정전보호회로는 상기 출력회로를 구성하는 출력MOSFET의 오프상태에서의 기생소자를 포함하는 것이고, 상기 더미회로는 상기 출력MOSFET에 상당하고 또한 그의 소자사이즈가 축소되어 오프상태로 된 더미MOSFET를 포함하는 것인 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항 또는 제 3 항에 있어서,상기 정전보호회로는 출력회로를 형성하기 위해 반도체기판상에 마련된 회로소자를 그의 일부로서 이용하는 것이고, 상기 더미회로는 상기 출력회로의 회로소자에 상당하고 또한 그의 소자사이즈가 축소되어 오프상태로 된 더미MOSFET를 포함하는 것인 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항에 있어서,상기 입력회로는 여러개로 이루어지는 것이고, 각 입력회로에 있어서의 상기 제 2 MOSFET의 게이트에는 각각 저항소자를 거쳐서 상기 기준전압이 공급되는 것인 것을 특징으로 하는 반도체집적회로장치.
- 제 1 항에 있어서,상기 입력회로는 3.3V용 스텁직렬종단형 논리에 적합한 것인 것을 특징으로 하는 반도체집적회로장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34251996A JP3693204B2 (ja) | 1996-12-06 | 1996-12-06 | 半導体集積回路装置 |
JP96-342519 | 1996-12-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19980063715A true KR19980063715A (ko) | 1998-10-07 |
KR100445841B1 KR100445841B1 (ko) | 2004-12-30 |
Family
ID=18354381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970065442A KR100445841B1 (ko) | 1996-12-06 | 1997-12-03 | 반도체집적회로장치 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6157203A (ko) |
JP (1) | JP3693204B2 (ko) |
KR (1) | KR100445841B1 (ko) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000306382A (ja) | 1999-02-17 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置 |
US6546534B1 (en) * | 1999-07-06 | 2003-04-08 | Sanyo Electric Co., Ltd. | Semiconductor integrated circuit device |
KR100360021B1 (ko) * | 2000-09-25 | 2002-11-07 | 삼성전자 주식회사 | 반도체 메모리 장치 및 이 장치의 비트 라인 분리 게이트배치방법 |
US6781428B2 (en) | 2001-06-27 | 2004-08-24 | Intel Corporation | Input circuit with switched reference signals |
US6828654B2 (en) * | 2001-12-27 | 2004-12-07 | Broadcom Corporation | Thick oxide P-gate NMOS capacitor for use in a phase-locked loop circuit and method of making same |
JP4292747B2 (ja) * | 2002-02-25 | 2009-07-08 | 富士ゼロックス株式会社 | 発光サイリスタおよび自己走査型発光素子アレイ |
JP3485559B1 (ja) * | 2002-06-24 | 2004-01-13 | 沖電気工業株式会社 | 入力回路 |
US6756834B1 (en) * | 2003-04-29 | 2004-06-29 | Pericom Semiconductor Corp. | Direct power-to-ground ESD protection with an electrostatic common-discharge line |
JP4275583B2 (ja) * | 2004-06-24 | 2009-06-10 | ユーディナデバイス株式会社 | 電子モジュール |
KR100815177B1 (ko) * | 2006-07-20 | 2008-03-19 | 주식회사 하이닉스반도체 | 반도체 장치 |
KR100889314B1 (ko) * | 2007-09-10 | 2009-03-18 | 주식회사 하이닉스반도체 | 버퍼 회로 |
KR100907009B1 (ko) * | 2007-11-12 | 2009-07-08 | 주식회사 하이닉스반도체 | 반도체 집적 회로 |
JP5175597B2 (ja) * | 2007-11-12 | 2013-04-03 | エスケーハイニックス株式会社 | 半導体集積回路 |
JP5547441B2 (ja) * | 2009-08-10 | 2014-07-16 | 旭化成エレクトロニクス株式会社 | 保護回路 |
TWI416703B (zh) * | 2009-11-24 | 2013-11-21 | Wintek Corp | 電子裝置 |
KR102103470B1 (ko) * | 2013-11-29 | 2020-04-23 | 에스케이하이닉스 주식회사 | 반도체 장치의 버퍼 회로 |
CN111052610A (zh) * | 2018-08-13 | 2020-04-21 | 深圳市汇顶科技股份有限公司 | 数据接口、芯片和芯片系统 |
JP2023042331A (ja) * | 2021-09-14 | 2023-03-27 | キオクシア株式会社 | 半導体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019729A (en) * | 1988-07-27 | 1991-05-28 | Kabushiki Kaisha Toshiba | TTL to CMOS buffer circuit |
US5023488A (en) * | 1990-03-30 | 1991-06-11 | Xerox Corporation | Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines |
JPH0729373A (ja) * | 1993-07-08 | 1995-01-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2792475B2 (ja) * | 1995-07-25 | 1998-09-03 | 日本電気株式会社 | 入力バッファ |
-
1996
- 1996-12-06 JP JP34251996A patent/JP3693204B2/ja not_active Expired - Lifetime
-
1997
- 1997-12-03 KR KR1019970065442A patent/KR100445841B1/ko not_active IP Right Cessation
- 1997-12-04 US US08/985,175 patent/US6157203A/en not_active Expired - Lifetime
-
1999
- 1999-11-16 US US09/441,659 patent/US6140834A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6140834A (en) | 2000-10-31 |
US6157203A (en) | 2000-12-05 |
KR100445841B1 (ko) | 2004-12-30 |
JPH10173509A (ja) | 1998-06-26 |
JP3693204B2 (ja) | 2005-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR19980063715A (ko) | 반도체집적회로장치 | |
US6233650B1 (en) | Using FET switches for large memory arrays | |
US6208168B1 (en) | Output driver circuits having programmable pull-up and pull-down capability for driving variable loads | |
US5151621A (en) | High speed output buffer unit that preliminarily sets the output voltage level | |
US7093066B2 (en) | Method for bus capacitance reduction | |
US6246629B1 (en) | Semiconductor IC device having a memory and a logic circuit implemented with a single chip | |
US7038927B2 (en) | High speed data bus | |
US5289062A (en) | Fast transmission gate switch | |
EP0905904B1 (en) | Semiconductor integrated circuit having tri-state logic gate circuit | |
US5483110A (en) | Signal transmission method, signal transmission circuit and information processing system using same | |
US4985644A (en) | Output buffer semiconductor and method for controlling current flow in an output switching device | |
US7068064B1 (en) | Memory module with dynamic termination using bus switches timed by memory clock and chip select | |
US20030042932A1 (en) | Combined dynamic logic gate and level shifter and method employing same | |
US20010043095A1 (en) | Output circuit | |
US5287527A (en) | Logical signal output drivers for integrated circuit interconnection | |
US6737891B2 (en) | Tri-directional, high-speed bus switch | |
JP3688572B2 (ja) | 半導体集積回路 | |
KR100247472B1 (ko) | 반도체기억장치및반도체집적회로장치 | |
US6597201B1 (en) | Dynamic predecoder circuitry for memory circuits | |
US6934204B2 (en) | Semiconductor device with reduced terminal input capacitance | |
US5798977A (en) | Power line coupling prevention circuit for semiconductor memory device | |
JP2538628B2 (ja) | 半導体集積回路 | |
JPH09139082A (ja) | 半導体記憶装置 | |
JPH07221605A (ja) | ラッチ回路並びにそれを用いたレジスタ回路およびパイプライン処理回路 | |
JPH0611109B2 (ja) | 半導体集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120724 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20130722 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20140722 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20150716 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20160720 Year of fee payment: 13 |
|
FPAY | Annual fee payment |
Payment date: 20170720 Year of fee payment: 14 |
|
EXPY | Expiration of term |