KR19980053670A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19980053670A KR19980053670A KR1019960072798A KR19960072798A KR19980053670A KR 19980053670 A KR19980053670 A KR 19980053670A KR 1019960072798 A KR1019960072798 A KR 1019960072798A KR 19960072798 A KR19960072798 A KR 19960072798A KR 19980053670 A KR19980053670 A KR 19980053670A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 하부 금속 배선이 형성된 반도체 기판 상에 제 1 IMO를 형성하는 단계; 상기 제 1 IMO를 평탄화시키는 단계; 상기 평탄화된 제 1 IMO 상에 제 2 IMO를 형성하는 단계; 하부 금속 배선이 노출되도록 상기 제 2 및 제 1 IMO를 사진식각하여 비아홀을 형성하는 단계; 및 상기 비아홀 및 그에 인접된 제 2 IMO 상에 상부 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a first IMO on a semiconductor substrate on which lower metal wirings are formed; Planarizing the first IMO; Forming a second IMO on the planarized first IMO; Forming via holes by photolithography the second and first IMO to expose the lower metal lines; And forming an upper metal interconnection on the via hole and a second IMO adjacent thereto.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는, SOG막으로 인하여 금속 배선의 부식 및 비아홀의 결함이 발생되는 것을 방지하는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that prevents corrosion of metal wiring and defects of via holes due to SOG film.
최근, 반도체 소자의 집적도가 증가함에 따라, 반도체 소자의 고집적도를 달성하기 위하여 다층 금속 배선 및 고밀도의 상호연결(interconnection)구조 등이 이용되고 있으며, 이러한 다층 금속 배선 기술에서는 하부층의 표면 요철로 인하여 다층 금속 배선을 형성한 후에 금속 배선들 사이의 단선 및 쇼트 문제가 발생되는 것을 최소화하기 위하여 하부층 상에 평탄화물로서 SOG(Spin On Glass) 또는 BPSG(Boro Phospho Silicate Glass) 등과 같은 복합 수지 물질들을 플로우(flow)시켜 하부층의 표면 요철을 감소시키는 방법이 실시되고 있다.In recent years, as the degree of integration of semiconductor devices increases, multilayer metal wirings and high-density interconnect structures are used to achieve high integration of semiconductor devices. In the multilayer metal wiring technology, due to the surface irregularities of the lower layers, After forming the multi-layered metal wiring, flow of composite resin materials such as spin on glass (SOG) or Boro Phospho Silicate Glass (BPSG) as a flattener on the lower layer to minimize the occurrence of disconnection and short problems between the metal wirings. A method of reducing the surface irregularities of the lower layer by flow is implemented.
상기와 같은 SOG를 이용한 반도체 소자의 제조 방법을 도 1A 및 도 1B를 참조하여 설명하면 다음과 같다.A method of manufacturing a semiconductor device using the SOG as described above will be described with reference to FIGS. 1A and 1B.
도 1A를 참조하면, 반도체 기판(1) 상에 공지의 방법으로 하부 금속 배선(2)을 형성한 후, 전체 상부에 제 1 층간 절연막(Inter Metal Oxide: 이하, IMO, 3)으로서 약 1,000Å 두께의 SiO2막을 형성한다. 하부 금속 배선(2)으로 인한 토폴로지의 악화를 방지하기 위하여 제 1 IMO(3) 상에 평탄화막인 SOG 복합 수지 물질을 도포 및 큐어링하여 SOG막(4)을 형성한다.Referring to FIG. 1A, after the lower metal wiring 2 is formed on the semiconductor substrate 1 by a known method, about 1,000 kV is used as the first interlayer insulating film (IMO, 3) on the whole. A thick SiO 2 film is formed. In order to prevent deterioration of the topology due to the lower metal wiring 2, the SOG composite resin material, which is a flattening film, is coated and cured on the first IMO 3 to form the SOG film 4.
도 1B를 참조하면, SOG막(4) 상에 SiO2로 이루어진 제 2 IMO(5)을 형성하고, 하부 금속 배선(2)이 노출되도록 상기 제 2 IMO(5), SOG막(4) 및 제 1 IMO(3)을 사진식각하여 비아홀을 형성하고, 비아홀 및 그에 인접된 제 2 IMO(5) 상에 상부 금속 배선(6)을 형성한다.Referring to FIG. 1B, a second IMO 5 made of SiO 2 is formed on the SOG film 4, and the second IMO 5, the SOG film 4, and the lower metal wiring 2 are exposed. The first IMO 3 is photo-etched to form a via hole, and the upper metal wiring 6 is formed on the via hole and the second IMO 5 adjacent thereto.
그러나, 상기와 같은 종래 기술은, 다량의 수분을 함유하고 있는 SOG 복합 수지 물질을 도포 및 큐어링할 때, 상기 SOG막에 함유된 수분이 제 1 IMO를 통과하여 하부 금속 배선을 부식시키는 문제점이 발생되고, 상부 금속 배선을 형성하기 위한 비아홀의 형성시 SOG막의 빠른 식각 속도로 인하여 언더 컷(under cut: 7)이 발생됨으로써, 소자의 신뢰성이 저하되는 문제점이 있었다.However, the prior art as described above has a problem in that when the SOG composite resin material containing a large amount of moisture is applied and cured, moisture contained in the SOG film passes through the first IMO to corrode the lower metal wiring. And an under cut (7) occurs due to the fast etching speed of the SOG film when the via hole for forming the upper metal wiring is formed, thereby lowering the reliability of the device.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 SiO2-Si3N4막으로 이루어진 제 1 IMO을 형성하는 평탄화 특성을 확보한 후, TEOS 산화막으로된 제 2 IMO을 형성함으로써, SOG막의 형성 공정을 생략하여 SOG막에 함유된 수분으로 인하여 금속 배선의 부식 및 비아홀의 결함이 발생되는 것을 방지할 수있는 반도체 소자의 제조 방법을 제공하는 것을 목적으로 한다.Therefore, in order to solve the above problems, the present invention ensures planarization characteristics of forming a first IMO made of SiO 2 -Si 3 N 4 film, and then forms a second IMO made of TEOS oxide film, thereby forming an SOG film. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the corrosion of metal wiring and the generation of defects in via holes due to the moisture contained in the SOG film by omitting the process.
도 1A 및 도 1B는 종래 기술에 다른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도.1A and 1B are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the prior art.
도 2A 내지 도 2C는 본 발명에 따른 반도체 소자의 제조 방법을 설명하기 위한 공정 단면도.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11: 반도체 기판12: 하부 금속 배선11: semiconductor substrate 12: lower metal wiring
13: 제 1 IMO14: 제 2 IMO13: first IMO14: second IMO
15: 상부 금속 배선15: upper metal wiring
상기와 같은 목적은, 하부 금속 배선이 형성된 반도체 기판 상에 1 IMO를 형성하는 단계; 상기 제 1 IMO를 평탄화시키는 단계; 상기 평탄화된 제 1 IMO 상에 제 2 아을 형성하는 단계; 하부 금속 배선이 노출되도록 상기 제 2 및 제 1 IMO를 사진식각하여 비아홀을 형성하는 단계; 및 상기 비아홀 및 그에 인접된 제 2 IMO 상에 상부 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 본 발명에 따른 반도체 소자의 제조 방법에 의하여 달성된다.The above object is to form a 1 IMO on the semiconductor substrate on which the lower metal wiring is formed; Planarizing the first IMO; Forming a second child on the planarized first IMO; Forming via holes by photolithography the second and first IMO to expose the lower metal lines; And forming an upper metal interconnection on the via hole and the second IMO adjacent thereto.
본 발명에 따르면, 평탄화막인 SOG막 형성 공정을 제거함으로써, 수분으로 인한 금속 배선의 부식 및 비아홀의 결함 발생을 방지할 수 있다.According to the present invention, by removing the step of forming the SOG film which is a planarization film, it is possible to prevent corrosion of the metal wiring and defect generation of via holes due to moisture.
[실시예]EXAMPLE
이하, 도 2A 내지 도 2C를 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to FIGS. 2A to 2C.
도 2A를 참조하면, 반도체 기판(11) 상에 통상의 방법으로 A1-1%Si 로 이루어진 하부 금속 배선(12)을 형성한 다음, 약 330 내지 370℃ 온도의 챔버내에 반응 가스로서 SiH4, NH3및 N2O를 주입하여 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방식으로 듀얼 프리컨시(Dual Frequency), 즉, 하이 프리컨시 및 로우 프리컨시를 이용하여 전체 상부에 약 1,800 내지 2,200Å 두께의 실리콘 옥시-나이트라이드(SiO2-Si3N4)로 이루어진 제 1 IMO(13)을 형성한다. 제 1 IMO(13)의 증착 온도를 약 330 내지 370℃로 하는 것은 하부 금속 배선(12)의 열적 스트레스로 인하여 입자 크기 및 비대화를 방지하기 위함이다.Referring to FIG. 2A, a lower metal wiring 12 made of A1-1% Si is formed on a semiconductor substrate 11 in a conventional manner, and then SiH 4 , as a reaction gas in a chamber at a temperature of about 330 to 370 ° C. Inject NH 3 and N 2 O and use dual frequency (Plasma Enhanced Chemical Vapor Deposition) PECVD, ie, high frequency and low frequency to apply about 1,800 to 2,200 Hz A first IMO 13 made of silicon oxy-nitride (SiO 2 -Si 3 N 4 ) of thickness is formed. The deposition temperature of the first IMO 13 is about 330 to 370 ° C. to prevent particle size and enlargement due to thermal stress of the lower metal wiring 12.
상기 PECVD 방식에 의한 실리콘 옥시-나이트라이드(SiO2-Si3N4)막은 실리콘 산화막에 비하여 평탄화 특성이 우수하기 때문에 증착 두께를 약 1,800 내지 2,200Å으로 하여 필요한 평탄화 특성을 막의 유동성에 의해 확보한다. 또한, 막의 응력은 하부 금속 배선(12)과 이후에 형성될 제 2 IMO의 응력 차이로 인하여 상기 제 1 IMO(13)에 균열이 발생되는 것을 방지하기 위하여 압축 응력을 -1.0×109dyne/㎠으로 조절한다.Since the silicon oxy-nitride (SiO 2 -Si 3 N 4 ) film by the PECVD method has superior planarization characteristics as compared to the silicon oxide film, the deposition thickness is about 1,800 to 2,200 kPa to secure the necessary planarization characteristics by the fluidity of the film. . In addition, the stress of the film has a compressive stress of −1.0 × 10 9 dyne / to prevent cracking in the first IMO 13 due to the difference in stress between the lower metal wiring 12 and the second IMO to be formed later. Adjust to cm 2.
도 2B를 참조하면, 챔버의 온도를 약 400℃ 정도로 하고, 약 1 분 동안 챔버 내의 압력을 200mTorr 이하의 진공 상태를 유지시켜 제 1 IMO(13)의 유동으로 인한 평탄화를 진행한다. 그리고 나서, 대기중의 수분 및 불순물로 인한 제 1 IMO(13)의 결함 발생을 최소화하기 위하여 인-시튜 방식으로 동일 챔버 내에 반응가스로서 TEOS 가스 및 O2가스를 주입하여 상기 제 1 IMO(13) 상에 TEOS 산화막으로된 제 2 IMO(14)를 증착한다. 이때, 제 2 IMO(14)의 증착 온도는 금속 배선의 특성을 변하시키지 않는 약 400℃ 정도로 하고, 증착 두께는 약 6,500 내지 7,500Å으로 하며, 증착과정에서 발생되는 응력은 압축 응력을 [-1.0±0.5]×109dyne/㎠로 조절하여 상·하부층의 응력차에 의한 균열을 방지한다.Referring to FIG. 2B, the chamber temperature is about 400 ° C., and the pressure in the chamber is maintained at a vacuum of 200 mTorr or less for about 1 minute to planarize due to the flow of the first IMO 13. Then, in order to minimize the occurrence of defects of the first IMO 13 due to moisture and impurities in the air, TEOS gas and O 2 gas are injected into the same chamber in the same chamber in an in-situ manner so that the first IMO 13 A second IMO 14 made of a TEOS oxide film is deposited on the C. At this time, the deposition temperature of the second IMO 14 is about 400 ° C., which does not change the characteristics of the metal wiring, and the deposition thickness is about 6,500 to 7,500 kPa, and the stress generated during the deposition process is a compressive stress [-1.0 It is adjusted to ± 0.5] × 10 9 dyne / cm 2 to prevent cracking due to stress difference between upper and lower layers.
도 2C를 참조하면, 하부 금속 배선(12)이 노출되도록 상기 제 2 IMO(14) 및 제 1 IMO(13)를 사진식갛여 금속 배선들 사이를 연결하기 위한 비아홀(도시되지 않음)을 형성한 후, 상기 비아홀 및 그에 인접된 제 2 IMO(14) 상에 상부 금속 배선(15)을 형성한다.Referring to FIG. 2C, the second IMO 14 and the first IMO 13 are photographic red so that the lower metal wiring 12 is exposed to form a via hole (not shown) for connecting between the metal wirings. Thereafter, an upper metal line 15 is formed on the via hole and the second IMO 14 adjacent thereto.
이상에서와 같이, 본 발명의 반도체 소자의 제조 방법은 평탄화막인 SOG막의 형성 공정을 생략함으로써, SOG막에 함유된 수분으로 인하여 금속 배선의 부식 및 비아홀의 결함이 발생되는 것을 방지할 수 있으며, SOG막 대신에 PECVD 방식으로 실리콘 옥시-나이트라이드 및 TEOS 산화막을 인-시튜 방식으로 증착함으로써, 평탄화 특성이 저하되는 것을 방지하여 토폴로지로 인한 단선 문제를 방지할 수 있다.As described above, in the method of manufacturing the semiconductor device of the present invention, the step of forming the SOG film, which is a planarization film, may be omitted, thereby preventing corrosion of metal wiring and defects of via holes due to moisture contained in the SOG film. By in-situ depositing the silicon oxy-nitride and the TEOS oxide film by PECVD instead of the SOG film, the planarization property can be prevented from being lowered to prevent the disconnection problem due to the topology.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960072798A KR100434713B1 (en) | 1996-12-27 | 1996-12-27 | Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960072798A KR100434713B1 (en) | 1996-12-27 | 1996-12-27 | Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980053670A true KR19980053670A (en) | 1998-09-25 |
| KR100434713B1 KR100434713B1 (en) | 2004-09-01 |
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| KR1019960072798A KR100434713B1 (en) | 1996-12-27 | 1996-12-27 | Method of manufacturing semiconductor device with corrosion-free metal line and defect-free via hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH03190232A (en) * | 1989-12-20 | 1991-08-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR910013464A (en) * | 1989-12-30 | 1991-08-08 | 김광호 | Contact hole formation method for multilayer wiring |
| JPH03255630A (en) * | 1990-03-05 | 1991-11-14 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH0697162A (en) * | 1992-09-16 | 1994-04-08 | Fuji Electric Co Ltd | Deposition of planarization film for integrated circuit device |
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