JPH03255630A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the short circuit between the first layer wiring and the second layer wiring provided on the second interlayer insulating film for enhancing the reliability of a semiconductor device by bumps by a method wherein the first interlayer insulating film higher than the bumps formed on the first layer wiring is formed and then said insulating film is flattened in the bump coated state so as to form the second interlayer insulating film on the first interlayer insulating film. CONSTITUTION:A semiconductor substrate 11 including the first layer wiring 12 is coated with the first interlayer insulating film 13. At this time, the substrate 11 is simultaneously coated with alumihillock 18 whose level is lower than that of the first interlayer insulating film 13. Successively, the first interlayer insulating film 13 is coated with a sacrifice film 14. Next, the sacrifice film 14 and the first interlayer insulating film 13 are etched away at the equal etching rate. Then, the surface of the first interlayer insulating film 13 is flattened in the bump coated state with the film 13 further to form the second interlayer insulating film 15 on the first interlayer insulating film 13. Finally, a contact hole 16 is formed in the first interlayer insulating film 13 and the second interlayer insulating film 15 using the photolithographic and etching technologies so as to form the second layer wiring 17.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which an interlayer insulating film is formed.

<Prior Art> A conventional method for manufacturing a semiconductor device will be explained with reference to the process diagram shown in FIG.

As shown in FIG. 3(I), a first layer wiring 12 is provided on a semiconductor substrate 31 on which semiconductor elements (not shown) such as transistors are formed.

Next, as shown in FIG. 3(II), the first layer wiring 32
an interlayer insulating film 3 that covers the semiconductor substrate 31 and has a thickness thicker than that of the first layer wiring.
form 3. This interlayer insulation @33.

It is formed from silicon oxide by CVD method or the like.

Subsequently, a sacrificial film 34 shown in FIG. 3(m) is formed on the interlayer insulating film 33. This sacrificial layer 11i34 is formed of resin such as photoresist or spin coating glass (SOG), and covers the unevenness of the interlayer insulation M33 to flatten the surface.

Next, the sacrificial film 34 is completely removed under etching conditions such that the etching rates of the interlayer insulating film 33 and the sacrificial film 34 are approximately equal. Then, an interlayer insulating film 33 having a flat surface shown in FIG. 3(IV) is obtained. The height of the living room insulating film 33 at this time is made to be approximately the same height as the thickness of the interlayer insulating film 33 on the semiconductor substrate 31 shown in FIG. 1(H) described above.

Next, a contact hole 36 shown in FIG. 3(V) is formed at a predetermined position in the interlayer insulating film 33 using photolithography and etching techniques.

Further, as shown in FIG. 3(VI), a second layer wiring 37 is formed on the interlayer insulating film 33.

Further, another manufacturing method will be explained with reference to the process diagram shown in FIG.

As shown in FIG. 4(IV), a first layer wiring 42 is formed on a semiconductor substrate 41, and a first interlayer insulating film 43 is further formed. Subsequently, a sacrificial film 44 is formed on the first interlayer insulating film 43, and its surface is flattened.

- First layer wiring 42. The method for forming the first interlayer insulating film 43 and the sacrificial film 44 is shown in FIGS.
), so the explanation will be omitted.

Subsequently, the first interlayer insulation IPJ 43 and the sacrificial film 44 are
The first etching rate is approximately equal to that of the first etching rate.
The interlayer insulating film 43 and the sacrificial W 244 are etched. This etching is performed until the surface of the first layer wiring 42 and the surface of the first interlayer insulating film 43 become flush, as shown in FIG. 4(IV).

Next, as shown in FIG. 4(V), a second interlayer insulating film 45 is formed on the first layer wiring 42 and the first interlayer insulating film 43. Then, as shown in FIG. The second interlayer insulating film 45 may be formed of the same type of insulating film as the first interlayer insulating film 43, or may be formed of a different type of insulating film.

Next, a contact hole 46 shown in FIG. 4 (VI) is formed at a predetermined position in the second interlayer insulating film 45 using photolithography and etching techniques.

Furthermore, as shown in FIG. 4 (■), a second layer wiring 47 is formed on the second interlayer insulating film 45.

<Problems to be Solved by the Invention> However, in the former manufacturing method described in the prior art described above, as shown in FIG.
If the first layer wiring 32 has a protrusion 38 grown thereon, when the interlayer insulating film 33 is etched, the protrusion 38 will be removed.
The tip of 8 protrudes above the living room insulating film 33.

Furthermore, when the second layer wiring 37 shown in FIG. 5(b) is formed on the interlayer insulating film 33, the first layer wiring 32 and the second layer wiring 37
A short circuit occurs through the protrusion 38.

The incidence of short circuits in this case was 80%.

On the other hand, in the latter manufacturing method, as shown in Figure 6 (a),
If a protrusion 48 is formed on the first layer interconnect 32 by growing the first layer interconnect 42 , the second interlayer insulating film 45 covers the protrusion 48 . At this time, the protrusion 48 further grows due to the heat generated during the formation of the second interlayer insulating film 45, and the convex portion 49 of the second interlayer insulating film 45 covering the protrusion 48 becomes larger.

Next, as shown in FIG. 6(b), a contact hole 46 is formed in the second living room insulating film 45 by photolithography and etching.

At this time, the convex portion 49- cannot be completely covered by an etching mask (not shown) formed by photolithography. Therefore, during etching, the tip of the convex portion 49 is etched to form a small hole 50.

When the second layer wiring 47 shown in FIG. 6(c) is formed, the first layer wiring 42 and the second layer wiring 47 are short-circuited via the protrusion 48.

The incidence of short circuits in this case was 30%.

Therefore, the reliability of the semiconductor device decreases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device with excellent reliability.

<Means for Solving the Problems> The present invention has been made to achieve the above object, that is, a first interlayer insulating film is formed on a semiconductor substrate including wiring at a height higher than the height of a protrusion formed on the wiring. In this method, the first interlayer insulating film is flattened while covering the protrusion, and the second interlayer insulating film is formed thereon.

<Function> The method for manufacturing the wiring structure of a semiconductor device described above includes flattening the covered surface while covering protrusions on the wiring with the first interlayer insulating film or the first interlayer insulating film and the sacrificial film. Since the first interlayer insulating film presses down the protrusion, growth of the protrusion due to heat during formation of the second interlayer insulating film is prevented.

Furthermore, since the second interlayer insulating film is formed flat, it is possible to prevent short circuits between the wiring provided on the second interlayer insulating film and the previously formed wiring or projections.

<Example> An embodiment of the present invention will be explained with reference to the process diagram shown in FIG.

Further, various numerical values used in the explanation are given as examples, and the present invention is not limited to these numerical values.

f31 As shown in Figure (1), a first scrap wiring (wiring) 12 is provided on a semiconductor substrate 11 on which semiconductor elements (not shown) such as transistors are formed. Said first layer distribution! Ja12 is
It is formed of an aluminum alloy (aluminum [AI] - 1% silicon [Si Miko, 5% copper [Cu]) or the like, and is formed to have a film thickness of 600 nm. When forming this first layer wiring 12, aluminum hillocks (protrusions) 18 may occur.

Next, as shown in FIG. 1(2), the semiconductor substrate 11 including the first layer wiring 12 is covered with a first interlayer insulation layer 913. The first interlayer insulating film 13 is formed of silicon oxide [5i02] by the CVD method. At this time, the aluminum hillock 18 is covered and the film thickness is set to 1.00 g so that the surface height of the first interlayer insulation M13 is higher than the height of the aluminum hillock 18.

Subsequently, the first interlayer insulation gl:l is covered with a sacrificial film 14 shown in FIG. 1(3). Said sacrifice! Reference numeral 114 is a material made of a hardened viscous fluid, which is made by coating and hardening spin coating glass (SOG). Alternatively, a resin such as a resist may be applied and cured. Therefore, the sacrificial material 814 flattens the unevenness of the first living room insulating film 13 by utilizing its fluidity during application.

Next, the sacrificial film 14 and the first interlayer insulating film 13 are etched under the conditions that the sacrificial film 14 and the first interlayer insulating film 13 are etched at a constant rate. The etching conditions are, for example, a mixed gas of hexafluoroethane [C2F6] and oxygen [02] is used as the etching gas, and the C2F6 flow rate is:
The flow rate is 1Oscc, the pressure in the reaction chamber is 260Pa, and the RF power is 600W.

Then, as shown in FIG. 1(4), the first interlayer insulating film 1
3, the surface of the first interlayer insulating film 13 is leveled.

Next, a second interlayer insulating film 15 shown in FIG. 1(5) is formed on the first interlayer insulating film 13. The second interlayer insulating film 15 is made of silicon oxide [5 iOz] by CVD method.
It is formed to have a thickness of M or 400 nits.

Further, it may be formed of an insulator other than SiO□.

Subsequently, as shown in FIG. 1(6), the first interlayer insulation l is formed by photolithography and etching techniques.
A contact hole 16 is formed between the contact hole 113 and the second interlayer insulating film 15 .

Next, the second layer wiring 17 shown in FIG. 1(7) is formed.

The second layer wiring 7 is formed of the same material as the first layer wiring 12. Further, it may be formed of other conductive materials.

In the above manufacturing method, the first
Short circuits between layer wiring 12 and second layer wiring 17 can be reduced to 1% or less.

Furthermore, if the first interlayer insulating film 13 is formed to be thicker than necessary, it will not be formed to have a uniform thickness with respect to the first layer wiring 12, as shown in FIG. Therefore, a cavity 19 is formed, which impairs the flatness of the first interlayer insulating film 13 after constant speed etching. Therefore, it is not preferable to make the film thicker than necessary.

<Effects of the Invention> As described above, according to the present invention, the first interlayer insulating film is formed higher than the height of the protrusions formed in the wiring, and the first interlayer insulating film is flattened while covering the protrusions. Since the second interlayer insulating film is formed on the second interlayer insulating film, the protrusion prevents short circuit between the wiring and the wiring provided on the second interlayer insulating film.

The reliability of semiconductor devices can be significantly improved.

[Brief explanation of drawings]

Fig. 1 is a process explanatory diagram of the embodiment; Fig. 2 is an explanatory diagram of defects in the first interlayer insulating film; Fig. 3 is a conventional process explanatory diagram; and Fig. 4 is a process explanatory diagram of another conventional example. Figures 5 and 6 are explanatory diagrams of the problem. 11... Semiconductor substrate, 12... First layer wiring. 13... First interlayer insulating film, 14... Sacrificial film. 15...Second interlayer insulating film. 18...Aluminum hillock (protrusion).

Claims (1)

[Scope of Claims] A step of forming wiring on a semiconductor substrate on which a semiconductor element is formed, covering the semiconductor substrate including the wiring with a first interlayer insulating film, and controlling the height of a protrusion formed on the wiring. forming the first interlayer insulating film to a thickness such that the surface of the first interlayer insulating film is higher than that of the first interlayer insulating film; and covering the first interlayer insulating film with a sacrificial film; a step of flattening the surface of the first interlayer insulating film; a step of etching the sacrificial film and the first interlayer insulating film at a substantially constant rate while the protrusion is covered with the first interlayer insulating film; A method for manufacturing a semiconductor device, comprising the step of forming a second interlayer insulating film on a surface etched at a constant rate.