JPH0258836A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device excellent in closely filled up reliability and capable of high integration when the second insulating films are formed by a method wherein the first insulating films are processed so that the normals on the surface of the first insulating film at slopes may make specific angles with the normals of the main surface of a substrate. CONSTITUTION:A substrate is arranged in a dryetching device, where mixed gas of CH4 and Ar is introduced to etch away SiO2 films 6 by plasma for forming SiO2 films 8. At this time, the SiO2 films 6 can be anisotropically etched away by CF4 gas while etching the SiO2 films 6 by Ar gas making an angle of 45 deg. so that the SiO2 films 8 in the gaps between Al wirings 4A-4C may be etched away making an angle of 60 deg.-85 deg. down to the gap bottoms. Later, the other SiO2 film 10 as the second insulating film is deposited. At this time, the SiO2 films 8 are provided with no sides making angles perpendicular to or exceeding the same with the main surface of the substrate so that the gaps of Al wirings 4 (4A-4C) having the aspect ratio exceeding one may be closely filled with the SiO2 film 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used as an interlayer insulating film in multi-layer interconnections for highly integrated ultra-LSIs, etc., and is effective for depositing an insulating film on a substrate having fine irregularities. The present invention relates to a method of manufacturing a semiconductor device.

BACKGROUND ART As the degree of integration of LSI increases, a technique of stacking interconnects in multiple layers is used, and it is necessary to bury an insulating film between fine interconnects and to form a flat interlayer insulating film. Therefore, conventionally, various studies have been made on embedding an insulating film such as an Sio2 film between fine interconnections using a vapor phase growth method (hereinafter referred to as CVD method). For example, as shown in Figure 4,
In the fourth (NA), an A1 wiring pattern 102 (102A to 102(2)) is formed on a Si substrate 100, and oxygen is added by plasma CVD using an organic oxysilane such as tetraethoxysilane (TE01) as a raw material gas. The reaction is carried out to deposit a 5in2 film 104. As shown in the above example, the SiO2 film using organic oxysilane has less overhang (and has good step coverage) compared to the 5in2 film made by the reaction of silane gas. Therefore, it is suitable for filling wiring gaps. [For example, VLS I Multilevel Interconnection Conference (I
E E E VM I (2) June15-16
．． 1987 M, J, Th.

ma″A 1.0μmCMO8LEVEL METAL
TECtlNOLOGY lNC0RPORATI
NG PLASMA ENHANCED TE0
1”] In other examples, as shown in FIG. 5, AI wiring patterns 102 (102A to 102(
2) is formed by a plasma reaction between TE01 and TE02, and then the corners of the SiO□ film 104 are etched at an angle of 45° by Ar sputtering to form a Sr02 film 105. obtain. And again T
Due to the plasma reaction of E01 and 02, the SiO2 film 106
is deposited to form an interlayer insulating film. In this way, finer gaps can be filled by etching the corners of the SiO2 film at an angle of 45° using Ar sputtering (Electronic Materials, September 1987, P, 116-P,
122rPREcIsION5000 CV D and its functions).

Problems to be Solved by the Invention However, the conventional manufacturing method shown in FIGS. 4 and 5 has the following problems.

It is not possible to fill minute interconnect gaps, especially those with an aspect ratio of 1 or more. In other words, in the example shown in Fig. 4, TE01
The SiO2 film produced by the plasma CVD method using SiO2 as a raw material has a characteristic of having little overhang, but since the film thickness at the flat part is about twice as thick as the film thickness in the concave part, the aspect ratio of the gap is 0. If the number is 8 or more, voids 108 (108A to 108B) will occur as shown in FIG. 4B.

In addition, as shown in FIG. 5, 5i
Even in the example where the corners of the N2 film 104 are etched at an angle of 45°, if the aspect ratio of the AI wiring gap becomes 1 or more, the AI wiring 102 (
102A to 102(2) When the surface is not directly sputtered with Ar, 31
02 film 104 cannot be etched. Therefore, when the 5i02 film 106 is deposited, voids 108 (108A to 108B) are generated as shown in FIG. 5C.

In view of these conventional problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that solves these problems, has excellent manufacturing yield and reliability, and enables high integration.

Means for Solving the Problems The present invention provides a method for forming a first insulating film on a semiconductor substrate having a small portion of the surface having an inclined portion whose normal line makes an angle of 80” or more with the normal to the surface of the substrate. a first step of forming the first insulating film, and etching a part of the first insulating film so that the normal to the surface of the insulating film in the inclined portion forms an angle of 60'' to 85° with the normal to the principal surface of the substrate; This method of manufacturing a semiconductor device is characterized by comprising a second step of forming a second insulating film on the first insulating film by a vapor phase reaction.

For production With the above configuration, the present invention operates as follows.

(1) By processing the first insulating film so that the normal to the surface of the first insulating film in the inclined part forms an angle of 60° to 85° with the normal to the main surface of the substrate, the second insulating film is When formed, gaps with an aspect ratio of 1 or more can be filled with voids.

(2) Since minute gaps can be filled without creating voids, the process of planarizing the surface of the semiconductor substrate becomes easier, and the formation of upper layer wiring becomes easier.

Further, disconnection of the lower layer wiring can be prevented.

(3) By combining the step of forming an insulating film by a thermal decomposition reaction of organic oxysilane and the step of forming an insulating film by a plasma decomposition reaction, it is possible to easily fill the insulating film into minute recesses.

Example Example 1 Hereinafter, the manufacturing method of the present invention will be explained based on specific examples.

FIGS. 1A to 1C show a process for forming an interlayer insulating film for two-layer interconnection, which is a manufacturing process according to an embodiment of the present invention. Circuit elements are formed on the semiconductor Si substrate 2 shown in FIG. The formed substrate was placed in a plasma CVD apparatus, the substrate temperature was maintained at 390°C, a mixed gas of TEOS and 02 was introduced, and the degree of vacuum was reduced to I.
Blasm is generated in a Q Torr state, and a 0.6 μm thick SiO2 film 6 is deposited as a first insulating film. Thereafter, as shown in FIG. 1B, the substrate indicated by A above was placed in a dry etching apparatus, a mixed gas of CF4 and Ar was introduced, and the degree of vacuum was 0.05 T.

Plasma is generated in the state of rr, and the 5i02 film 6 is heated to 0.3μ.
A SiO2 film 8 is obtained by etching. At this time, A
The A1 wiring (4A to 4(2)
) in the gap, the membrane 8 is 60" to 8" to the bottom of the gap.
It can be machined to have an inclination of 5°. After that, as shown in Fig. 1C, the substrate indicated by B above was placed in a plasma CVD apparatus, the substrate temperature was maintained at 390°C, a mixed gas of TEOS and 02 was introduced, and the degree of vacuum was increased to 10T.
Plasma is generated in the orr state, and a 0.5 μm thick SiO2 film 10 is deposited as a second insulating film. At this time, Si
n,, the film 8 has an inclination of 60° to 85° to the bottom of the gap and does not have side surfaces that are perpendicular to the main surface of the substrate or at an angle greater than 1, so the aspect ratio is 1 or more due to the SiO2 film 10. The gap between the A1 wiring 4 (4A to 4(2)) can be filled as a void.

Note that similar results can be obtained by using SiH4 and O2 or SiH4 and N20 instead of TEOS and 02 in the plasma CVD for forming the first insulating film. In addition, in the above dry etching, C instead of CF4 is used.
Similar results are obtained using HF3. Furthermore, in the plasma CVD for forming the first and second insulating films, tetramethoxysilane [S i (
Similar results can be obtained using OCH3)4].

It goes without saying that (in the process of etching the SiO2 film 6 to obtain the S+02 film 8, the inclination of the 5in2 film 8 in the gap between the AI interconnections with respect to the main surface of the substrate is 85°.
The closer it is, the finer the AII line gaps can be filled without any voids. Also, in this etching process, A
1 placement &! J14 (4A~4(2) Do not expose the surface directly to Ar plasma atmosphere (5in2 to the bottom of the gap)
Since the film 8 can be sloped, the A
rNo damage caused by plasma.

Furthermore, in the above embodiment, a case was described in which an interlayer insulating film was formed on an AII line having a side surface substantially perpendicular to the main surface of the substrate. However, in the manufacturing method of the above embodiment, the AI wiring is A similar effect can be obtained even when the side surface has an angle of 90° or more.

Embodiment 2 Referring to FIG. 1, the process of forming an interlayer insulating film for two-layer wiring in a second manufacturing process embodiment of the present invention will be described.

In FIG. 1A, a circuit element is formed on a Si substrate 2, and has a side surface substantially perpendicular to the main surface of the substrate.

First A! A 5in2 film 6 as a first insulating film is deposited to a thickness of 0.6 μm on the substrate on which the wirings 4 (4A to 4(2)) are formed using the plasma CVD method in the same manner as in Example 1. Then, as shown in FIG. As shown in FIG.
The in2 film 6 is etched by 0.3 μm from 60° to 85°.
A SiO film 8 having an angle of .degree. is obtained. After that, the first
As shown in Figure C, the substrate is placed in a thermal CVD apparatus, the substrate temperature is maintained at 390°C, a mixed gas of TEOS and 03 is introduced, and the second insulating film is formed by thermal reaction at a vacuum level of 60 Torr. A film 10 of 0.5 μm of Sin is deposited to fill the gap between the Al interconnects 4.

Note that in the thermal CVD for forming the second insulating film,
Tetramethoxysilane (S i (
Similar results are obtained using OCH3)4).

Embodiment 3 Using FIG. 2, the process of forming an interlayer insulating film for two-layer wiring in the manufacturing process of a third embodiment of the present invention is shown.

In FIG. 2A, a circuit element is formed on a Si substrate 2, and a first Al wiring 4 (4
A 5in2 film as a first insulating film was formed on the substrate on which A to A4(2) was formed using the plasma CVD method in the same manner as in Example 1.
A film 6 is deposited to a thickness of 0.6 μm. Thereafter, as shown in FIG. 2B, a resist film 7 is applied onto the substrate to a thickness of about 1.5 μm to flatten the surface of the substrate. After that, the substrate is placed in a dry etching device, 02 gas is introduced, and the degree of vacuum is set to 0. Plasma is generated under the condition of I Torr, and the resist III 7 is etched by 1.5 μm, and as shown in FIG.
(7A to 7D) are formed. After that, as shown in the second diagram, the substrate is placed in a dry etching device and heated to zero.
A mixed gas of 2F6 and 02 is introduced, and the vacuum level is 2 Torr.
Plasma is generated in this state, and the resist film 7 (7A to 7
D> and the SiO2 film 6 is etched to obtain the SiO2 film 8. At this time, resist 1I7 (
By isotropically etching the SiO2 film 6 with a mixed gas of 02F6 and 0° while etching the Al wirings 4 (4A to 4(2)),
The in2 membrane 8 can be machined to have an inclination of 60'' to 85 degrees to the bottom of the gap.

At this time, no side surface perpendicular to the main surface of the substrate remains in the 5i02 film 8. Thereafter, as shown in FIG. 2E, a 5in2 film 10 serving as a second insulating film is deposited to a thickness of 0.5 μm using the plasma CVD method as in Example 1, and the gap between the Al wirings 4 is filled.

In Example 3, instead of forming the second insulating film by plasma CVD using TEOS and 02, the second insulating film was formed by thermal CVD using TEOS and 03 as in Example 2.
A similar result can be obtained even if the second insulating film is formed by the method.

Embodiment 4 Using FIG. 3, a process for forming an interlayer insulating film for two-layer wiring in the manufacturing process of a fourth embodiment of the present invention will be described. Figure 3 A and S
A circuit element is formed on the i-board 2, and first Al wiring 4 (4A to 4(2)) having a side surface substantially perpendicular to the main surface of the board is formed.
Using the plasma CVD method in the same manner as in Example 1, Si○2io as the first insulating film was deposited on the substrate on which 0.6
μm deposits. Thereafter, as shown in FIG. 3B, the S102 film 6 was etched by 0.3 μm by dry etching using Ar and fluoride gas as in Example 1 to form an inclination of 60° to 85°. A Si02 film 8 having the following properties is obtained. Next, as shown in FIG. 3C, as in Example 2, 5i
An N2 film 9 was deposited to a thickness of 0.2 μm, and the Al wiring 400.8
Fills gaps of μm or less. Then, as shown in the third diagram, a SiO2 film 10 of 0.3 μm is deposited by plasma CVD using a mixed gas of TEOS and O2 as in Example 1. At this time, the 5in2 film 9 produced by thermal reaction of TEOS has better step coverage than the SjO2 film 1O produced by plasma reaction of TEOS, and is suitable for filling gaps of 1 μm or less. However, the S io 2 film 9 due to the thermal reaction of TEOS has poor film quality (and thickness).
The generation of cracks can be prevented by depositing the 5in2 film 10 by EOS plasma reaction. Furthermore, the deposition rate of the 5i02 film due to the thermal reaction of TEOS is 0.2 μm/in, whereas the deposition rate of the Sin film due to the plasma reaction of TEOS is 0.8 μm/in.
/min, so throughput can be improved. Further, by appropriately selecting the SiO2 film thickness due to the thermal reaction of the TEOS and the 5i02 film thickness due to the plasma reaction of the TEOS and repeating these steps, it is possible to fill the gap of the A1 wiring 4 of any size. can.

In Example 4, instead of etching the SiO2 film 6 to have an inclination of 60 to 85 degrees by dry etching using Ar and fluoride gas,
Similar results can be obtained by forming a resist film in the recesses on the SiO2 film 6 and then etching the SiO2 film 6 by dry etching using O2 and fluoride gas as in Example 3.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

The first insulating film formed in the gap is 60 to 85 mm deep to the bottom of the gap.
By etching so that no side surfaces perpendicular to the main surface of the substrate remain, it is possible to fill minute gaps with an aspect ratio of 1 or more without any voids when forming the second insulating film. Can be done.

Since it is possible to fill minute gaps without creating voids, the planarization process of the semiconductor substrate surface is facilitated, and when applied to the formation of interlayer insulating films for multilayer interconnections, the format of upper layer interconnections can be prepared. In addition, disconnection of lower-layer wiring can be prevented.Furthermore, by realizing multilayer wiring, higher integration and higher speed of elements can be achieved.

By combining the step of depositing an insulating film using a thermal decomposition reaction of organic oxysilane and the step of depositing an insulating film using a plasma decomposition reaction, it is possible to easily fill the insulating film into minute recesses.

As described above, the present invention makes it possible to embed an insulating film into minute recesses without creating voids, and thus greatly contributes to higher integration and improved reliability of devices.

[Brief explanation of the drawing]

Embodiment 1 of the method for manufacturing a semiconductor device according to the present invention is shown in FIG.
FIG. 2 is a process cross-sectional view for explaining Example 3 of the manufacturing method according to the present invention,
FIG. 3 is a process sectional view for explaining Embodiment 4 of the manufacturing method according to the present invention, FIG. 4 is a process sectional view for explaining an example of the conventional manufacturing method, and FIG. FIG. 7 is a process cross-sectional view for explaining another example of the method. 2...Si substrate, 4A, 4B, 4C,...
・・AI wiring, 6, 8, 9.10・・・・・・CVD-
3in2 membrane, 7.7A, 7B, 7C,? D...
resist film. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 7.7/4.7B, 7Q-Regis 14 Figure 8-CVD-Rice 0?, 10-CVD-Σ10♂(, Dropped) which ridge layer υ
Regret

Claims (4)

[Claims] (1) a first step of forming a first insulating film on a semiconductor substrate having, on at least a portion of the surface, an inclined portion whose normal line makes an angle of 80° or more with the normal to the main surface of the substrate; 1
a second step of etching a part of the insulating film so that the normal to the surface of the insulating film in the inclined portion forms an angle of 60° to 85° with the normal to the principal surface of the substrate; A method for manufacturing a semiconductor device, comprising a third step of forming a second insulating film on the insulating film by a gas phase reaction. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the second step is etching the first insulating film in plasma containing argon gas and fluoride gas. (3) The second step is characterized in that the first insulating film is etched in plasma containing oxygen and fluoride gas after a resist is formed in the recessed portion of the first insulating film. A method of manufacturing the semiconductor device described above. (4) In the third step of forming the second insulating film, the thermal decomposition reaction of organic oxysilane and ozone is at least one of the plasma decomposition reactions due to plasma generation between organic oxysilane and oxygen, or one of the above two reactions. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step is to repeatedly form an insulating film.