JPH09199503A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use a Cu wiring which can be subjected to a precision processing without oxidizing the Cu wiring. SOLUTION: A PE-TEOS film 22 is deposited on a Cu film 21 by a plasma CVD method using the mixture of TEOS(tetraethoxysilane) gas and oxygen gas and the PE-TEOS film 22 is patterned. The Cu film 21 and a barrier film 14 are etched by an RIE method (a high temperature etching method) by using the patterned PE-TEOS film 22 as a mask to form a Cu wiring 23. Then a PE-TEOS film 24 which covers the Cu wiring 23 is deposited. With this constitution, a semiconductor device which uses Cu wirings and has a high integral rate can be manufactured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device that uses finely processed copper wiring without oxidizing the copper wiring and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become more highly integrated and the constituent elements have become finer, and wiring between these constituent elements and the like has become multi-layer wiring using a reduction in wiring width and a flattening technique. Is required. Conventionally, the wiring of the semiconductor integrated circuit is A
1 alloy film, for example, an Al alloy film containing 1% Si, an Al alloy film containing 1% Si and 2% Cu, etc. have been used. In the recent semiconductor integrated circuits, there are problems in wiring reliability due to problems of electromigration and stress migration, and it is becoming difficult to use the Al alloy film. On the other hand, the wiring resistance itself by the Al alloy film has become a problem with the increase in the speed of the semiconductor integrated circuit, and if the Al alloy film thickness is increased in order to reduce the resistance itself of the Al alloy film wiring, then the fine processing is performed. The above problem comes up.

In order to solve the above problems, copper (C
In recent years, technical development of copper wiring using u) as a wiring material has been actively carried out. The resistivity of Cu is about 1.4 μΩ · cm,
The resistivity of Al is about half of 2.9 μΩ · cm, and Cu
Since the wiring has a higher resistance to electromigration and stress migration than the Al wiring film, the use of Cu wiring makes it possible to obtain a highly reliable semiconductor integrated circuit with high reliability.

However, there are the following two problems when using Cu wiring in a semiconductor integrated circuit. One is Cu
The wiring is easily oxidized, and oxygen diffuses into the Cu wiring due to heat treatment in an oxidizing atmosphere or the like, and the Cu wiring resistance gradually increases, so that a desired low resistance Cu wiring cannot be obtained. Another problem is the reactive ion etching (R
The problem is that it is difficult to form Cu wiring using the IE) method. The reason for this is that since the halide of Cu produced by etching in the RIE method, which is usually used for microfabrication, has a high gasification temperature, about 400 ° C. is required.
This is because the heat resistance of the photoresist is exceeded.

As a Cu wiring technique for solving the above problems, there are currently two methods, a high temperature etching method and a damascene method. The high temperature etching method is a method of etching a substrate to be processed at the time of etching using an inorganic material mask that can withstand high temperature as a mask for RIE at the time of forming Cu wiring. This inorganic material mask has an inorganic material film C
It is necessary that the Cu deposition film is not oxidized when it is formed on the Cu deposition film to be the u wiring, and that the etching selection ratio is sufficient when the Cu deposition film is etched by RIE or the like. An example of such an inorganic material mask is a SiO ₂ film formed by a sputtering method. However, the film formation by this sputtering method is liable to generate dust, and it is difficult to obtain a good quality inorganic material mask film.
Further, after forming the Cu wiring, a protective film for preventing oxidation of the Cu wiring from the side wall of the Cu wiring must be formed without oxidizing the Cu wiring.

On the other hand, the damascene method is a method capable of forming fine wirings without the need to form wirings by the RIE method in which a substrate to be processed is heated to a high temperature unlike the above-mentioned high temperature etching method. It is under consideration. As shown in FIG. 3A, the Cu wiring forming method using the damascene method is performed by the RIE method using a photoresist as a mask at a predetermined position of the Cu wiring forming of the interlayer insulating film 12 deposited on the semiconductor substrate 11. , The groove 13 is formed, and then the barrier film 14 is formed by the Ti film and the TiN film by the collimating sputtering method.
Or T by MOCVD method using organic Ti material
The barrier film 14 is formed of an iN film. Next, Cu film 1
5 is deposited by the CVD method.

Next, as shown in FIG. 3B, an etchback method or a CMP (Chemical Mechanical) method is used.
The barrier film 14 and the Cu film 15 on the interlayer insulating film 12 are removed by a vertical polishing (N.
Cu wiring 16 is formed in the third portion. According to this damascene method, it is not necessary to form a fine Cu wiring by etching the Cu film by RIE or the like, and the fine processing is performed only by forming it on the interlayer insulating film by an ordinary photolithography technique.
u wiring can be formed. After that, an SiN film 17 for preventing oxidation of the Cu wiring 16 is deposited, and then an interlayer insulating film 18 is deposited. After that, although illustration is omitted, a buried plug or Cu wiring by the same damascene method as described above is formed in the interlayer insulating film 18 to manufacture a semiconductor device having a multilayer wiring structure. However, this method has a point that a uniform Cu film can be formed in the groove 13, and if a void is generated in the groove 13 or the growth of the Cu film in the groove 13 is uneven, the cross-sectional area of the Cu wiring is reduced. There is a possibility that different portions may be formed, wiring resistance may increase, and reliability problems may occur.

Both of the above two Cu wiring forming methods have a problem that it is difficult to form a fine Cu wiring without oxidizing the Cu wiring.

[0009]

The present invention is based on the above-mentioned Cu.
It is an object of the present invention to solve a problem in a semiconductor device using wiring. That is, an object of the present invention is to provide a semiconductor device using Cu wiring that can be finely processed without oxidizing the Cu wiring.

[0010]

A semiconductor device and a method of manufacturing the same according to the present invention are proposed to solve the above-mentioned problems, and the semiconductor device according to claim 1 is a semiconductor device using copper wiring. And a copper wiring on the interlayer insulating film of the semiconductor substrate and an oxide film formed on the copper wiring by a plasma CVD method using an organic silane-based gas.

A semiconductor device according to a second aspect of the present invention is characterized in that it has an oxide film which covers the copper wiring and is formed by a plasma CVD method using an organic silane-based gas.

According to a third aspect of the present invention, there is provided a semiconductor device having a protective film formed by a plasma CVD method using an organic silane-based gas, the protective film covering copper wiring, and a low dielectric constant film on the protective film. It is a thing.

A semiconductor device according to a fourth aspect is characterized in that the oxide film is an oxide film formed by a plasma CVD method using a tetraethyl orthosilicate gas.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device using a copper wiring, wherein a step of forming a copper film on an interlayer insulating film of a semiconductor substrate and an organosilane gas on the copper film. A step of depositing an oxide film by a plasma CVD method using, a step of patterning the oxide film, a step of etching the copper film by reactive ion etching using the oxide film as a mask to form a copper wiring, and a copper wiring And a step of depositing an oxide film by a plasma CVD method using an organic silane-based gas.

A method of manufacturing a semiconductor device according to a sixth aspect is characterized by including a step of depositing an oxide film covering a copper wiring by a plasma CVD method using an organic silane-based gas.

According to a seventh aspect of the method of manufacturing a semiconductor device, a step of depositing a protective film for covering copper wiring by a plasma CVD method using an organic silane gas, and a step of forming a low dielectric constant film on the protective film. It is characterized by having.

The method of manufacturing a semiconductor device according to claim 8 is characterized in that the organic silane-based gas is tetraethyl orthosilicate gas.

The basis of the present invention is that Cu wiring is formed by a high temperature etching method, and when Cu wiring is formed by the RIE method, an organic silane-based gas such as TEOS (Tetraethyl) is used.
Plasma CVD SiO ₂ film (PE-TE) using a mixed gas of an Orthosilicate gas and an O ₂ gas.
That is, the OS film) was used as an inorganic material mask during etching. After etching the Cu film, PE-
The TEOS film covers the side wall and the upper surface of the Cu wiring.
Since this PE-TEOS film can be formed with almost no oxidation of the Cu wiring at the time of film formation, the Cu wiring can be formed by the high temperature etching method using the inorganic material mask of this film without oxidizing the Cu wiring. Therefore, it is possible to form a fine Cu wiring.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings. The same components as those in FIG. 3 referred to in the description of the prior art are denoted by the same reference numerals.

Example 1 This example is an example in which the present invention is applied to a semiconductor device and a method of manufacturing the same, which will be described with reference to FIGS. 1 (a) to 1 (c). First, as shown in FIG. 1A, an interlayer insulating film 12 having a film thickness of about 600 nm is formed on a semiconductor substrate 11 on which elements constituting a semiconductor integrated circuit are formed by atmospheric pressure CVD method or the like. Thereafter, although not shown in the drawings, an embedded electrode of an element forming a semiconductor integrated circuit using the embedded plug method is formed in the interlayer insulating film 12. Next, Ti
The N barrier film 14 is deposited by collimating sputtering to a thickness of about 20 nm. Subsequently, a Cu film 21 is deposited by a magnetron sputtering method to a film thickness of about 500 nm, and then an organic silane-based gas such as TEOS (T
An SiO ₂ film (PE-TEOS film) 22 having a film thickness of about 20 is formed by a plasma CVD method using a mixed gas of an etraethyl orthosilicate gas and an O ₂ gas.
Deposit about 0 nm. The conditions for forming the PE-TEOS film are as follows, for example. TEOS gas: 800 sccm O ₂ gas: 600 sccm Pressure: 1130 Pa RF Power: 700 W Substrate temperature: 400 ° C

A SiO ₂ film formed by a plasma CVD method using an ordinary mixed gas of silane SiH ₄ gas and O ₂ gas,
Alternatively, when the SiO ₂ film is deposited by the atmospheric pressure CVD method, the underlying Cu film 21 is oxidized, which causes a problem that the resistance of the Cu wiring 23 described later increases.
During the deposition of the E-TEOS film 22, the underlying Cu film 21 is hardly oxidized. The gas used for forming the SiO ₂ film is TEOS gas, which is an organic silane-based gas, and silane Si.
The reason why the degree of oxidation of the Cu wiring greatly differs from that of the H ₄ gas is not clear, but carbon contained in the organic silane-based gas may have some effect.

Next, as shown in FIG. 1B, the PE-TEOS film 22 is patterned by a photolithography method, and then the processed substrate is heated to a high temperature by using the patterned PE-TEOS film 22 as a mask. RIE
Method, that is, the etching of the Cu film 21 and the barrier film 14 by the high temperature etching method is performed, for example, under the following etching conditions to form the Cu wiring 23. Cu high temperature etching conditions SiCl ₄ gas: 30 sccm N ₂ gas: 100 sccm Pressure: 1300 Pa RF Power: 500 W Substrate temperature: 350 ° C

Next, as shown in FIG. 1 (c), TEOS
Plasma CVD using mixed gas of gas and O ₂ gas
A PE-TEOS film 24 is deposited to a thickness of about 2000 nm by the method. The conditions for forming this PE-TEOS film are as follows, for example. TEOS gas: 800 sccm O ₂ gas: 600 sccm Pressure: 1130 Pa RF Power: 700 W Substrate temperature: 400 ° C

Subsequently, the PE-TEOS film 24 is flattened by an etch-back method using a photoresist or CMP. After that, when forming a multilayer wiring structure, a second-layer Cu wiring is formed on the PE-TEOS film 24 by the same manufacturing method as described above. By adopting the above-mentioned Cu wiring forming method, it is possible to form a fine Cu wiring without oxidizing the Cu wiring.

Embodiment 2 This embodiment is an example in which the present invention is applied to a semiconductor device and a method of manufacturing the same, which is shown in FIGS. 1 (a), 1 (b) and 2
Description will be made with reference to (a) and (b). First, the film structure shown in FIG. 1A is formed on the semiconductor substrate 11 by the same manufacturing method as in Example 1, and the Cu film 21 using the PE-TEOS film 22 as a mask is etched by the high temperature etch back method. , Figure 1
The Cu wiring shown in (b) is formed.

Next, as shown in FIG. 2A, TEOS
Plasma CVD using mixed gas of gas and O ₂ gas
The PE-TEOS film 31 by the method is deposited under the same formation conditions as in Example 1 to a film thickness of about 200 nm. After that, a low dielectric constant film 32 such as SOG (Spin On Gl) is formed.
ass) or SiOF film is formed to a film thickness of about 1500 nm, followed by an etch back method using a photoresist,
Alternatively, the low dielectric constant film 32 is flattened by CMP. Etchback for planarization is performed until the low dielectric constant film 32 does not remain on the Cu wiring 23. The reason is that in a semiconductor integrated circuit having a multilayer wiring structure, when a buried plug connecting upper and lower Cu wirings is formed in an interlayer insulating film, if the interlayer insulating film is a PE-TEOS film of the same quality, the contact hole side wall shape is smooth. This is because the embedded plug is easy to form.

Next, as shown in FIG. 2B, TEOS
Plasma CVD using mixed gas of gas and O ₂ gas
The PE-TEOS film 33 by the method is deposited under the same formation conditions as in Example 1 to a film thickness of about 600 nm. After that, when forming a multilayer wiring structure, the second-layer Cu wiring is formed on the PE-TEOS film 33 by the same manufacturing method as described above. By adopting the Cu wiring forming method described above, it is possible to form a fine Cu wiring without oxidizing the Cu wiring, and further it is possible to reduce the Cu wiring capacitance of the second layer in the multilayer wiring configuration.

Although the present invention has been described with reference to the two examples, the present invention is not limited to these examples. For example, as an organic silane-based gas for forming an oxide film, TEOS (Tetraethyl Orthosi) is used.
licate) gas was used, but Tetramethyl
Orthosilicate (TMOS) gas, Di
acetoxy Digitallybuty
Silane (DADBS) gas, Tetraethy
l Silane (TES) gas, Tetramety
l Silane (TMS) gas, Octametyl
Cyclo-tetra Siloxane (OMCT
S) Gas, Tetrapropoxy Silane
(TPOS) gas, Tetramethyl Cyclo
Other organic silane-based gas such as -tetra Siloxane (TMCTS) gas may be appropriately used. Further, within the scope of the technical idea of the present invention, the process equipment and process conditions can be changed appropriately.

[0029]

As is apparent from the above description, the semiconductor device using the Cu wiring of the present invention and the manufacturing method thereof are
A fine Cu wiring can be formed without oxidizing the Cu wiring, and a highly integrated semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device for explaining the first half of the steps of Example 1 to which the present invention is applied in the order of steps,
(A) shows a state in which a barrier film, a Cu film and a PE-TEOS film are formed on an interlayer insulating film of a semiconductor substrate, and (b) shows PE.
-Cu wiring is formed by RIE using the TEOS film as a mask, and (c) is a state in which a PE-TEOS film covering the Cu wiring is deposited and flattened by etching back or the like.

FIG. 2 is a process of Example 2 to which the present invention is applied.
1B is a schematic cross-sectional view of a semiconductor device for explaining the steps subsequent to the step shown in FIG. 1B described in FIG. 1A, in which PE-TEOS film which is a protective film for Cu wiring is deposited, and After the dielectric constant film is formed, it is flattened by etching back, and (b) is a state in which the PE-TEOS film is deposited.

FIG. 3 is a schematic cross-sectional view of a semiconductor device for explaining a method of manufacturing a conventional semiconductor device in which Cu wiring is formed by a damascene method, in the order of steps, in which (a) shows a groove formed in an interlayer insulating film of a semiconductor substrate. In the state where the barrier film and the Cu film are deposited, (b) shows that the Cu film is etched back to form the Cu wiring in the groove.
In this state, the N film and the interlayer insulating film are deposited.

[Explanation of symbols]

 11 semiconductor substrate 12 interlayer insulating film 13 groove 14 barrier film 15, 21 Cu film 16, 23 Cu wiring 17 SiN film 18 interlayer insulating film 22, 24, PE-TEOS film 31, 33 PE-TEOS film 32 low dielectric constant film

Claims (8)

[Claims] 1. In a semiconductor device using copper wiring, copper wiring on an interlayer insulating film of a semiconductor substrate, and plasma C using organosilane-based gas on the copper wiring.
A semiconductor device comprising: an oxide film formed by the VD method. 2. The semiconductor device according to claim 1, further comprising an oxide film which covers the copper wiring and is formed by a plasma CVD method using an organic silane-based gas. 3. Plasma CV using an organic silane-based gas
The semiconductor device according to claim 1, further comprising a protective film formed by the D method and covering the copper wiring, and a low dielectric constant film on the protective film. 4. The semiconductor device according to claim 1, wherein the oxide film is an oxide film formed by a plasma CVD method using tetraethyl orthosilicate gas. 5. A method of manufacturing a semiconductor device using copper wiring, the step of forming a copper film on an interlayer insulating film of a semiconductor substrate, and plasma CVD using an organosilane-based gas on the copper film.
A step of depositing an oxide film by a method, a step of patterning the oxide film, a step of etching the copper film by reactive ion etching to form a copper wiring by using the oxide film as a mask, and a step of forming the copper wiring. A step of depositing an oxide film by a plasma CVD method using an organic silane-based gas for coating, and a method of manufacturing a semiconductor device using a copper wiring. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of depositing an oxide film covering the copper wiring by a plasma CVD method using an organic silane-based gas. 7. A step of depositing a protective film covering the copper wiring by a plasma CVD method using an organic silane-based gas, and a step of forming a low dielectric constant film on the protective film. The method for manufacturing a semiconductor device according to claim 5, wherein 8. The organic silane-based gas is tetraethyl orthosilicate gas, according to claim 5,
The manufacturing method of the semiconductor device described in the above.