KR19980049921A - Process Simplification Method of Semiconductor Device - Google Patents
Process Simplification Method of Semiconductor Device Download PDFInfo
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- KR19980049921A KR19980049921A KR1019960068670A KR19960068670A KR19980049921A KR 19980049921 A KR19980049921 A KR 19980049921A KR 1019960068670 A KR1019960068670 A KR 1019960068670A KR 19960068670 A KR19960068670 A KR 19960068670A KR 19980049921 A KR19980049921 A KR 19980049921A
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- metal wiring
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 238000010849 ion bombardment Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000005530 etching Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000151 deposition Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 230000005596 ionic collisions Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자에 관한 것으로 특히, 금속배선공정후 상기 금속배선의 패드부위를 노출시킬 때 공정을 단순화 할 수 있는 반도체소자의 공정단순화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a process simplification method of a semiconductor device which can simplify the process when exposing a pad portion of the metal wiring after a metal wiring process.
본 발명에 따른 반도체소자의 공정단순화 방법은 기판의 소정영역에 금속배선을 형성하는 단계, 상기 금속배선상에 ARC층을 형성하는 단계, 상기 ARC층을 포함한 기판전면에 제 1, 제 2 절연막을 차례로 형성하는 단계, 제 2, 제 1 절연막 및 ARC층을 선택적으로 패터닝하여 금속배선의 상층부를 노출시키는 단계를 포함하여 공정단순화 및 신뢰도 있는 반도체소자의 공정단순화 방법을 제공할 수 있는 효과가 있다.In the process simplification method of a semiconductor device according to the present invention, forming a metal wiring in a predetermined region of a substrate, forming an ARC layer on the metal wiring, and forming a first and a second insulating film on the front surface of the substrate including the ARC layer. Forming sequentially, selectively patterning the second, first insulating film and the ARC layer to expose the upper layer portion of the metal wiring has the effect of providing a process simplification and a process simplification method of a reliable semiconductor device.
Description
본 발명은 반도체소자에 관한 것으로 특히, 금속배선공정후 상기 금속배선의 패드부위를 노출시킬 때 공정을 단순화 할 수 있는 반도체소자의 공정단순화 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a process simplification method of a semiconductor device which can simplify the process when exposing a pad portion of the metal wiring after a metal wiring process.
이하에서, 첨부된 도면을 참조하여 종래 반도체소자의 패드노출 방법에 대하여 설명하기로 한다.Hereinafter, a pad exposure method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1d는 종래 반도체소자의 패드 노출공정 단면도이다.1A to 1D are cross-sectional views of a pad exposing process of a conventional semiconductor device.
먼저, 도 1a에 나타낸 바와 같이, 기판(1)상에 배선금속층(2)과 ARC(Anti Refractory Coat)층(3)을 형성한 후 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 기판(1)의 소정영역에만 남긴다. 그리고, 상기 ARC층(3)과 배선금속층(2)의 계면에서는 ARC층(3)증착시 고온공정을 실시하게 되어 그 계면에 열적반응층(4)이 생성된다. 이때, 상기 배선금속층(2)은 본딩 패드(bonding pad)를 하기 위한 금속층이고, ARC층(3)은 하부의 절연층상에 금속층을 형성한후 패터닝할 때 금속층의 난반사를 방지하기 위하여 형성하는 반사방지물질이다. 만약, 이와 같은 ARC층을형성하지 않고 노광공정을 할 경우에는 난반사나 측면반사에 의해 필요이상의 노광을 할 수 있는 문제점이 발생한게 된다.First, as shown in FIG. 1A, a wiring metal layer 2 and an ARC (Anti Refractory Coat) layer 3 are formed on a substrate 1, and then selectively patterned (photolithography process + etching process) to form a substrate 1. Only in a predetermined area of). At the interface between the ARC layer 3 and the wiring metal layer 2, a high temperature process is performed during the deposition of the ARC layer 3, and a thermal reaction layer 4 is formed at the interface. In this case, the wiring metal layer 2 is a metal layer for bonding pads, and the ARC layer 3 is a reflection formed to prevent diffuse reflection of the metal layer when patterning after forming a metal layer on the lower insulating layer. It is a prevention substance. If the exposure process is performed without forming such an ARC layer, a problem may occur in which the exposure is more than necessary due to diffuse reflection or side reflection.
도 1b에 나타낸 바와 같이, 상기 ARC층(3)과 열적반응층(4)을 감광막(도시하지 않음)을 이용한 포토/에칭공정으로 배선금속층(2)상에서 제거한다. 이때, 상기 배선금속층(2)상의 에지부에는 완전히 제거되지 않은 ARC층(3)이 부분적으로 남게 된다. 그리고, 상기 ARC층(3)을 배선금속층(2)상에서 제거하는 이유는 후속공정인 와이어 본딩(wire bonding)공정시 배선금속과 와이어 본딩시 사용하는 금(gold)와 이어(wire)와의 접촉특성을 좋게 하기 위해서이다.As shown in Fig. 1B, the ARC layer 3 and the thermal reaction layer 4 are removed on the wiring metal layer 2 by a photo / etching process using a photosensitive film (not shown). At this time, the ARC layer 3 which is not completely removed remains partially at the edge portion of the wiring metal layer 2. In addition, the reason why the ARC layer 3 is removed from the wiring metal layer 2 is because of the contact property between the wiring metal and the gold used in the wire bonding during the subsequent wire bonding process. To make it good.
도 1c에 나타낸 바와 같이, 상기 배선금속층(2)을 포함한 기판(1)전면에 산화막(5), 질화막(6) 그리고, 감광막(PR)을 차례로 형성한다음 노광 및 현상공정으로 패드영역의 감광막(PR)을 선택적으로 패터닝한다.As shown in FIG. 1C, an oxide film 5, a nitride film 6, and a photoresist film PR are sequentially formed on the entire surface of the substrate 1 including the wiring metal layer 2, and then the photoresist film of the pad region is exposed and developed. Selectively pattern (PR).
도 1d에 나타낸 바와 같이, 상기 패터닝된 감광막(PR)을 마스크로 이용한 식각공정으로 질화막(6) 및 산화막(5)을 차례로 제거하여 패드부위의 상기 배선금속층(2)상층부를 노출시킨다. 그다음, 상기 감광막(PR)을 제거한다.As illustrated in FIG. 1D, the nitride film 6 and the oxide film 5 are sequentially removed by an etching process using the patterned photoresist film PR as a mask to expose the upper layer of the wiring metal layer 2 on the pad portion. Then, the photoresist film PR is removed.
종래 반도체소자의 패드 노출공정에 있어서는 다음과 같은 문제점이 있었다.The pad exposure process of the conventional semiconductor device has the following problems.
첫째, 패드부위의 배선금속층을 노출시키는 공정에 있어서 반사방지막인 ARC층의 제거공정과, 산화막 및 질화막을 형성한후 제거하는 공정등 2단계로 이루어져 공정이 복잡하여 생산성이 떨어진다.First, in the process of exposing the wiring metal layer on the pad part, the process consists of two steps, a process of removing the ARC layer, which is an anti-reflection film, and a process of removing and then forming an oxide film and a nitride film.
둘째, ARC층 제거공정시 함께 제거되어야할 열적반응층이 덜 식각된 채로 산화막과 질화막 그리고 감광막을 형성한후 열처리공정(예를 들면 감광막에 대한 소프트(soft)/하드(hard) 베이크(bake)공정)을 하게될 경우, 상기 열적반응층이 배선금속층 상에서 경화되어 본딩 패드공정 등에 대한 불량유발 및 배선저항 등의 문제를 발생시킬 수 있다.Second, after forming the oxide film, nitride film and photoresist with less etching of the thermal reaction layer to be removed during the ARC layer removal process, for example, soft / hard bake on the photoresist film. Process), the thermal reaction layer may be cured on the wiring metal layer to cause problems such as defects in the bonding pad process and wiring resistance.
본 발명은 상기한 바와 같은 종래 반도체소자의 문제점들을 해결하기 위하여 안출한 것으로 패드부위의 배선금속층 노출공정을 한 번에 하여 공정을 단순화시킬 수 있는 반도체소자의 공정단순화 방법을 제공하는 데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the problems of the conventional semiconductor device as described above, and an object thereof is to provide a process simplification method for a semiconductor device that can simplify the process by exposing a wiring metal layer at a pad portion at a time. have.
도 1a 내지 도 1d는 종래 반도체소자의 패드 노출공정 단면도.1A to 1D are cross-sectional views of a pad exposing process of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명 반도체소자의 패드 노출공정 단면도.2A to 2C are cross-sectional views of a pad exposing process of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10:기판, 11: 배선금속층, 12:ARC층, 13:열적반응층, 14:제1절연막, 15:제2절연막10: substrate, 11: wiring metal layer, 12: ARC layer, 13: thermal reaction layer, 14: first insulating film, 15: second insulating film
본 발명에 따른 반도체소자의 공정단순화 방법은 기판의 소정영역에 금속배선을 형성하는 단계, 상기 금속배선상에 ARC층을 형성하는 단계, 상기 ARC층을 포함한 기판전면에 제 1, 제 2 절연막을 차례로 형성하는 단계, 제 2, 제 1 절연막 및 ARC층을 선택적으로 패터닝하여 금속배선의 상층부를 노출시키는 단계를 포함한다.In the process simplification method of a semiconductor device according to the present invention, forming a metal wiring in a predetermined region of a substrate, forming an ARC layer on the metal wiring, and forming a first and a second insulating film on the front surface of the substrate including the ARC layer. Forming sequentially, and selectively patterning the second, first insulating film and the ARC layer to expose the upper layer portion of the metal wiring.
이와 같은 본 발명 반도체소자의 공정단순화 방법을 첨부된 도면을 참조하여 설명하기로 한다.Such a process simplification method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명 반도체소자의 패드 노출공정 단면도이다.2A to 2C are cross-sectional views of a pad exposing process of a semiconductor device according to the present invention.
먼저, 도 2a에 나타낸 바와 같이, 기판(10)상에 배선금속층(11)과 ARC(Anti Refractory Coat)층(12)을 차례로 형성한후 선택적으로 패터닝(포토리소그래피공정 + 식각공정)하여 기판(10)의 소정영역에만 남긴다. 이때, 상기 ARC층(12)과 배선금속층(11)의 계면에서는 ARC층(12)증착시 약 400℃ 이상의 고온공정을 실시하게 되어 ARC층(12)과 배선금속층(11)의 계면에 상기 ARC층(12)과 배선금속층(11)의 합금층인 열적반응층(13)이 생성된다. 이때, 상기 배선금속층(11)은 본딩 패드(bonding pad)를 하기 위한 금속층이고, ARC층(12)은 하부의 절연층상에 금속층을 형성한후 패터닝할 때 금속층의 난반사를 방지하기 위하여 형성하는 광 반사방지층이다.First, as shown in FIG. 2A, a wiring metal layer 11 and an ARC (Anti Refractory Coat) layer 12 are sequentially formed on the substrate 10, and then selectively patterned (photolithography process + etching process) to form a substrate ( It remains only in the predetermined area of 10). At this time, at the interface between the ARC layer 12 and the wiring metal layer 11, a high temperature process of about 400 ° C. or more is performed at the time of depositing the ARC layer 12, so that the ARC is connected to the interface between the ARC layer 12 and the wiring metal layer 11. A thermal reaction layer 13, which is an alloy layer of the layer 12 and the wiring metal layer 11, is produced. At this time, the wiring metal layer 11 is a metal layer for bonding pads (bonding pad), the ARC layer 12 is a light formed to prevent diffuse reflection of the metal layer when patterning after forming a metal layer on the lower insulating layer. It is an antireflection layer.
도 2b에 나타낸 바와 같이, 상기 배선금속층(11)을 포함한 기판(10)전면에 제 1 절연막(14), 제 2 절연막(15) 그리고, 감광막(PR)을 차례로 형성한 다음 노광 및 현상공정으로 패드영역의 감광막(PR)을 선택적으로 패터닝한다. 이때, 상기 제 1 절연막(14)은 산화막으로 형성하고, 제 2 절연막(15)은 질화막을 사용하여 형성한다.As shown in FIG. 2B, the first insulating film 14, the second insulating film 15, and the photosensitive film PR are sequentially formed on the entire surface of the substrate 10 including the wiring metal layer 11, and then exposed and developed. The photoresist film PR of the pad region is selectively patterned. In this case, the first insulating film 14 is formed of an oxide film, and the second insulating film 15 is formed of a nitride film.
도 2c에 나타낸 바와 같이, 상기 패터닝된 감광막(PR)을 마스크로 이용한 식각공정으로 제 2 절연막(15), 제 1 절연막(14), ARC층(12) 그리고, 열적반응층(13)을 차례로 제거하여 패드부위의 상기 배선금속층(11)상층부를 노출시킨다. 그다음, 상기 감광막(PR)을 제거한다. 이때, 이온충돌법을 이용하여 제거한다. 그리고, 상기 배선금속층(11)의 상층부를 노출시키는 이유는 배선금속층(11)과 금 와이어와의 접촉을 위한 것이다. 이때, 상기 제 1, 제 2 절연막(14)(15)과 ARC층(12) 및 열적반응층(13)을 제거할 때 산화막으로 형성하는 제 1 절연막(14)의 식각시간을 일반적인 경우보다 2배 정도의 시간동안 식각한다.As shown in FIG. 2C, the second insulating film 15, the first insulating film 14, the ARC layer 12, and the thermal reaction layer 13 are sequentially formed by an etching process using the patterned photoresist film PR as a mask. It removes and exposes the upper layer part of the said wiring metal layer 11 of a pad part. Then, the photoresist film PR is removed. At this time, it is removed by ion collision method. The reason why the upper layer portion of the wiring metal layer 11 is exposed is for contact between the wiring metal layer 11 and the gold wire. In this case, when the first and second insulating layers 14 and 15, the ARC layer 12, and the thermal reaction layer 13 are removed, an etching time of the first insulating layer 14 formed of an oxide film is 2 times higher than that of the general case. Etch for twice as long.
본 발명에 따른 반도체소자의 공정단순화 방법에 있어서는 다음과 같은 효과가 있다.In the process simplification method of the semiconductor device according to the present invention has the following effects.
첫째, 패드부위의 배선금속층을 노출시키는 공정이 ARC층과 열적반응층 및 제 1 절여막과 제 2 절연막에 대한 한 번의 제거공정으로 이루어져 공정이 단순해지므로 생산성을 향상시킬 수 있다.First, since the process of exposing the wiring metal layer on the pad part includes a single removal process for the ARC layer, the thermal reaction layer, and the first ablation film and the second insulating film, the process can be simplified, thereby improving productivity.
둘째, ARC층에 대한 제거공정이 이온충돌법을 사용하는 방법과 산화막 제거공정시에 필요한 시간의 2배로 식각을 하므로 ARC층 뿐만 아니라 ARC층 하부에 형성된 열적반응층까지 완전히 제거할 수 있어 열적반응층의 경화문제를 해결하여 신뢰도 있는 반도체소자를 제공할 수 있다.Second, since the removal process for the ARC layer is etched twice as much as the time required for the ion collision method and the oxide film removal process, it is possible to completely remove not only the ARC layer but also the thermal reaction layer formed under the ARC layer. It is possible to provide a reliable semiconductor device by solving the hardening problem of the layer.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960068670A KR100370121B1 (en) | 1996-12-20 | 1996-12-20 | Method for simplifying processes in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960068670A KR100370121B1 (en) | 1996-12-20 | 1996-12-20 | Method for simplifying processes in semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980049921A true KR19980049921A (en) | 1998-09-15 |
| KR100370121B1 KR100370121B1 (en) | 2003-03-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960068670A KR100370121B1 (en) | 1996-12-20 | 1996-12-20 | Method for simplifying processes in semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR100370121B1 (en) |
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1996
- 1996-12-20 KR KR1019960068670A patent/KR100370121B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR100370121B1 (en) | 2003-03-28 |
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