KR102726634B1 - 선택적 이중층 유전체 재성장을 통한 완전 자기 정렬 비아 - Google Patents

선택적 이중층 유전체 재성장을 통한 완전 자기 정렬 비아 Download PDF

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KR102726634B1
KR102726634B1 KR1020207036487A KR20207036487A KR102726634B1 KR 102726634 B1 KR102726634 B1 KR 102726634B1 KR 1020207036487 A KR1020207036487 A KR 1020207036487A KR 20207036487 A KR20207036487 A KR 20207036487A KR 102726634 B1 KR102726634 B1 KR 102726634B1
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dielectric layer
layer
conductive
dielectric
conductive cap
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KR20210014127A (ko
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칸다바라 타필리
제프리 스미스
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도쿄엘렉트론가부시키가이샤
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    • H01L21/76832—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H01L21/0274—
    • H01L21/76816—
    • H01L21/76831—
    • H01L21/76834—
    • H01L21/76846—
    • H01L21/7685—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H10W20/0693—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs by forming self-aligned vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/085—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
KR1020207036487A 2018-06-27 2019-06-26 선택적 이중층 유전체 재성장을 통한 완전 자기 정렬 비아 Active KR102726634B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862690838P 2018-06-27 2018-06-27
US62/690,838 2018-06-27
PCT/US2019/039260 WO2020006087A1 (en) 2018-06-27 2019-06-26 Fully self-aligned via with selective bilayer dielectric regrowth

Publications (2)

Publication Number Publication Date
KR20210014127A KR20210014127A (ko) 2021-02-08
KR102726634B1 true KR102726634B1 (ko) 2024-11-05

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KR1020207036487A Active KR102726634B1 (ko) 2018-06-27 2019-06-26 선택적 이중층 유전체 재성장을 통한 완전 자기 정렬 비아

Country Status (6)

Country Link
US (2) US11031287B2 (OSRAM)
JP (1) JP7339481B2 (OSRAM)
KR (1) KR102726634B1 (OSRAM)
CN (1) CN112368822B (OSRAM)
TW (1) TWI816819B (OSRAM)
WO (1) WO2020006087A1 (OSRAM)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7348440B2 (ja) * 2018-03-20 2023-09-21 東京エレクトロン株式会社 統合的な半導体処理モジュールを組み込んだ自己認識及び補正異種プラットフォーム及びその使用方法
US11121025B2 (en) * 2018-09-27 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Layer for side wall passivation
US11515203B2 (en) * 2020-02-05 2022-11-29 Tokyo Electron Limited Selective deposition of conductive cap for fully-aligned-via (FAV)
US11508572B2 (en) 2020-04-01 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
KR20230026385A (ko) * 2020-06-17 2023-02-24 도쿄엘렉트론가부시키가이샤 영역 선택적 증착에서 측방 막 형성을 감소시키는 방법
US20220238323A1 (en) * 2021-01-28 2022-07-28 Tokyo Electron Limited Method for selective deposition of dielectric on dielectric
US11929314B2 (en) * 2021-03-12 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures including a fin structure and a metal cap
US12564027B2 (en) 2022-04-27 2026-02-24 Tokyo Electron Limited Top-down self-alignment of vias in a semiconductor device for sub-22NM pitch metals
US12308310B2 (en) 2022-05-05 2025-05-20 Nanya Technology Corporation Method for forming semiconductor interconnection structure against stress migration
US12417982B2 (en) 2022-05-25 2025-09-16 Nanya Technology Corporation Semiconductor device with contact structure
TWI825807B (zh) * 2022-05-25 2023-12-11 南亞科技股份有限公司 具有插塞結構之半導體元件的製備方法
US12283518B2 (en) 2022-05-25 2025-04-22 Nanya Technology Corporation Method for fabricating semiconductor device with contact structure
US20250054809A1 (en) * 2023-08-07 2025-02-13 Tokyo Electron Limited Fully self-aligned via with graphene cap

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030148618A1 (en) 2002-02-07 2003-08-07 Applied Materials, Inc. Selective metal passivated copper interconnect with zero etch stops
KR100790452B1 (ko) 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
US20170110397A1 (en) 2015-10-20 2017-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6287961B1 (en) * 1999-01-04 2001-09-11 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
JP4910231B2 (ja) * 2000-10-25 2012-04-04 ソニー株式会社 半導体装置の製造方法
US20050082089A1 (en) * 2003-10-18 2005-04-21 Stephan Grunow Stacked interconnect structure between copper lines of a semiconductor circuit
TWI220774B (en) * 2003-11-03 2004-09-01 Univ Nat Sun Yat Sen Method for patterning low dielectric constant film and method for manufacturing dual damascene structure
KR100590205B1 (ko) * 2004-01-12 2006-06-15 삼성전자주식회사 반도체 장치의 배선 구조체 및 그 형성 방법
US7259463B2 (en) 2004-12-03 2007-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Damascene interconnect structure with cap layer
US20070228571A1 (en) * 2006-04-04 2007-10-04 Chen-Hua Yu Interconnect structure having a silicide/germanide cap layer
US7776743B2 (en) * 2008-07-30 2010-08-17 Tel Epion Inc. Method of forming semiconductor devices containing metal cap layers
KR100953736B1 (ko) * 2009-07-27 2010-04-19 주식회사 아토 증착 장치 및 반도체 소자의 제조 방법
TWI424529B (zh) * 2010-10-28 2014-01-21 旺宏電子股份有限公司 半導體結構及其製造方法
JP5665557B2 (ja) * 2011-01-14 2015-02-04 ルネサスエレクトロニクス株式会社 半導体装置および半導体装置の製造方法
US9269612B2 (en) * 2011-11-22 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms of forming damascene interconnect structures
US8803321B2 (en) * 2012-06-07 2014-08-12 International Business Machines Corporation Dual damascene dual alignment interconnect scheme
US8652962B2 (en) * 2012-06-19 2014-02-18 Taiwan Semiconductor Manufacturing Co., Ltd. Etch damage and ESL free dual damascene metal interconnect
US9583429B2 (en) * 2013-11-14 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US9659857B2 (en) * 2013-12-13 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method making the same
US9553017B2 (en) * 2015-01-23 2017-01-24 GlobalFoundries, Inc. Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures
DE102015114405A1 (de) * 2015-08-28 2017-03-02 Infineon Technologies Dresden Gmbh Halbleitervorrichtung mit sich durch eine zwischenschicht erstreckenden kontaktstrukturen und herstellungsverfahren
KR102616823B1 (ko) * 2015-12-16 2023-12-22 삼성전자주식회사 반도체 장치
US9530691B1 (en) * 2016-02-19 2016-12-27 Globalfoundries Inc. Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias
US10068764B2 (en) 2016-09-13 2018-09-04 Tokyo Electron Limited Selective metal oxide deposition using a self-assembled monolayer surface pretreatment
KR102449200B1 (ko) * 2017-07-04 2022-09-30 삼성디스플레이 주식회사 클럭 배선을 포함하는 표시 장치
JP7348440B2 (ja) * 2018-03-20 2023-09-21 東京エレクトロン株式会社 統合的な半導体処理モジュールを組み込んだ自己認識及び補正異種プラットフォーム及びその使用方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030148618A1 (en) 2002-02-07 2003-08-07 Applied Materials, Inc. Selective metal passivated copper interconnect with zero etch stops
KR100790452B1 (ko) 2006-12-28 2008-01-03 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 다층 금속배선형성방법
US20170110397A1 (en) 2015-10-20 2017-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

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Publication number Publication date
US11705369B2 (en) 2023-07-18
US20200006140A1 (en) 2020-01-02
CN112368822B (zh) 2023-09-22
TWI816819B (zh) 2023-10-01
US11031287B2 (en) 2021-06-08
TW202006886A (zh) 2020-02-01
KR20210014127A (ko) 2021-02-08
JP7339481B2 (ja) 2023-09-06
JP2021530101A (ja) 2021-11-04
CN112368822A (zh) 2021-02-12
US20210249305A1 (en) 2021-08-12
WO2020006087A1 (en) 2020-01-02

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