KR102712052B1 - 인-모듈 기능들을 수행하는 메모리 모듈 - Google Patents

인-모듈 기능들을 수행하는 메모리 모듈 Download PDF

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KR102712052B1
KR102712052B1 KR1020170004297A KR20170004297A KR102712052B1 KR 102712052 B1 KR102712052 B1 KR 102712052B1 KR 1020170004297 A KR1020170004297 A KR 1020170004297A KR 20170004297 A KR20170004297 A KR 20170004297A KR 102712052 B1 KR102712052 B1 KR 102712052B1
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memory
memory array
memory module
host device
module
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KR20170104115A (ko
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무-티엔 창
디민 니우
홍종 정
임선영
김인동
최장석
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삼성전자주식회사
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    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
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    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
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    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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    • G—PHYSICS
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    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Dram (AREA)
KR1020170004297A 2016-03-03 2017-01-11 인-모듈 기능들을 수행하는 메모리 모듈 Active KR102712052B1 (ko)

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
US201662303343P 2016-03-03 2016-03-03
US201662303347P 2016-03-03 2016-03-03
US201662303352P 2016-03-03 2016-03-03
US201662303349P 2016-03-03 2016-03-03
US62/303,343 2016-03-03
US62/303,349 2016-03-03
US62/303,352 2016-03-03
US62/303,347 2016-03-03
US201662347569P 2016-06-08 2016-06-08
US62/347,569 2016-06-08
US15/213,386 2016-07-18
US15/213,386 US10592114B2 (en) 2016-03-03 2016-07-18 Coordinated in-module RAS features for synchronous DDR compatible memory

Publications (2)

Publication Number Publication Date
KR20170104115A KR20170104115A (ko) 2017-09-14
KR102712052B1 true KR102712052B1 (ko) 2024-10-02

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US (4) US10592114B2 (cg-RX-API-DMAC10.html)
JP (1) JP7022511B2 (cg-RX-API-DMAC10.html)
KR (1) KR102712052B1 (cg-RX-API-DMAC10.html)
CN (1) CN107153616B (cg-RX-API-DMAC10.html)
TW (2) TWI756767B (cg-RX-API-DMAC10.html)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10592114B2 (en) * 2016-03-03 2020-03-17 Samsung Electronics Co., Ltd. Coordinated in-module RAS features for synchronous DDR compatible memory
KR102336666B1 (ko) 2017-09-15 2021-12-07 삼성전자 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
CN107507637B (zh) * 2017-09-18 2024-02-27 深圳市江波龙电子股份有限公司 一种低功耗双列直插式存储器及其增强驱动方法
KR102517685B1 (ko) * 2017-11-07 2023-04-05 후아웨이 테크놀러지 컴퍼니 리미티드 메모리 블록 복구 방법 및 디바이스
KR102410022B1 (ko) * 2017-11-24 2022-06-21 에스케이하이닉스 주식회사 에러스크럽방법 및 이를 이용한 반도체모듈
CN111448543B (zh) 2017-12-07 2021-10-01 华为技术有限公司 内存访问技术及计算机系统
US11416395B2 (en) 2018-02-05 2022-08-16 Micron Technology, Inc. Memory virtualization for accessing heterogeneous memory components
US11099789B2 (en) 2018-02-05 2021-08-24 Micron Technology, Inc. Remote direct memory access in multi-tier memory systems
US10782908B2 (en) 2018-02-05 2020-09-22 Micron Technology, Inc. Predictive data orchestration in multi-tier memory systems
US12135876B2 (en) * 2018-02-05 2024-11-05 Micron Technology, Inc. Memory systems having controllers embedded in packages of integrated circuit memory
US10880401B2 (en) 2018-02-12 2020-12-29 Micron Technology, Inc. Optimization of data access and communication in memory systems
US10534731B2 (en) 2018-03-19 2020-01-14 Micron Technology, Inc. Interface for memory having a cache and multiple independent arrays
KR102658230B1 (ko) 2018-06-01 2024-04-17 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
US10877892B2 (en) 2018-07-11 2020-12-29 Micron Technology, Inc. Predictive paging to accelerate memory access
TWI686697B (zh) * 2018-07-26 2020-03-01 大陸商深圳大心電子科技有限公司 記憶體管理方法以及儲存控制器
TWI671632B (zh) 2018-10-24 2019-09-11 財團法人工業技術研究院 記憶體裝置及其復新資訊同步方法
KR102649315B1 (ko) * 2018-12-03 2024-03-20 삼성전자주식회사 휘발성 메모리 장치를 포함하는 메모리 모듈 및 이를 포함하는 메모리 시스템
US10996890B2 (en) 2018-12-19 2021-05-04 Micron Technology, Inc. Memory module interfaces
US11403035B2 (en) 2018-12-19 2022-08-02 Micron Technology, Inc. Memory module including a controller and interfaces for communicating with a host and another memory module
US10789015B2 (en) 2019-03-01 2020-09-29 Micron Technology, Inc. Background operations in memory
US10852949B2 (en) 2019-04-15 2020-12-01 Micron Technology, Inc. Predictive data pre-fetching in a data storage device
CN111143109B (zh) * 2019-12-16 2021-08-13 浙江大学 一种ecc内存管理器、方法及电子设备
US11200113B2 (en) * 2020-01-14 2021-12-14 Intel Corporation Auto-increment write count for nonvolatile memory
US11663124B2 (en) * 2020-02-25 2023-05-30 Micron Technology, Inc. Apparatuses and methods for interfacing on-memory pattern matching
KR102838666B1 (ko) * 2020-11-03 2025-07-24 삼성전자주식회사 메모리 모듈 및 메모리 모듈의 동작방법
TWI771926B (zh) * 2021-02-25 2022-07-21 慧榮科技股份有限公司 資料儲存裝置以及非揮發式記憶體控制方法
US11625343B2 (en) 2021-05-12 2023-04-11 Micron Technology, Inc. Memory with a communications bus for device-to-controller communication, and associated systems, devices, and methods
US12164803B2 (en) * 2021-05-21 2024-12-10 Micron Technology, Inc. Memory with memory-initiated command insertion, and associated systems, devices, and methods
JP7727190B2 (ja) * 2021-11-04 2025-08-21 富士通株式会社 メモリアクセスコントローラ及びメモリアクセスコントロール方法
KR20240039906A (ko) 2022-09-20 2024-03-27 에스케이하이닉스 주식회사 메모리 컨트롤러 및 그것을 포함하는 메모리 시스템
US12704992B2 (en) 2023-02-15 2026-08-11 Micron Technology, Inc. Multiple rank DRAMs on a same module side

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080082750A1 (en) 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
JP2008171163A (ja) * 2007-01-11 2008-07-24 Hitachi Ltd フラッシュメモリモジュール、そのフラッシュメモリモジュールを記録媒体として用いたストレージ装置及びそのフラッシュメモリモジュールのアドレス変換テーブル検証方法
US20100332943A1 (en) 2009-06-29 2010-12-30 Sandisk Corporation Method and device for selectively refreshing a region of a non-volatile memory of a data storage device
JP2012089137A (ja) * 2010-10-20 2012-05-10 Samsung Electronics Co Ltd 半導体装置、これを含むメモリモジュール、メモリシステム及びその動作方法
JP2014157391A (ja) * 2013-02-14 2014-08-28 Sony Corp 記憶制御装置、記憶装置、情報処理システムおよび記憶制御方法

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907867A (en) 1994-09-09 1999-05-25 Hitachi, Ltd. Translation lookaside buffer supporting multiple page sizes
KR960039006A (ko) 1995-04-26 1996-11-21 김광호 디램버스에 접속가능한 불휘발성 반도체 메모리장치
US6154821A (en) 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
JP2001010865A (ja) 1999-06-23 2001-01-16 Ngk Insulators Ltd 窒化珪素焼結体及びその製造方法
JP3872922B2 (ja) 1999-06-28 2007-01-24 株式会社東芝 半導体記憶装置及びメモリ混載ロジックlsi
US6321282B1 (en) 1999-10-19 2001-11-20 Rambus Inc. Apparatus and method for topography dependent signaling
TW451193B (en) 1999-11-30 2001-08-21 Via Tech Inc A method to determine the timing setting value of dynamic random access memory
JP4078010B2 (ja) 2000-03-03 2008-04-23 株式会社日立グローバルストレージテクノロジーズ 磁気ディスク装置及び情報記録方法
US6445624B1 (en) 2001-02-23 2002-09-03 Micron Technology, Inc. Method of synchronizing read timing in a high speed memory system
TWI240864B (en) 2001-06-13 2005-10-01 Hitachi Ltd Memory device
JP4059002B2 (ja) 2001-06-13 2008-03-12 株式会社日立製作所 メモリ装置
CN100489797C (zh) 2001-10-11 2009-05-20 阿尔特拉公司 可编程逻辑设备上的错误检测
US7269709B2 (en) 2002-05-15 2007-09-11 Broadcom Corporation Memory controller configurable to allow bandwidth/latency tradeoff
US6820181B2 (en) 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7386768B2 (en) 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
JP2005234932A (ja) 2004-02-20 2005-09-02 Oki Electric Ind Co Ltd マトリックス状バス接続システムとその低電力方法
KR100564635B1 (ko) 2004-10-25 2006-03-28 삼성전자주식회사 메모리 모듈 내에서의 인터페이스 타이밍을 제어하는메모리 시스템 및 그 방법
US7620783B2 (en) 2005-02-14 2009-11-17 Qualcomm Incorporated Method and apparatus for obtaining memory status information cross-reference to related applications
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
KR100660892B1 (ko) 2005-11-21 2006-12-26 삼성전자주식회사 더블 펌프드 어드레스 스킴의 메모리 장치에서 고속 동작을위해 확장된 유효 어드레스 윈도우로 유효 커맨드를샘플링하는 회로 및 방법
US7461231B2 (en) 2006-01-12 2008-12-02 International Business Machines Corporation Autonomically adjusting one or more computer program configuration settings when resources in a logical partition change
EP2450798B1 (en) 2006-02-09 2013-10-30 Google Inc. Memory circuit system and method
US7716411B2 (en) 2006-06-07 2010-05-11 Microsoft Corporation Hybrid memory device with single interface
US7894289B2 (en) * 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
CN100514488C (zh) 2007-04-16 2009-07-15 中国人民解放军国防科学技术大学 采样点可配置的片外dram数据采样方法
WO2008131058A2 (en) 2007-04-17 2008-10-30 Rambus Inc. Hybrid volatile and non-volatile memory device
US7827360B2 (en) 2007-08-02 2010-11-02 Freescale Semiconductor, Inc. Cache locking device and methods thereof
JP2009054116A (ja) * 2007-08-29 2009-03-12 Buffalo Inc メモリシステムおよび情報処理装置
US8085586B2 (en) * 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US8359521B2 (en) 2008-01-22 2013-01-22 International Business Machines Corporation Providing a memory device having a shared error feedback pin
US20100005214A1 (en) 2008-07-01 2010-01-07 International Business Machines Corporation Enhancing bus efficiency in a memory system
WO2010016817A1 (en) 2008-08-08 2010-02-11 Hewlett-Packard Development Company, L.P. Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
JP5317657B2 (ja) 2008-12-04 2013-10-16 三洋電機株式会社 画像表示装置
CN101751226A (zh) 2008-12-08 2010-06-23 忆正存储技术(深圳)有限公司 非易失存储介质控制器以及非易失存储设备
US8064250B2 (en) 2008-12-16 2011-11-22 Micron Technology, Inc. Providing a ready-busy signal from a non-volatile memory device to a memory controller
KR20130071436A (ko) 2010-05-07 2013-06-28 모사이드 테크놀로지스 인코퍼레이티드 단일 버퍼를 사용하여 복수의 메모리 장치를 동시에 판독하는 방법 및 장치
US8411519B2 (en) 2010-06-04 2013-04-02 Apple Inc. Selective retirement of blocks
US9047178B2 (en) 2010-12-13 2015-06-02 SanDisk Technologies, Inc. Auto-commit memory synchronization
KR20120079682A (ko) 2011-01-05 2012-07-13 삼성전자주식회사 디램 캐시를 포함하는 메모리 장치 및 이를 포함하는 시스템
JP2012146360A (ja) 2011-01-12 2012-08-02 Renesas Electronics Corp 半導体集積回路及び書込処理方法
US9779020B2 (en) 2011-02-08 2017-10-03 Diablo Technologies Inc. System and method for providing an address cache for memory map learning
US9104547B2 (en) 2011-08-03 2015-08-11 Micron Technology, Inc. Wear leveling for a memory device
US9032162B1 (en) 2011-08-12 2015-05-12 Altera Corporation Systems and methods for providing memory controllers with memory access request merging capabilities
US8850155B2 (en) 2011-12-19 2014-09-30 Advanced Micro Devices, Inc. DDR 2D Vref training
US10902890B2 (en) 2012-06-22 2021-01-26 Intel Corporation Method, apparatus and system for a per-DRAM addressability mode
US9280497B2 (en) 2012-12-21 2016-03-08 Dell Products Lp Systems and methods for support of non-volatile memory on a DDR memory channel
BR122016007765B1 (pt) * 2013-03-15 2022-03-03 Intel Corporation Aparelho em comunicação com controlador de memória de host, aparelho acoplado a um módulo de memória e métodos para formar conjuntos eletrônicos
KR102039537B1 (ko) 2013-03-15 2019-11-01 삼성전자주식회사 불휘발성 저장 장치 및 그것의 운영체제 이미지 프로그램 방법
CN105027092B (zh) 2013-03-27 2018-01-30 株式会社日立制作所 具有sdram接口的dram、混合闪存存储器模块
CN104216837A (zh) 2013-05-31 2014-12-17 华为技术有限公司 一种内存系统、内存访问请求的处理方法和计算机系统
JP6165008B2 (ja) 2013-09-25 2017-07-19 キヤノン株式会社 メモリ制御装置、メモリ制御方法、情報機器及びプログラム
WO2015089054A1 (en) 2013-12-12 2015-06-18 Samsung Electronics Co., Ltd. Disaggregated memory appliance
KR102226367B1 (ko) 2014-01-02 2021-03-12 삼성전자주식회사 불휘발성 메모리 장치 및 그것을 포함하는 불휘발성 메모리 시스템
US20150268959A1 (en) 2014-03-21 2015-09-24 Qualcomm Incorporated Physical register scrubbing in a computer microprocessor
US9354872B2 (en) 2014-04-24 2016-05-31 Xitore, Inc. Apparatus, system, and method for non-volatile data storage and retrieval
CN204332379U (zh) * 2014-07-17 2015-05-13 威盛电子股份有限公司 非易失性存储器的存储器控制器和固态驱动器
US10379926B2 (en) * 2014-08-05 2019-08-13 Macronix International Co., Ltd. Method and device for monitoring data error status in a memory
CN104409097B (zh) 2014-10-10 2017-10-13 北京航空航天大学 一种利用电源检测实现非易失性异步逻辑电路的低功耗控制方法
US9460791B1 (en) 2015-12-08 2016-10-04 Inphi Corporation Data clock synchronization in hybrid memory modules
US10621119B2 (en) 2016-03-03 2020-04-14 Samsung Electronics Co., Ltd. Asynchronous communication protocol compatible with synchronous DDR protocol
US10592114B2 (en) * 2016-03-03 2020-03-17 Samsung Electronics Co., Ltd. Coordinated in-module RAS features for synchronous DDR compatible memory
US9830086B2 (en) 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080082750A1 (en) 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
JP2008171163A (ja) * 2007-01-11 2008-07-24 Hitachi Ltd フラッシュメモリモジュール、そのフラッシュメモリモジュールを記録媒体として用いたストレージ装置及びそのフラッシュメモリモジュールのアドレス変換テーブル検証方法
US20100332943A1 (en) 2009-06-29 2010-12-30 Sandisk Corporation Method and device for selectively refreshing a region of a non-volatile memory of a data storage device
JP2012089137A (ja) * 2010-10-20 2012-05-10 Samsung Electronics Co Ltd 半導体装置、これを含むメモリモジュール、メモリシステム及びその動作方法
JP2014157391A (ja) * 2013-02-14 2014-08-28 Sony Corp 記憶制御装置、記憶装置、情報処理システムおよび記憶制御方法

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