KR102533966B1 - Semiconductor device test apparatus - Google Patents

Abstract

The present invention relates to a semiconductor device testing apparatus, comprising: an insert 2 accommodating a semiconductor device 1 and having an insert pocket hole; a socket guide (3) having a guide pin for guiding an engagement position with the insert and having a socket guide hole; a test socket 4 connected to the semiconductor device 1 accommodated in the insert 2, coupled to the socket guide, and having a socket hole; The socket guide 3 is seated and includes a board 5 having one or more board guide pins, the board guide pins of the board 5 perpendicular to the socket hole, the socket guide hole, and the insert pocket hole. It is characterized in that each part is fixed and aligned by penetrating through.

Description

Semiconductor device test device {SEMICONDUCTOR DEVICE TEST APPARATUS}

The present invention relates to a semiconductor device testing apparatus, and more particularly, by improving a method of aligning a semiconductor device and a board and contacting a semiconductor device, and a fine pitch semiconductor package. It relates to a semiconductor device test apparatus capable of improving productivity by increasing alignment precision and reducing accumulation tolerance in a package test.

In general, semiconductor devices may be formed on a silicon wafer used as a semiconductor substrate by repeatedly performing a series of manufacturing processes, and the semiconductor devices thus formed may be manufactured as finished products through a dicing process, a bonding process, and a packaging process. .

These semiconductor devices may be judged to be good or defective through electrical property tests. A semiconductor device test apparatus including a plurality of transfer modules for transferring semiconductor devices, a test module for inspecting semiconductor devices, and an interface module for connecting the semiconductor devices and the test module to each other may be used for the electrical property test. there is.

The interface module may include an interface board disposed between the test module and the insert accommodating the semiconductor devices, and socket guides mounted on the interface board.

Test sockets for connection with semiconductor devices are mounted on the socket guide, and passive devices such as resistors, condensers, and amplifiers for signal conversion and power supply devices for testing semiconductor devices can be mounted on the lower surface of the interface board. there is.

Meanwhile, the alignment of the insert and the test socket may be achieved by alignment between the socket guide and the insert and alignment between the socket guide and the test socket. Here, the alignment between the socket guide and the insert is achieved by a guide pin provided in the socket guide and a guide hole formed in the insert to insert the guide pin, and the alignment between the socket guide and the test socket is achieved by the guide pin provided in the socket guide and the guide hole. This can be done by a guide hole formed in the test socket to insert the pin.

However, since the positions of the guide pins for aligning the insert and the socket guide and the guide pins for aligning the socket guide and the test socket are different, the assembly tolerance generated in the assembly of the socket guide and the insert and the assembly of the socket guide and the test socket Accumulated tolerances occur due to assembly tolerances that occur. This cumulative tolerance causes an alignment error between the insert and the socket test, which causes an alignment error between the semiconductor device and the socket test.

In particular, as semiconductor devices having a fine pitch of solder balls of about 0.3 mm or less are released, precise alignment between the solder balls and contact terminals of the test socket is also required. Accordingly, the cumulative tolerance increases the influence of the fine-pitch alignment between the solder balls and the contact terminals, causing a problem.

1 is a schematic explanatory diagram of a semiconductor wafer and a semiconductor device according to the prior art. In FIG. 1 , a plurality of chips are manufactured as one semiconductor device 20 on a semiconductor wafer 10 , and the semiconductor device 20 is connected by a plurality of solder balls 30 .

In memory semiconductors, current major models have a pitch of 0.4 to 0.5 mm, and some models have a pitch of 0.27 to 0.3 mm. In addition, this pitch tends to gradually decrease. For example, in the case of a 0.3 pitch, the radius of a ball should theoretically not exceed 0.15 mm, and in practice it is about 0.06 mm.

2 is an exploded perspective view of a semiconductor device test apparatus according to the prior art, and FIG. 3 is a cross-sectional view of the coupled state of FIG. 2 .

2 and 3, the semiconductor device testing apparatus includes a device 1, an insert 2, a socket guide 3, a socket 4, and a board 5. It has already been described that it is important to align each part for a test of a semiconductor device.

Referring to FIG. 2, when viewed through a side cross-sectional view in a state in which the respective parts are engaged and coupled to each other, a board PCB (printed circuit board) hole (HOLE) of a board 5 for alignment for semiconductor device testing 54 and the socket guide bottom pin 33 of the socket guide 3 are coupled to the socket hole 42 of the socket 4. In addition, the pocket guide pin 31 of the socket guide 3 is inserted into the insert pocket hole 2 of the insert 2 coupled to the upper portion. .

In the above state, looking at the accumulated tolerance, the board and socket hole-socket guide bottom hole tolerance is ±0.025, the board and socket guide hole and Socket Guide Bottom Hole Distance Tolerance is ±0.01, Socket Guide Pocket Guide Pin and Pocket Guide Tolerance is ±0.025, Socket Guide Bottom Pin (S/G Bottom Hole) Pin) and pocket guide pin (Pocket Guide Pin) distance tolerance is ± 0.02, there was a problem that the cumulative tolerance of the total cumulative tolerance ± 0.08 occurs.

In addition, when the tolerance is increased, a ball of a fine pitch (0.3 pitch or less) semiconductor device may be out of the pad range, resulting in a contact fail problem.

[Prior art literature]

Korean Patent Publication No. 10-2017-0142608 (published on December 28, 2017)

The present invention has been made to solve the above problems of the prior art, and as a post-process for semiconductor manufacturing, to provide a semiconductor test device, to facilitate alignment of a semiconductor device and a board before a semiconductor device test process. By doing so, it is to provide a new type of semiconductor device test device that can reduce the effort and time required for alignment and also reduce the accumulation tolerance.

According to a preferred embodiment of the present invention for achieving the above object,

In the semiconductor device test device,

an insert accommodating a semiconductor device and having an insert pocket hole;

a socket guide having a guide pin for guiding an engagement position with the insert and having a socket guide hole;

a test socket connected to the semiconductor device accommodated in the insert, coupled to the socket guide, and having a socket hole;

The test socket is coupled, the socket guide is seated, and includes a board having one or more board guide pins;

The board guide pin of the board vertically penetrates the socket hole, the socket guide hole, and the insert pocket hole to fix and align the test socket, socket guide, and insert pocket hole to the board. do.

In addition, it is characterized in that there are three guide positions for guiding coupling of the board, the test socket, the socket guide, and the insert.

In addition, it is characterized in that the test socket, socket guide and inserts are guided from the board at once through the board guide pin of the board to reduce the cumulative tolerance to ±0.045 mm.

According to the semiconductor device test device according to the present invention described above, as a post-process for semiconductor manufacturing, to provide a semiconductor test device, by making it easy to align the semiconductor device and the board before the semiconductor device test process, the alignment ( By reducing the effort and time required for Align and reducing the accumulated tolerance, it is possible to meet more favorable conditions for contact and increase productivity.

1 is a schematic explanatory diagram of a semiconductor wafer and a semiconductor device according to the prior art.
2 is an exploded perspective view of a semiconductor device testing apparatus according to the prior art.
Figure 3 is a cross-sectional view of the coupled state of Figure 2;
4 is an exploded perspective view of a semiconductor device testing apparatus according to a preferred embodiment of the present invention.
Figure 5 is a cross-sectional view of the coupled state of Figure 4;
FIG. 6 is a partial cross-sectional perspective view of the coupled state of FIG. 4 .

Since the present invention can make various changes and have various embodiments, specific embodiments will be illustrated in the drawings and described in detail.

However, this is not intended to limit the present invention to specific embodiments, and should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "include" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that the presence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in the present application, they should not be interpreted in an ideal or excessively formal meaning. don't

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. In order to facilitate overall understanding in the description of the present invention, the same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an exploded perspective view of a semiconductor device testing apparatus according to a preferred embodiment of the present invention, FIG. 5 is a cross-sectional view of a coupled state of FIG. 4 , and FIG. 6 is a partial cross-sectional perspective view of the coupled state of FIG. 4 .

4 to 6, a semiconductor device testing apparatus according to a preferred embodiment of the present invention includes a device 1, an insert 2, a socket guide 3, a socket 4, and a board 5 ). It has already been described that it is important to align each part for a test of a semiconductor device.

In the following description, parts overlapping with those of the prior art will be omitted and description will be made focusing on other parts.

The semiconductor device test apparatus according to the present invention,

an insert 2 accommodating the semiconductor device 1 and having an insert pocket hole 22;

a socket guide (3) having a guide pin for guiding an engagement position with the insert and having a socket guide hole (32);

a test socket (4) in contact with the semiconductor device accommodated in the insert, coupled to the socket guide, and having a socket hole (42);

The test socket 4 is coupled to an upper surface, the socket guide 3 is seated, and includes a board 5 having one or more board guide pins 52,

The board guide pin 52 of the board 5 vertically penetrates the socket hole 42, the socket guide hole 32, and the insert pocket hole 22 to form a test socket 4 and a socket guide 3. , It is characterized in that the insert (2) is fixed to the board (5) to align.

In addition, it is characterized in that there are three guide positions for guiding coupling of the board 5, the test socket 4, the socket guide 3, and the insert 2.

Referring to FIGS. 4 to 6 , the insert pocket hole 22 , the socket guide hole 32 , and the board guide pin 52 pass through and are coupled to the socket hole 42 .

In the present invention, the cumulative tolerance is improved by reducing the location of the guide to one location. That is, the cumulative tolerance was reduced from ±0.08 to ±0.045.

Looking at the tolerance, it can be seen that the Board Pin-Socket & Socket Guide & Pocket Hole tolerance is ±0.025, the Board Pin-Socket & Socket Guide & Pocket Hole distance tolerance is ±0.02, and the total cumulative tolerance is ±0.045.

When testing the existing semiconductor device (1) in the test process, after stacking the semiconductor device (1) on the insert (2), insert (2) on the socket guide (3) The test is performed by placing the semiconductor device (1) on the assembled board (5) and socket (4) by guiding the .

In the semiconductor device test process as described above, conventionally, since the guide portion of each of the parts 1, 2, 3, 4, and 5 is made separately, there is a problem in that the accumulated tolerance due to processing and assembly increases. However, in the present invention, a guide pin 52 is created on the board 5 to guide the rest of the parts from the board at once to reduce the accumulation tolerance. showing a way

As described above, in the coupling between components, as in FIG. 3, the tolerance when the socket guide bottom pin 33 is coupled to the socket hole 42 and the board PCB hole 54, and the pocket guide pin 31 By creating a guide pin 52 on the board 5 with an accumulated tolerance of ±0.08 mm due to the tolerance when the insert is coupled to the pocket hole 22, guide the remaining parts from the board at once ( Guide), it was possible to reduce the cumulative tolerance to ±0.045 mm.

As described above, according to the present invention, it is possible to easily align the semiconductor device and the board before the semiconductor device test process, thereby reducing the effort and time required for alignment and reducing the accumulation tolerance. It allows more favorable conditions for contact and increases productivity.

As described above, the optimal embodiment has been disclosed in the drawings and specifications. Although specific terms are used herein, they are only used for the purpose of describing the present invention and are not used to limit the scope of the present invention described in the claims or defining the meaning. Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: semiconductor element
2: insert
3: Socket Guide
4: socket
5: board
22: insert pocket hole
32: socket guide hole
42: socket hole

Claims (3)

In the semiconductor device test device,
an insert accommodating a semiconductor device and having an insert pocket hole;
a socket guide having a guide pin for guiding an engagement position with the insert and having a socket guide hole;
a test socket contacting the semiconductor device stored in the insert, coupled to the socket guide, and having a socket hole;
The test socket is coupled to an upper surface, the socket guide is seated, and includes a board having one or more board guide pins;
The board guide pin of the board vertically penetrates the socket hole, the socket guide hole, and the insert pocket hole to fix and align the test socket, the socket guide, and the insert to the board.
According to claim 1,
The semiconductor device test apparatus, characterized in that three guide positions for guiding coupling of the board, the test socket, the socket guide and the insert.
According to claim 1,
Semiconductor device test characterized in that the cumulative tolerance can be reduced to ±0.045 mm by guiding the test socket, socket guide and insert from the board at once through the board guide pin of the board. Device.

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