KR102509114B1 - Electroluminescent Display Device And Driving Method Of The Same - Google Patents

Abstract

An electroluminescent display device of the present invention includes a display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels; and a panel driving circuit for driving the signal lines of the display panel, compensating the electron mobility of the driving elements by simultaneously compensating the threshold voltage of the driving element for pixel lines belonging to the same display block, and then writing pixel data thereon. contains a lo

Description

Electroluminescent Display Device And Driving Method Of The Same}

The present invention relates to an electroluminescent display device and a driving method thereof.

The electroluminescent display device is roughly divided into an inorganic light emitting display device and an organic light emitting display device according to the material of the light emitting layer. Among them, the active matrix type organic light emitting display device includes an organic light emitting diode (OLED), which is a representative field light emitting diode that emits light by itself, and has a response speed It is fast and has the advantages of high luminous efficiency, luminance and viewing angle.

An OLED, which is a self-luminous device, includes an anode electrode and a cathode electrode, and an organic compound layer formed between them. An organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form and adjusts the luminance of an image implemented in the pixels according to the gray level of image data. The driving TFT controls the driving current input to the OLED according to the voltage applied between its gate electrode and its source electrode (hereinafter referred to as "gate-source potential"). Depending on the driving current, the amount of light emitted and the luminance of the OLED are determined.

In general, when the driving TFT operates in a saturation region, the driving current Ids flowing between the drain and source of the driving TFT is expressed as follows.

Ids = 1/2*(μ*C*W/L)*(Vgs-Vth) ²

Here, μ is the electron mobility, C is the capacitance of the gate insulating film, W is the channel width of the driving TFT, and L is the channel length of the driving TFT. Further, Vgs represents a potential between the gate and source of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT.

Electrical characteristics of the pixels, such as the threshold voltage (Vth) of the driving TFT and the electron mobility (μ) of the driving TFT, are factors that determine the driving current (Ids), and thus must be the same in all pixels. However, electrical characteristics of pixels change due to various causes such as process variation and change over time, and thus luminance between pixels may vary even when the same data voltage is applied. Such luminance deviation causes deterioration in image quality and shortened lifespan of the display device.

Internal compensation techniques are known to compensate for luminance variations between pixels. The internal compensation technology properly applies a gate signal and a data signal to compensate for changes in the threshold voltage (Vth) and electron mobility (μ) of the driving TFT during real-time driving, thereby increasing the potential (Vgs) between the gate and source of the driving TFT. It is a voltage programming technique that sets the

There are as many pixel lines as the vertical resolution in the display panel. A plurality of pixels adjacent to each other along a horizontal direction are disposed on each pixel line. The voltage programming for the internal compensation method is sequentially performed by one pixel line within one frame period. Accordingly, each pixel line requires a time equal to one horizontal period (1H) for the voltage programming. One horizontal period (1H) is the time obtained by dividing one frame period by the vertical resolution. The pixels of each pixel line do not emit light while the voltage programming is in progress, but emit light after the voltage programming is completed. In other words, the voltage-programmed pixel line displays an image by emitting light for a remaining period of one frame period, that is, a time equal to (vertical resolution-1) horizontal periods.

One horizontal period (1H) varies according to a frame frequency defining one frame period and a vertical resolution. One horizontal period (1H) becomes shorter as the frame frequency increases when the vertical resolution is the same (high-speed drive model). One horizontal period (1H) becomes shorter as the vertical resolution increases when the frame frequency is the same (high resolution model). 1 horizontal period (1H) becomes shorter when both vertical resolution and frame frequency increase (high speed drive & high resolution model).

If one horizontal period (1H) is too short, the time for the voltage programming is insufficient, so that changes in the threshold voltage (Vth) and electron mobility (μ) of the driving TFT cannot be adequately compensated. A method to increase the compensation performance is required.

Accordingly, an object of the present invention is to provide an electroluminescent display device and a method for driving the same that sufficiently secures compensation time and improves compensation performance by driving pixels in units of display blocks when compensating for deviations in electrical characteristics of pixels using an internal compensation method. is to provide

In order to achieve the above object, the electroluminescent display device of the present invention includes a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels. a display panel provided with; and a panel driving circuit for driving the signal lines of the display panel, compensating the electron mobility of the driving elements by simultaneously compensating the threshold voltage of the driving element for pixel lines belonging to the same display block, and then writing pixel data thereon. contains a lo

The present invention is a method for driving an electroluminescent display device in which a plurality of pixel lines are provided on a display panel, and a plurality of pixels including a driving element and a light emitting element are disposed on each pixel line. driving pixel lines in units of display blocks; and compensating the electron mobility of the driving element by simultaneously compensating the threshold voltage of the driving element for pixel lines belonging to the same display block by driving the signal lines of the display panel, and then writing pixel data thereon. include

The present invention divides and drives pixel lines on which pixels are arranged in units of display blocks, and simultaneously compensates the threshold voltages of driving elements for pixel lines belonging to the same display block, thereby securing a sufficient threshold voltage compensation time of driving elements. Compensation performance can be improved.

Furthermore, in the present invention, in the same display block, after sequentially compensating for the electron mobility of driving elements on a per-pixel line basis, pixels disposed on the pixel lines are simultaneously connected to a high-potential pixel driving voltage and the light emitting elements emit light at the same time. , it is possible to eliminate a light emission period deviation between pixel lines according to pixel data written in a line sequential manner.

Furthermore, within the same display block, the present invention sequentially initializes the source potential of the driving element lower than the operating point voltage of the light emitting element in units of pixel lines before simultaneously compensating for the threshold voltage of the driving element, and converts pixel data into a line sequential method. , and the light emitting element sequentially emits light in units of pixel lines, it is possible to eliminate a light emitting period deviation between pixel lines according to pixel data written in a line sequential manner.

Furthermore, the present invention simultaneously initializes the source potential of the driving element to be lower than the operating point voltage of the light emitting element before simultaneously compensating for the threshold voltage of the driving element within the same display block, and writes pixel data in a line non-sequential manner to emit light. By non-sequentially emitting light in units of pixel lines, a luminance deviation at a boundary between adjacent display blocks is minimized.

Furthermore, in the present invention, when the number of pixel lines belonging to the same display block is J (J is a positive integer greater than or equal to 2), the position of each display block on the display panel is determined by K (K is a positive integer smaller than J). By shifting the pixel lines by two pixel lines, it is possible to spatially disperse the block boundary line having a large luminance variance so that it is less noticeable to the user.

1 is a diagram showing an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 is a view showing a pixel array formed in the display panel of FIG. 1 .
3 to 5 are diagrams illustrating a block driving method of driving pixels in units of display blocks according to an embodiment of the present invention.
6 is a diagram showing an equivalent circuit of a pixel for implementing the block driving method of the present invention.
FIG. 7 is a diagram showing a driving waveform for driving the pixels shown in FIG. 6 in units of display blocks and a change in potential of a driving TFT included in a specific pixel.
8A to 8D are diagrams sequentially showing operating states of the specific pixels.
9 is a diagram showing that emission periods vary between pixel lines within the same display block.
10 is a diagram showing a driving method for eliminating a light emission period deviation between pixel lines.
FIG. 11 is a diagram showing an equivalent circuit of a pixel for implementing the driving scheme of FIG. 10 .
FIG. 12 is a diagram showing another driving method for eliminating the emission period deviation between pixel lines.
13 and 14 are diagrams illustrating a driving method for minimizing visibility of a block boundary due to a variation in an emission period between pixel lines.
15A and 16B are diagrams showing other driving schemes for minimizing block boundary visibility due to emission period deviation between pixel lines.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various forms different from each other, only these embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to completely inform the person who has the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, so the present invention is not limited to the details shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as 'on ~', 'upon ~', '~ below', 'next to', etc., 'right' Or, unless 'directly' is used, one or more other parts may be located between the two parts.

Although first, second, etc. may be used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numbers designate substantially like elements throughout the specification.

Features of various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or together in an association relationship. there is.

In the present invention, a pixel circuit formed on a substrate of a display panel may be implemented as a TFT having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since electrons are carriers, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In the case of a p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. Since holes flow from the source to the drain side in the p-type TFT, current flows from the source to the drain side. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can be changed depending on the applied voltage.

Hereinafter, the gate-on voltage (Gate On Voltage) is the voltage of the gate signal at which the TFT can be turned on. A gate off voltage is a voltage at which a TFT can be turned off. In NMOS, the gate on voltage is the gate high voltage and the gate off voltage is the gate low voltage. In PMOS, the gate on voltage is the gate low voltage and the gate off voltage is the gate high voltage.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following embodiments, the electroluminescent display device will be mainly described as an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical concept of the present invention is not limited to an organic light emitting display device and may be applied to an inorganic light emitting display device including an inorganic light emitting material.

FIG. 1 shows an organic light emitting display device according to an embodiment of the present invention, and FIG. 2 shows a pixel array formed on the display panel of FIG. 1 .

Referring to FIGS. 1 and 2 , an organic light emitting display device according to an exemplary embodiment of the present invention includes a display panel 10 , a panel driving circuit, and a timing controller 11 .

A plurality of data lines 14 and a plurality of gate lines 15 intersect on the display panel 10 , and pixels PIX are arranged in a matrix form at each crossing area. Each of the pixels PIX includes a light emitting element (hereinafter, OLED) and a driving element (hereinafter, driving TFT), and compensates for the threshold voltage and electron mobility of the driving TFT according to the source follower internal compensation method. The set gate-source voltage of the driving TFT is maintained for approximately one frame period to display a desired grayscale.

The pixel PIX of the present invention may have a structure to which a source follower internal compensation scheme may be applied. Each pixel PIX may include switch TFTs for controlling a potential between the gate and source of the driving TFT. Each pixel PIX may further include a switch TFT for controlling emission timing of the OLED. Switch TFTs of each pixel PIX are switched by gate signals applied from gate lines 15 . Each pixel PIX may be connected to two or three gate lines 15 according to its circuit configuration. Although FIG. 2 shows one gate line 15 connected to each pixel PIX for convenience of explanation, it should be noted that at least two or more gate lines 15 may be connected to each pixel PIX. Each pixel PIX may receive a high potential pixel driving voltage EVDD and a low potential pixel driving voltage EVSS from a power generator (not shown).

A pixel array as shown in FIG. 2 is formed on the display panel 10 by the pixels PIX arranged in a matrix form. The pixel array is divided into a plurality of display blocks BLK1 to BLKj along a data line extension direction (eg, a vertical direction), and each display block includes a plurality of pixel lines L#1 to L#n. can Here, each pixel line denotes a set of pixels PIX disposed adjacent to each other along a gate line extension direction (eg, a horizontal direction) to receive pixel data at the same time. In order to sufficiently secure the threshold voltage compensation time of the driving TFT belonging to the pixels PIX, the threshold voltage compensation timing of the driving TFT targets the pixel lines L#1 to L#n included in the same display block. can be done simultaneously.

The panel driving circuit drives the signal lines 14 and 15 of the display panel 10 under the control of the timing controller 11 to target the pixel lines L#1 to L#n belonging to the same display block. , The threshold voltage of the driving TFT is simultaneously compensated and then the electron mobility of the driving TFT is compensated, thereby securing a sufficient threshold voltage compensation time within one frame period to enhance compensation performance. As the number of pixel lines (L#1 to L#n) belonging to the same display block increases, threshold voltage compensation performance in the resolution display block improves, but light emission between the pixel lines (L#1 to L#n) is increased. Due to the period deviation, a boundary line between adjacent display blocks may be recognized. Accordingly, the number of pixel lines L#1 to L#n belonging to the same display block may be appropriately set in consideration of the threshold voltage compensation performance and the visibility of the boundary between the display blocks.

3 to 5 are diagrams illustrating a block driving method of driving pixels in units of display blocks according to an embodiment of the present invention.

3 to 5 , the panel driving circuit of the present invention divides and drives the display panel 10 into display blocks BLK1 to BLKj (S1). In other words, the panel driving circuit drives the signal lines 14 and 15 of the display panel 10 in units of display blocks BLK1 to BLKj each including the pixel lines L#1 to L#n. (S1).

The panel driving circuit sequentially compensates for the threshold voltage and electron mobility of the driving TFT in units of display blocks, while simultaneously adjusting the threshold voltage of the driving TFT for pixel lines (L#1 to L#n) belonging to the same display block. After the compensation, the electron mobility of the driving TFT in the same display block is compensated in units of pixel lines (S2 and S3).

Specifically, the panel driving circuit simultaneously compensates the threshold voltages of the driving TFTs for the pixel lines L#1 to L#n of the first display block BLK1, and then in the first display block BLK1. Electron mobility of the driving TFT is compensated in units of pixel lines. Subsequently, the panel driving circuit simultaneously compensates the threshold voltage of the driving TFT for the pixel lines L#1 to L#n of the second display block BLK2, and then the pixels in the second display block BLK2. Electron mobility of the driving TFT is compensated for on a line-by-line basis. In this way, the panel driving circuit compensates for the threshold voltage and electron mobility of the driving TFT up to the jth display block BLKj.

Subsequently, the panel driving circuit maintains the gate-source voltage of the driving TFT set in step S3 to the corresponding pixel PIX, applies a driving current to the OLED of each pixel PIX, and emits light to display an image. Do (S4).

Meanwhile, the gate signal of FIG. 6 corresponds to the first gate signal for controlling the gate potential of the driving TFT. It should be noted that the second gate signal for controlling the source potential of the driving TFT is not shown in FIG. 6 for convenience.

In each display block of FIG. 6, a period in which the threshold voltage of the driving TFT is simultaneously compensated is marked as "D1", and a period until the first pixel data is written after the threshold voltage is compensated is marked as "D2". D2 indicates a holding period during which the gate-source potential of the driving TFT is maintained.

6 is a diagram showing an equivalent circuit of a pixel for implementing the block driving method of the present invention.

Referring to FIG. 6 , the pixel PIX of the present invention may include an OLED, a driving TFT (DT), a storage capacitor (Cst), a first switch TFT (ST1), and a second switch TFT (ST2).

The OLED includes an anode electrode connected to the source node N2, a cathode electrode connected to the low potential pixel driving voltage terminal EVSS, and an organic compound layer positioned between the anode electrode and the cathode electrode.

The driving TFT (DT) controls the driving current (Ioled) applied to the OLED according to the gate-source potential (Vgs). The driving TFT (DT) has a gate connected to the gate node N1, a drain to which the high-potential pixel driving voltage EVDD is applied, and a source connected to the source node N2.

The storage capacitor Cst is connected between the gate node N1 and the source node N2.

The first switch TFT (ST1) is switched according to the first gate signal (WS1) to control the gate potential of the driving TFT (DT). The first switch TFT (ST1) has a gate connected to the first gate line 15A, a drain connected to the data line 14, and a source connected to the gate node N1. The first gate signal WS1 includes a first gate pulse synchronized with the offset voltage Vofs and a second gate pulse synchronized with the data voltage Vdata.

The second switch TFT (ST2) is switched according to the second gate signal (WS2), and controls the source potential of the driving TFT (DT). The gate of the second switch TFT (ST2) is connected to the second gate line 15B, the drain of the second switch TFT (ST2) is connected to the source node N2, and the source of the second switch TFT (ST2) An initialization voltage (Vinit) is applied. Here, the initialization voltage Vinit is used to initialize the source potential of the driving TFT (DT) lower than the operating point voltage of the OLED.

FIG. 7 is a diagram showing a driving waveform for driving the pixels shown in FIG. 6 in units of display blocks and a change in potential of a driving TFT included in a specific pixel. 8A to 8D are diagrams sequentially showing operating states of the specific pixels.

Referring to FIG. 7 , driving signals for the i-th display block BLKi and the j-th display block BLKj adjacent to each other are shown. Referring to the i-th display block BLKi, the first gate signals WS1 i(n-2), WS1 i(n-1), and WS1 i(n) each generate a first gate pulse Pa and the second gate pulse Pb are applied to the first gate lines 15A of the three pixel lines L#n-2, L#n-1, and L#n in the form of multi-pulses, The two gate signals (WS2 i(n-2), WS2 i(n-1), and WS2 i(n)) are each in the form of a single pulse to three pixel lines (L#n-2, L#n-1). , L#n) is applied to the second gate line 15B. The first gate pulses Pa of the first gate signals WS1 i(n-2), WS1 i(n-1), and WS1 i(n) are applied simultaneously, and the second gate signals WS2 i (n-2), WS2 i(n-1), and WS2 i(n)) are also applied simultaneously. On the other hand, the second gate pulses Pb of the first gate signals WS1 i(n-2), WS1 i(n-1), and WS1 i(n) are sequentially applied according to the line sequential method.

In this case, an offset voltage is applied to the data line 14 in response to the first pulses P1 of the first gate signals WS1 i(n-2), WS1 i(n-1), and WS1 i(n). (Vofs) is applied, and the data line ( 14) is applied with the gradation voltage Vdata for image display.

Referring to FIGS. 8A to 8D together with FIG. 7 , operation states of the pixels PIX of FIG. 6 included in the n-th pixel line L#n of the i-th display block BLKi will be sequentially described as follows. same.

As shown in FIG. 7 , the pixel PIX of FIG. 6 is driven in the order of an initialization period TP1 , a threshold voltage compensation period TP2 , an electron mobility compensation period TP3 , and an emission period TP4 .

In the initialization period TP1 of FIG. 8A , the first switch TFT ST1 is turned on according to the first gate pulse Pa of the first gate signal WS1 to apply an offset voltage Vofs to the gate node N1. and the second switch TFT ST2 is turned on according to the second gate signal WS2 to apply the initialization voltage Vinit to the source node N2. Here, the offset voltage Vofs is set higher than the threshold voltage or higher than the initialization voltage Vinit. Therefore, since the gate-source potential of the driving TFT (DT) is higher than the threshold voltage, the driving TFT (DT) is turned on and the OLED does not emit light.

Subsequently, the gate potential VN1 of the driving TFT DT is maintained at the offset voltage Vofs by the first switch TFT ST1 maintained in the turned-on state during the threshold voltage compensating period TP2 of FIG. 10B. At this time, the second switch TFT (ST2) is turned off according to the second gate signal (WS2), and as a result, the source potential (VN2) of the driving TFT (DT) is the current flowing between the drain and source of the driving TFT (DT) ( Ids) gradually rises from the initialization voltage Vinit. At this time, the source potential (VN2) of the driving TFT (DT) rises until the gate-source voltage (Vgs) of the driving TFT (DT) reaches the threshold voltage (Vth). The sampled threshold voltage Vth of the driving TFT DT is compensated by being stored in the storage capacitor Cst. It takes a long time until the gate-source voltage (Vgs) of the driving TFT (DT) reaches the threshold voltage (Vth). According to the present invention, it is possible to sufficiently secure the threshold voltage compensation period TP2 within one frame period through simultaneous compensation for each block, thereby increasing the accuracy of threshold voltage compensation.

Subsequently, after passing through a predetermined holding period in the electron mobility compensation period TP3 of FIG. 8C, the first switch TFT ST1 is turned on according to the second gate pulse Pb of the first gate signal WS1. The gate potential (VN1) of the driving TFT (DT) is raised by applying the gradation voltage (Vdata) for image display to the gate node (N1). Then, the source potential (VN2) of the driving TFT (DT) also rises according to the electron mobility characteristics of the driving TFT (DT), and eventually the storage capacitor (Cst) has the gradation voltage (Vdata) for image display and the threshold voltage (Vth) The voltage (Vdata+Vth-ㅿVμ) obtained by subtracting the amount of voltage change (ㅿVμ) according to the electron mobility characteristics from the sum of is stored. The voltage (Vdata+Vth-ㅿVμ) stored in the storage capacitor Cst becomes the gate-to-source voltage Vgs for which the electron mobility of the driving TFT DT is compensated. This gate-source voltage (Vgs) is set in inverse proportion to the electron mobility of the driving TFT (DT). In other words, when the electron mobility of the driving TFT (DT) is high, the gate-source voltage (Vdata+Vth-ㅿVμ) becomes small, and conversely, when the electron mobility of the driving TFT (DT) is small, the gate-source voltage ( Vdata+Vth-ㅿVμ) increases. Through this, the electron mobility of the driving TFT (DT) is compensated.

Then, in the light emission period TP4 of FIG. 8D, both the first switch TFT ST1 and the second switch TFT ST2 are turned off, and the driving TFT DT is turned off during the electron mobility compensation period TP3. Operating by the voltage level (Vdata+Vth-ㅿVμ) stored in Cst), the driving current (Ioled) in which the threshold voltage (Vth) and the electron mobility (μ) are compensated is applied to the OLED. The OLED receives a driving current (Ioled) proportional to (Vdata -ㅿVμ) ² . At this time, since the source potential of the driving TFT (DT) is higher than the operating point voltage of the OLED, the OLED emits light by the driving current (Ioled).

9 is a diagram showing that emission periods vary between pixel lines within the same display block.

Referring to FIG. 9 , for each pixel line, a holding period FP1 to FP4 exists from after the threshold voltage Vth of the driving TFT DT is compensated until the electron mobility of the driving TFT DT is compensated. . During the holding period FP1 to FP4, both the gate node N1 and the source node N2 of the driving TFT DT are maintained in a floating state.

As described above, after the threshold voltages of the driving TFTs (DT) are simultaneously compensated for the pixel lines belonging to the same display block, the electron mobility of the driving TFTs (DT) in the same display block is sequentially measured in pixel line units. In the case of compensation, the emission period differs due to a difference in holding period between pixel lines in the same display block.

In FIG. 9, targeting the four pixel lines (L#n-3, L#n-2, L#n-1, and L#n), the pixel lines with the late pixel data writing have a holding period (FP1 to FP4). It is shown that the light emission period (EP1 to EP4) is shortened while the length is increased. 9, the first gate signals WS1 i(n-3), WS1 i(n-2), WS1 i(n-1), and WS1 i(n) and the second gate signals WS2 i( n-3), WS2 i(n-2), WS2 i(n-1), and WS2 i(n)) maintain a low level during the holding period FP1 to FP4 of the corresponding pixel line. The holding period (FP1 to FP4) is the shortest in the pixel line (L#n-3) in which the order of compensation for the electron mobility of the driving TFT (DT) is the fastest, and the compensation for the electron mobility of the driving TFT (DT) It is the longest in the pixel line (L#n) with the last sequence. In addition, the light emission period (EP1 to EP4) is the longest in the pixel line (L#n-3) where the compensation order for the electron mobility of the driving TFT (DT) is the fastest. The sequence of compensation for is the shortest in the pixel line (L#n) which is the latest.

In other words, in each display block, the light emission period is longest at the pixel line where pixel data is written fastest (ie, the first pixel line) and shortest at the pixel line where pixel data is written the slowest (ie, last pixel line). . Since the luminance increases as the emission period increases when displaying the same grayscale, a luminance deviation may occur between pixel lines. When pixel data is sequentially written to the pixel lines L#n-3, L#n-2, L#n-1, and L#n in a line-sequential manner, the luminance deviation between the pixel lines is It is the largest at the boundary between display blocks, so that the boundary between display blocks can be recognized as a line dim. Accordingly, a method for minimizing line dim between display blocks while increasing compensation accuracy is proposed below.

10 is a diagram showing a driving method for eliminating a light emission period deviation between pixel lines. 11 is a diagram showing an equivalent circuit of a pixel for implementing the driving method of FIG. 10 .

The panel driving circuit of the present invention sequentially writes pixel data to the pixel lines belonging to the same display block according to a line sequential method in order to eliminate the variation in emission period between the pixel lines belonging to the same display block, thereby enabling electromigration of the driving TFT. After sequentially compensating for the degree, the OLED emits light at the same time.

This will be described in detail with reference to FIGS. 10 and 11.

The pixel PIX of FIG. 11 is different from the pixel PIX of FIG. 6 in that it further includes a third switch TFT ST3, and the rest of the configuration is the same as that of the pixel PIX of FIG. The third switch TFT (ST3) is switched according to the third gate signal (EM) to control the drain potential of the driving TFT (DT). In other words, the third switch TFT (ST3) is switched according to the third gate signal (EM) applied from the third gate line (15C), and the input terminal of the high-potential pixel driving voltage (EVDD) and the driving TFT (DT) are switched. Controls the electrical connection between drains. The gate of the third switch TFT (ST3) is connected to the third gate line (15C), the drain of the third switch TFT (ST3) is connected to the input terminal of the high-potential pixel driving voltage (EVDD), and the third switch TFT ( The source of ST3) is connected to the drain of the driving TFT (DT).

The first to fourth pixel lines L#1, L#2, L#3, and L#4 including a plurality of pixels PIX of FIG. 11 are driven as shown in FIG. 10 . That is, the first to fourth pixel lines L#1, L#2, L#3, and L#4 belonging to the same display block have an initialization period AP, a threshold voltage compensation period BP, and electron mobility. It is driven in order of the compensation period (CP) and the light emission period (DP).

The first gate pulse (Pa) of the first gate signals WS1(1), WS1(2), WS1(3), and WS1(4) is the second in the initialization period AP and the threshold voltage compensating period BP. It is simultaneously applied to the first to fourth pixel lines L#1, L#2, L#3, and L#4. The second gate signals WS2(1), WS2(2), WS2(3), and WS2(4) are applied to the first to fourth pixel lines L#1, L#2, and L#2 in the initialization period AP. L#3 and L#4) are simultaneously applied with an on level. Also, the third gate signals EM(1), EM(2), EM(3), and EM(4) are applied to the first to fourth pixel lines in the initialization period AP and the threshold voltage compensating period BP. The ON level is simultaneously applied to the L#1, L#2, L#3, and L#4.

Accordingly, during the initialization period AP, the source of the driving TFT DT in the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4. The potential is initialized at the same time lower than the operating point voltage of the OLED. And, during the threshold voltage compensating period BP, the driving TFTs DT in the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4. The threshold voltage of is compensated at the same time.

Subsequently, in the electron mobility compensation period CP, the second gate pulses Pb of the first gate signals WS1(1), WS1(2), WS1(3), and WS1(4) are Applied to the fourth pixel lines L#1, L#2, L#3, and L#4 according to a line sequential method, and the third gate signals EM(1), EM(2), and EM(3) ), EM(4)) are simultaneously applied at an off level to the first to fourth pixel lines L#1, L#2, L#3, and L#4.

Accordingly, during the electron mobility compensation period CP, the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4 receive the first gate signal. Pixel data is sequentially written in synchronization with the second gate pulse Pb of the fields WS1(1), WS1(2), WS1(3), and WS1(4). As a result, the electron mobility of the driving TFT (DT) is sequentially compensated in units of pixel lines. Pixels disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4 while pixel data is written in the line sequential manner in the electron mobility compensation period CP. Since (PIX) is disconnected from the high-potential pixel driving voltage EVDD, it does not emit light immediately after receiving pixel data and maintains a non-emission state.

Subsequently, during the light emission period DP, the third gate signals EM(1), EM(2), EM(3), and EM(4) are applied to the first to fourth pixel lines L#1 and L #2, L#3, and L#4) are simultaneously applied with an on level. The timing at which the third gate signals EM(1), EM(2), EM(3), and EM(4) rise to an on level is determined by the first to fourth pixel lines L#1, L#2, L#3, L#4) must be determined after all pixel data is written.

Accordingly, since the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4 are connected to the high-potential pixel driving voltage EVDD, they are simultaneously it will glow

FIG. 12 is a diagram showing another driving method for eliminating the emission period deviation between pixel lines.

The panel driving circuit of the present invention controls the source potential of the driving TFTs before simultaneously compensating for the threshold voltages of the driving TFTs for the pixel lines belonging to the same display block in order to eliminate the variation in emission period between the pixel lines belonging to the same display block. Initialize sequentially in pixel line units. In addition, pixel data is written in line-sequential manner in pixel lines belonging to the same display block to sequentially compensate the electron mobility of the driving TFT in units of pixel lines, and sequentially emit light in units of pixel lines from the OLED. This driving method differs from the driving method of FIG. 9 in that the initialization start sequence is differentiated according to the light emission start sequence according to pixel data writing. Initializing the source potential of the driving TFT means that the OLED does not emit light by lowering the source potential of the driving TFT to the operating point voltage of the OLED. After maintaining a non-emission state during the initialization period and the threshold voltage compensation period, the OLED starts to emit light immediately after pixel data is written in the electron mobility compensation period. Then, the OLED maintains the light emitting state until the source potential of the driving TFT is initialized. Therefore, if the order of initializing the source potentials of the driving TFTs is set to be the same as the writing order of pixel data, the emission periods between pixel lines belonging to the same display block can be made the same.

This will be described in detail with reference to FIGS. 6 and 12 .

The first to fourth pixel lines L#1, L#2, L#3, and L#4 including a plurality of pixels PIX of FIG. 6 are driven as shown in FIG. 12 . That is, the first to fourth pixel lines L#1, L#2, L#3, and L#4 belonging to the same display block have an initialization period AP1 to AP4 and a threshold voltage compensation period BP1 to BP4. , the electron mobility compensation period (CP1 to CP4), and the light emission period (DP1 to DP4) are driven in this order. The initialization periods AP1 to AP4 are different in the first to fourth pixel lines L#1, L#2, L#3, and L#4.

The first gate pulse (Pa) of the first gate signals (WS1(1), WS1(2), WS1(3), and WS1(4)) corresponds to the initialization period (AP1 to AP4) and the threshold voltage compensating period (BP1 to BP1). BP4) is simultaneously applied to the first to fourth pixel lines L#1, L#2, L#3, and L#4. The second gate signals WS2(1), WS2(2), WS2(3), and WS2(4) are applied to the first to fourth pixel lines L#1 and L# in the initialization period AP1 to AP4. 2, L#3, and L#4) are sequentially applied with an on level.

Accordingly, during the initialization period AP1 to AP4, the driving TFTs DT are provided in the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4. The source potential of is sequentially initialized lower than the operating point voltage of the OLED. In this case, the timing at which the OLED starts not to emit light is later than the pixel line with the early initialization timing in the pixel line with the late initialization timing.

And, during the threshold voltage compensating period BP1 to BP4, the driving TFT ( The threshold voltage of DT) is compensated at the same time.

Subsequently, in the electron mobility compensation period CP1 to CP4, the second gate pulse Pb of the first gate signals WS1(1), WS1(2), WS1(3), and WS1(4) It is applied to the first to fourth pixel lines (L#1, L#2, L#3, and L#4) according to a line sequential method.

Accordingly, during the electron mobility compensation period CP1 to CP4, the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4 are Pixel data is sequentially written in synchronization with the second gate pulse Pb of the gate signals WS1(1), WS1(2), WS1(3), and WS1(4). As a result, the electron mobility of the driving TFT (DT) is sequentially compensated in units of pixel lines.

In addition, the light emitting periods DP1 to DP4 are sequentially started in the first to fourth pixel lines L#1, L#2, L#3, and L#4 by pixel data written in a line sequential manner. do. The start timing of the light emitting periods DP1 to DP4 depends on the writing order of pixel data. The timing at which the OLED starts to emit light is later than the pixel line in which the pixel data writing timing is early in the pixel line with the late pixel data writing timing.

A pixel line with a relatively early write timing of pixel data has a relatively early initialization timing, whereas a pixel line with a relatively slow write timing of pixel data has a relatively late initialization timing. Accordingly, the period during which light emission of the OLED is maintained in all pixel lines belonging to the same display block is equal to each other.

13 and 14 are diagrams illustrating a driving method for minimizing visibility of a block boundary due to a variation in an emission period between pixel lines.

The panel driving circuit of the present invention controls the source potential of the driving TFTs before simultaneously compensating for the threshold voltages of the driving TFTs for the pixel lines belonging to the same display block in order to eliminate the variation in emission period between the pixel lines belonging to the same display block. It is initialized at the same time lower than the operating point voltage of OLED. In addition, after simultaneously compensating for the threshold voltage of the driving TFT for pixel lines belonging to the same display block, pixel data is written in a line non-sequential manner to compensate for the electron mobility of the driving TFT in a non-sequential manner in units of pixel lines. The OLED emits light in a non-sequential manner in units of pixel lines.

This will be described in detail with reference to FIGS. 6, 13 and 14. In FIG. 13, symbols 1 to 4 indicate the order of writing pixel data to pixel lines L#1 to L#4 or L#5 to L#8 belonging to the same display block BLK1 or BLK2. FIG. 14 shows driving waveforms of pixel lines L#1 to L#4 belonging to the first display block BLK1 of FIG. 13 . The second display block BLK2 of FIG. 13 is driven in the same way as in FIG. 14 .

The first to fourth pixel lines L#1, L#2, L#3, and L#4 each including a plurality of pixels PIX of FIG. 6 are driven as shown in FIGS. 13 and 14 . That is, the first to fourth pixel lines L#1, L#2, L#3, and L#4 belonging to the same display block have an initialization period AP, a threshold voltage compensation period BP, and electron mobility. It is driven in order of the compensation period (CP1 to CP4) and the light emission period (DP1 to DP4).

The first gate pulse (Pa) of the first gate signals (WS1(1), WS1(2), WS1(3), and WS1(4) is the first gate pulse (Pa) in the initialization period (AP) and the threshold voltage compensating period (BP). It is simultaneously applied to the first to fourth pixel lines L#1, L#2, L#3, and L#4. The second gate signals WS2(1), WS2(2), WS2(3), and WS2(4) are applied to the first to fourth pixel lines L#1, L#2, and L#2 in the initialization period AP. L#3 and L#4) are simultaneously applied with an on level. Also, the third gate signals EM(1), EM(2), EM(3), and EM(4) are applied to the first to fourth pixel lines in the initialization period AP and the threshold voltage compensating period BP. The ON level is simultaneously applied to the L#1, L#2, L#3, and L#4.

Accordingly, during the initialization period AP, the source of the driving TFT DT in the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4. The potential is initialized at the same time lower than the operating point voltage of the OLED. And, during the threshold voltage compensating period BP, the driving TFTs DT in the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4. The threshold voltage of is compensated at the same time.

Subsequently, in the electron mobility compensation period CP1 to CP4, the second gate pulse Pb of the first gate signals WS1(1), WS1(2), WS1(3), and WS1(4) It is applied to the first to fourth pixel lines (L#1, L#2, L#3, and L#4) according to a line non-sequential method (①③④②).

Accordingly, during the electron mobility compensation period CP1 to CP4, the pixels PIX disposed on the first to fourth pixel lines L#1, L#2, L#3, and L#4 are Pixel data is sequentially written in synchronization with the second gate pulse Pb of the gate signals WS1(1), WS1(2), WS1(3), and WS1(4). In other words, pixel data is written to the first pixel line L#1, then pixel data is written to the second pixel line L#2, and then pixel data is written to the third pixel line L#3. Then, pixel data is written to the fourth pixel line (L#4). As a result, the electron mobility of the driving TFT (DT) is non-sequentially compensated in units of pixel lines.

Further, the light emitting periods DP1 to DP4 are sequentially generated in the first to fourth pixel lines L#1, L#2, L#3, and L#4 by pixel data written in a line non-sequential manner. It begins. The start timing of the light emitting periods DP1 to DP4 depends on the writing order of pixel data. The timing at which the OLED starts to emit light is later than the pixel line in which the pixel data writing timing is early in the pixel line with the late pixel data writing timing.

When pixel data is written in a line non-sequential manner in this way, as shown in FIG. 13 , the fourth pixel line L#4 belonging to the first display block BLK1 and the fifth pixel line belonging to the second display block BLK2 ( The emission period deviation between L#5), that is, the luminance deviation is reduced compared to the line sequential method. Specifically, the light emission period DP2 of the fourth pixel line L#4 is the second longest in the first display block BLK1. Also, the fifth pixel line L#5 has the longest emission period in the second display block BLK2. Accordingly, the emission period deviation between the fourth pixel line L#4 and the fifth pixel line L#5 disposed at the boundary between the first and second display blocks BLK1 and BLK2 can be minimized.

According to the driving method of the present invention, the luminance deviation at the boundary between adjacent display blocks is minimized by changing the order of writing pixel data in each of the display blocks. In this driving scheme, a pixel block line that emits light most recently in a first display block (that is, pixel data is written last) and a pixel block line that emits light most quickly in a second display block adjacent to the first display block (that is, that pixel data is written most quickly) This is to change the order of writing pixel data so that pixel block lines (in which pixel data are written) are not adjacent to each other. Accordingly, at least one pixel block line is disposed between a pixel block line that emits light most slowly in the first display block and a pixel block line that emits light most rapidly in the second display block.

15A and 16B are diagrams showing other driving schemes for minimizing block boundary visibility due to emission period deviation between pixel lines.

The panel driving circuit of the present invention drives signal lines of a display panel, simultaneously compensates threshold voltages of driving TFTs for pixel lines belonging to the same display block, and then writes pixel data to display electron mobility of driving TFTs as lines. compensate in a sequential manner. When pixel data is written in a line-sequential manner in this way, a block boundary line may be visually recognized due to a light emission period deviation between pixel lines. In order to minimize the visibility of block boundaries, the panel driving circuit according to the present invention drives the signal lines of the display panel to change the position of each display block on the display panel without fixing it temporally. In the case of FIGS. 10 to 14 , the position of the display block is temporally fixed, whereas in the driving method of FIGS. 15A to 16B , the position of the display block is temporally changed.

When the number of pixel lines belonging to the same display block is J (J is a positive integer greater than or equal to 2), the panel driving circuit of the present invention moves the position of each display block on the display panel at predetermined times K (K is a positive integer smaller than J). By shifting the pixel lines by an integer) number of pixel lines, it is possible to spatially disperse the block boundary line having a large luminance deviation so that it is less noticeable to the user.

For example, as shown in FIGS. 15A and 16B , the panel driving circuit of the present invention may shift the position of each display block by one pixel line in a cycle of one frame period. Specifically, in the Nth frame, pixel lines L#1 to L#3 are driven as first display blocks BLK1, and pixel lines L#4 to L#6 are driven as second display blocks BLK2. The pixel lines L#7 to L#9 are driven as the third display block BLK3, and the pixel lines L#10 to L#12 are driven as the fourth display block BLK4. Subsequently, in the N+1th frame, pixel lines L#2 to L#4 are driven as first display blocks BLK1, and pixel lines L#5 to L#7 are driven as second display blocks BLK2. The pixel lines L#8 to L#10 are driven as the third display block BLK3, and the pixel lines L#11 to L#13 are driven as the fourth display block BLK4.

As described above, the present invention divides and drives the pixel lines on which pixels are arranged in units of display blocks, and simultaneously compensates the threshold voltages of the driving elements for the pixel lines belonging to the same display block, thereby compensating the threshold voltage of the driving elements. By securing sufficient time, compensation performance can be improved.

Furthermore, in the present invention, in the same display block, after sequentially compensating for the electron mobility of driving elements on a per-pixel line basis, pixels disposed on the pixel lines are simultaneously connected to a high-potential pixel driving voltage and the light emitting elements emit light at the same time. , it is possible to eliminate a light emission period deviation between pixel lines according to pixel data written in a line sequential manner.

Furthermore, the present invention sequentially initializes the source potential of the driving element lower than the operating point voltage of the light emitting element in pixel line units before simultaneously compensating for the threshold voltage of the driving element within the same display block, and converts pixel data into a line sequential method. , and the light emitting element sequentially emits light in pixel line units, it is possible to eliminate a light emitting period deviation between pixel lines according to pixel data written in a line sequential manner.

Furthermore, the present invention simultaneously initializes the source potential of the driving element to be lower than the operating point voltage of the light emitting element before simultaneously compensating for the threshold voltage of the driving element within the same display block, and writes pixel data in a line non-sequential manner to emit light. By non-sequentially emitting light in units of pixel lines, a luminance deviation at a boundary between adjacent display blocks is minimized.

Furthermore, in the present invention, when the number of pixel lines belonging to the same display block is J (J is a positive integer greater than or equal to 2), the position of each display block on the display panel is determined by K (K is a positive integer smaller than J). By shifting the pixel lines by two pixel lines, it is possible to spatially disperse the block boundary line having a large luminance variance so that it is less noticeable to the user.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit

Claims (20)

a display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels; and
driving the signal lines of the display panel to simultaneously initialize the source potential of the driving element to be lower than the operating point voltage of the light emitting element during an initialization period targeting a first pixel line and a second pixel line belonging to the same display block; Then, during the threshold voltage compensation period, the threshold voltage of the driving element is simultaneously compensated, and then, during the electron mobility compensation period, pixel data is written to sequentially compensate the electron mobility of the driving element in pixel line units, and then light emission. A panel driving circuit for simultaneously emitting light from the light emitting elements during a period of time;
In the first pixel of the first pixel line and the second pixel of the second pixel line,
The electroluminescent display device of claim 1 , wherein a switch element connecting the driving element and a high-potential pixel driving voltage is simultaneously turned off during the electron mobility compensation period, and the switch element is simultaneously turned on during the emission period. delete delete a display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels; and
a panel driving circuit for driving signal lines of the display panel;
The panel driving circuit,
Targeting a first pixel line and a second pixel line belonging to the same display block,
In the initialization period, the source potential of the driving element is sequentially initialized in units of pixel lines lower than the operating point voltage of the light emitting element, and then the threshold voltage of the driving element is simultaneously compensated during a threshold voltage compensation period, followed by electron mobility compensation. During a period, pixel data is written in a line-sequential manner to sequentially compensate the electron mobility of the driving element in units of the pixel lines, and then sequentially emit light in units of the pixel lines during an emission period by the light emitting elements;
In the first pixel line and the second pixel line,
The electroluminescent display device having different lengths of the initialization period. According to claim 4,
The first start timing of the initialization period for the first pixel line is earlier than the second start timing of the initialization period for the second pixel line;
The order of initialization of the source potential of the driving element is earlier in the first pixel line than in the second pixel line. a display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels; and
a panel driving circuit for driving signal lines of the display panel;
The panel driving circuit,
Targeting pixel lines belonging to the same display block,
Simultaneously initializing the source potential of the driving element to be lower than the operating point voltage of the light emitting element before simultaneously compensating for the threshold voltage of the driving element;
After simultaneously compensating for the threshold voltages of the driving elements, pixel data is written in a line non-sequential manner to compensate for the electron mobility of the driving elements in a non-sequential manner in units of pixel lines, and in addition to compensating for the light emitting elements in units of pixel lines. An electroluminescent display device that emits light in a non-sequential manner. According to claim 6,
When the display panel includes a first display block and a second display block adjacent to each other, and the second display block is driven following the first display block,
and at least one pixel block line is disposed between a pixel block line that emits light most slowly in the first display block and a pixel block line that emits light most quickly in the second display block. The method of any one of claims 1 and 4 to 7,
The panel driving circuit,
An electroluminescent display device for driving signal lines of the display panel to temporally fix the position of each display block on the display panel. a display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, and a driving element and a light emitting element in each of the pixels; and
Signal lines of the display panel are driven to simultaneously initialize the source potential of the driving element to be lower than the operating point voltage of the light emitting element, targeting pixel lines belonging to the same display block, and then simultaneously setting the threshold voltage of the driving element After compensation, a panel driving circuit for sequentially compensating the electron mobility of the driving element in a pixel line unit by writing pixel data in a line sequential manner;
The panel driving circuit,
An electroluminescent display device that temporally changes a position of each display block on the display panel by driving signal lines of the display panel. According to claim 9,
When the number of pixel lines belonging to the same display block is J (J is a positive integer greater than or equal to 2),
The panel driving circuit,
The electroluminescent display device shifts the position of each display block on the display panel by K (K is a positive integer smaller than J) pixel lines by driving signal lines of the display panel. delete delete delete delete delete delete delete delete delete delete

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