KR20190008680A - Electroluminescent Display Device And Driving Method Of The Same - Google Patents

Abstract

According to the present invention, an electroluminescent display device capable of increasing compensation performance comprises: a display panel having a plurality of pixel lines driven in a display block unit, having a plurality of pixels in each pixel line, and having driving elements and light emitting elements in each of the pixels; and a panel driving circuit driving signal lines of the display panel and compensating for electron mobility of the driving elements by simultaneously writing pixel data after compensating threshold voltages of the driving elements for the pixel lines belonging to the same display block.

Description

[0001] The present invention relates to an electroluminescent display device and a driving method thereof,

The present invention relates to an electroluminescence display and a driving method thereof.

An electroluminescent display device is classified into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. Among them, an active matrix type organic light emitting display device includes an organic light emitting diode (OLED), which is a typical electroluminescent diode that emits light by itself, And high luminous efficiency, brightness, and viewing angle.

The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form and adjusts the brightness of an image implemented in the pixels according to the gradation of the image data. The driving TFT controls a driving current to be input to the OLED in accordance with a voltage (hereinafter referred to as " gate-source potential ") applied between the gate electrode and the source electrode of the driving TFT. The light emission amount and luminance of the OLED are determined according to the driving current.

In general, when the driving TFT operates in the saturation region, the driving current Ids flowing between the drain and the source of the driving TFT is expressed as follows.

Ids = 1/2 * (μ * C * W / L) * (Vgs-Vth) ²

Here, μ represents the electron mobility, C represents the capacitance of the gate insulating film, W represents the channel width of the driving TFT, and L represents the channel length of the driving TFT. Vgs represents the gate-source potential of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT.

The electrical characteristics of the pixel, such as the threshold voltage (Vth) of the driving TFT, the electron mobility (μ) of the driving TFT, etc., must be the same in all pixels since they are factors that determine the driving current (Ids). However, the electrical characteristics of the pixels change due to various causes such as a process variation and an aging change, so that the luminance between pixels can be varied even if the same data voltage is applied. Such a luminance deviation leads to deterioration of image quality and life span of the display device.

Internal compensation techniques are known to compensate for luminance variations between pixels. The internal compensation technique is to appropriately apply the gate signal and the data signal so as to compensate for the change in the threshold voltage (Vth) and the electron mobility (μ) of the driving TFT during real time driving, Is a voltage programming technique that sets the voltage to be applied.

In the display panel, there are pixel lines as many as the vertical resolution. In each pixel line, a plurality of pixels neighboring each other along the horizontal direction are arranged. The voltage programming for the internal compensation scheme sequentially proceeds by one pixel line within one frame period. Therefore, the pixel lines each require a time of one horizontal period (1H) for the voltage programming. One horizontal period (1H) is a time obtained by dividing one frame period by a vertical resolution. The pixels of each pixel line do not emit light while the voltage programming is proceeding and emit after the voltage programming is completed. In other words, the voltage-programmed pixel line emits light for a time period corresponding to the remaining period of one frame period, i.e., (vertical resolution-1) horizontal periods, to display an image.

One horizontal period (1H) depends on the frame frequency defining one frame period and the vertical resolution. 1 horizontal period (1H) becomes shorter as the frame frequency increases when the vertical resolution is the same (high-speed driving model). 1 The horizontal period (1H) becomes shorter as the vertical resolution increases when the frame frequency is the same (high resolution model). 1 The horizontal period (1H) becomes shorter as both the vertical resolution and the frame frequency increase (high-speed driving & high-resolution models).

If one horizontal period (1H) is too short, the time for the voltage programming is insufficient, so that the change of the threshold voltage (Vth) and the change of the electron mobility (μ) of the driving TFT can not be compensated appropriately. There is a need for a scheme capable of increasing compensation performance.

Therefore, an object of the present invention is to provide an electroluminescent display device and a driving method thereof, which can sufficiently compensate a driving time of pixels by driving pixels in a display block unit when compensating an electric characteristic deviation of pixels with an internal compensation scheme, .

According to an aspect of the present invention, there is provided an electroluminescent display device including a plurality of pixel lines driven in units of display blocks, a plurality of pixels arranged in each pixel line, A display panel having a display panel; And a panel driving circuit for driving the signal lines of the display panel to compensate the electron mobility of the driving device by simultaneously writing pixel data after compensating the threshold voltage of the driving device for pixel lines belonging to the same display block, .

There is provided a method of driving an electroluminescent display device in which a plurality of pixel lines are provided in a display panel and a plurality of pixels including driving elements and light emitting elements are arranged in each pixel line, Driving pixel lines on a display block basis; And compensating the electron mobility of the driving device by driving the signal lines of the display panel to write pixel data after simultaneously compensating the threshold voltage of the driving device for pixel lines belonging to the same display block .

According to the present invention, pixel lines in which pixels are arranged are divided and driven in units of a display block, pixel lines belonging to the same display block are simultaneously compensated for the threshold voltages of the driving elements, The compensation performance can be enhanced.

Further, in the present invention, in the same display block, after sequentially compensating the electron mobility of the driving element in units of pixel lines, the pixels arranged in the pixel lines are concurrently connected to the high-potential pixel driving voltage so as to emit light simultaneously , It is possible to eliminate the deviation of the light emission period between the pixel lines according to the pixel data written in the line sequential manner.

Further, in the present invention, in the same display block, before the threshold voltage of the driving element is simultaneously compensated, the source potential of the driving element is sequentially lowered to be lower than the operating point voltage of the light emitting element in units of pixel lines, And sequentially emit light emitting elements in units of pixel lines, it is possible to eliminate the deviation of the light emitting period between the pixel lines according to the pixel data written in the line sequential manner.

Further, in the present invention, in the same display block, before the threshold voltage of the driving element is simultaneously compensated, the source potential of the driving element is simultaneously initialized to be lower than the operating point voltage of the light emitting element, and pixel data is written in a line non- By causing the elements to emit light in a non-sequential manner on a pixel-by-pixel line basis, the luminance deviation at the boundary between neighboring display blocks is minimized.

Further, according to the present invention, when the number of pixel lines belonging to the same display block is J (J is a positive integer of 2 or more), the position of each display block on the display panel is set to K (K is a positive integer smaller than J) By shifting the pixel line by pixel line, it is possible to disperse the block boundary line having a large luminance deviation spatially so as not to be conspicuous to the user's eyes.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
2 is a view showing a pixel array formed on the display panel of Fig.
FIGS. 3 to 5 are views illustrating a method of driving a block for driving pixels on a display block basis according to an embodiment of the present invention.
6 is a diagram showing one equivalent circuit of a pixel for implementing the block driving method of the present invention.
FIG. 7 is a graph showing a drive waveform for driving the pixels as shown in FIG. 6 on a display block basis and a potential change of a drive TFT included in a specific pixel.
8A to 8D are diagrams sequentially showing the operation states of the specific pixels.
9 is a diagram showing that the light emission period varies between pixel lines within the same display block.
10 is a diagram showing a driving method for eliminating a light emission period deviation between pixel lines.
11 is a diagram showing one equivalent circuit of a pixel for implementing the driving method of FIG.
12 is a view showing another driving method for eliminating a light emission period deviation between pixel lines.
FIGS. 13 and 14 are views showing a driving method for minimizing block boundary line visibility due to a light emission period deviation between pixel lines. FIG.
FIGS. 15A and 16B are diagrams showing another driving method for minimizing block boundary line visibility due to a light emission period deviation between pixel lines. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that the features of the various embodiments of the invention may be combined or combinable, either partially or entirely, and technically various interlocking and driving are possible, and that the embodiments may be practiced independently of each other, have.

In the present invention, the pixel circuit formed on the substrate of the display panel may be realized by a TFT of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers begin to flow from the source. The drain is an electrode in which the carrier exits from the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since the electrons flow from the source to the drain in the n type TFT, the direction of the current flows from the drain to the source side. In the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage.

In the following, the gate on voltage is the voltage of the gate signal that the TFT can turn on. The gate off voltage is a voltage at which the TFT can be turned off. In the NMOS, the gate-on voltage is the gate high voltage and the gate-off voltage is the gate low voltage. In the PMOS, the gate-on voltage is the gate-low voltage and the gate-off voltage is the gate-high voltage.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, an electroluminescent display device will be described mainly with respect to an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to the organic light emitting display, but can be applied to an inorganic light emitting display device including an inorganic light emitting material.

FIG. 1 shows an organic light emitting display according to an embodiment of the present invention, and FIG. 2 shows a pixel array formed on the display panel of FIG.

Referring to FIGS. 1 and 2, an organic light emitting diode display according to an embodiment of the present invention includes a display panel 10, a panel driving circuit, and a timing controller 11.

A plurality of data lines 14 and a plurality of gate lines 15 are intersected with each other in the display panel 10 and pixels PIX are arranged in a matrix form in each of the intersection regions. Each of the pixels PIX includes a light emitting element (hereinafter, referred to as OLED) and a driving element (hereinafter, driving TFT) and compensates for the threshold voltage and electron mobility of the driving TFT according to the source follower internal compensation method, The gate-source voltage of the set driving TFT is maintained for approximately one frame period to display the desired gray level.

The pixel PIX of the present invention may have a structure in which a source-follower internal compensation scheme can be applied. Each pixel PIX may be provided with switch TFTs for controlling the gate-source potential of the driving TFT. Each pixel PIX may further include a switch TFT for controlling the emission timing of the OLED. The switch TFTs of each pixel PIX are switched by the gate signal applied from the gate lines 15. [ Each pixel PIX may be connected to two or three gate lines 15 according to its circuit configuration. Although FIG. 2 shows a single gate line 15 connected to each pixel PIX for convenience of description, it should be noted that at least two gate lines 15 may be connected to each pixel PIX. Each pixel PIX can receive a high-potential pixel drive voltage EVDD and a low-potential pixel drive voltage EVSS from a power generating unit (not shown).

In the display panel 10, a pixel array as shown in Fig. 2 is formed by the pixels PIX arranged in a matrix form. The pixel array is divided into a plurality of display blocks BLK1 to BLKj along a data line extending direction (e.g., a vertical direction), and each display block includes a plurality of pixel lines L # 1 to L # n . Here, each pixel line means a set of pixels PIX that are arranged adjacent to each other along a gate line extending direction (e.g., a horizontal direction) and simultaneously write pixel data. The threshold voltage compensation timings of the driving TFTs are set such that the pixel lines L # 1 to L # n included in the same display block are subjected to the threshold voltage compensation timing of the driving TFTs belonging to the pixels PIX It can be done at the same time.

The panel drive circuit drives the signal lines 14 and 15 of the display panel 10 under the control of the timing controller 11 to drive the pixel lines L # 1 to L # n belonging to the same display block , The threshold voltage of the driving TFT is simultaneously compensated, and then the electron mobility of the driving TFT is compensated. Thus, the threshold voltage compensation time is sufficiently secured within one frame period to improve the compensation performance. As the number of the pixel lines L # 1 to L # n belonging to the same display block is increased, the threshold voltage compensation performance in the resolution display block is improved. However, Due to the period deviation, the boundary line between adjacent display blocks can be viewed. Therefore, the number of the pixel lines L # 1 to L # n belonging to the same display block can be set appropriately in consideration of the threshold voltage compensation performance and the degree of visibility of the boundary line between the display blocks.

FIGS. 3 to 5 are views illustrating a method of driving a block for driving pixels on a display block basis according to an embodiment of the present invention.

3 to 5, the panel driving circuit of the present invention divides the display panel 10 into display blocks BLK1 to BLKj (S1). In other words, the panel driving circuit drives the signal lines 14 and 15 of the display panel 10 in units of display blocks BLK1 to BLKj each including the pixel lines L # 1 to L # n (S1).

The panel driving circuit sequentially compensates the threshold voltage and the electron mobility of the driving TFT in units of display blocks, and simultaneously applies the threshold voltages of the driving TFTs to the pixel lines L # 1 to L # n belonging to the same display block simultaneously After compensation, the electron mobility of the driving TFT in the same display block is compensated in units of pixel lines (S2, S3).

Specifically, the panel driving circuit simultaneously compensates the threshold voltage of the driving TFT with respect to the pixel lines L # 1 to L # n of the first display block BLK1, The electron mobility of the driving TFT is compensated in units of pixel lines. Subsequently, the panel driving circuit simultaneously compensates the threshold voltage of the driving TFT with respect to the pixel lines L # 1 to L # n of the second display block BLK2, and then, in this second display block BLK2, The electron mobility of the driving TFT is compensated in units of lines. In this way, the panel driving circuit compensates the threshold voltage and the electron mobility of the driving TFT up to the jth display block BLKj.

Then, the panel driving circuit holds the gate-source voltage of the driving TFT set in step S3 in the corresponding pixel PIX, applies driving current to the OLED of each pixel PIX, emits the OLED, (S4).

On the other hand, the gate signal in Fig. 6 corresponds to the first gate signal for controlling the gate potential of the driving TFT. It should be noted that the second gate signal for controlling the source potential of the driving TFT is not shown in FIG. 6 for the sake of convenience.

In each display block in Fig. 6, a period during which the threshold voltage of the driving TFT is simultaneously compensated is denoted by " D1 ", and a period until the first pixel data is written after the threshold voltage compensation is denoted by " D2 ". D2 indicates a holding period during which the gate-source potential of the driving TFT is maintained.

6 is a diagram showing one equivalent circuit of a pixel for implementing the block driving method of the present invention.

Referring to FIG. 6, the pixel PIX of the present invention may include an OLED, a driving TFT DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2.

The OLED includes an anode electrode connected to the source node N2, a cathode electrode connected to the low-potential pixel driving voltage end (EVSS), and an organic compound layer positioned between the anode electrode and the cathode electrode.

The driving TFT DT controls the driving current Ioled applied to the OLED according to the gate-source potential Vgs. The driving TFT DT has a gate connected to the gate node N1, a drain to which the high-potential pixel driving voltage EVDD is applied, and a source connected to the source node N2.

The storage capacitor Cst is connected between the gate node N1 and the source node N2.

The first switch TFT (ST1) is switched in accordance with the first gate signal (WS1) to control the gate potential of the drive TFT (DT). The first switch TFT ST1 has a gate connected to the first gate line 15A, a drain connected to the data line 14, and a source connected to the gate node N1. The first gate signal WS1 includes a first gate pulse synchronized with the offset voltage Vofs and a second gate pulse synchronized with the data voltage Vdata.

The second switch TFT (ST2) is switched in accordance with the second gate signal (WS2) to control the source potential of the drive TFT (DT). The gate of the second switch TFT ST2 is connected to the second gate line 15B and the drain of the second switch TFT ST2 is connected to the source node N2 and the source of the second switch TFT ST2 is connected to the source The initializing voltage Vinit is applied. Here, the initialization voltage Vinit is used to initialize the source potential of the driving TFT DT to be lower than the operating point voltage of the OLED.

FIG. 7 is a diagram showing a driving waveform for driving the pixels as shown in FIG. 6 on a display block basis and a potential change of a driving TFT included in a specific pixel. 8A to 8D are diagrams sequentially showing the operation states of the specific pixels.

Referring to FIG. 7, driving signals for neighboring i-th display block BLKi and j-th display block BLKj are shown. the first gate signals WS1 i (n-2), WS1 i (n-1) and WS1 i (n) are applied to the first gate pulse Pa, And the second gate pulse Pb to the first gate line 15A of the three pixel lines L # n-2, L # n-1 and L # n, N-2, L # n-1 (n-1) and WS2 (n-1) , L # n). The first gate pulse Pa of the first gate signals WS1 i (n-2), WS1 i (n-1), and WS1 i (n) are simultaneously applied to each other and the second gate signals WS2 i (n-2), WS2 i (n-1) and WS2 i (n) are simultaneously applied to each other. On the other hand, the second gate pulse Pb of the first gate signals WS1 i (n-2), WS1 i (n-1), and WS1 i (n) is sequentially applied in accordance with the line sequential method.

In this case, the data line 14 is supplied with the offset voltage V1 corresponding to the first pulses P1 of the first gate signals WS1 i (n-2), WS1 i (n-1), WS1 i And sequentially applies the second pulses P2 of the first gate signals WS1 i (n-2), WS1 i (n-1) and WS1 i (n) 14), the gradation voltage Vdata for image display is applied.

Referring to Figs. 8A to 8D together with Fig. 7, the operation states of the pixel PIX of Fig. 6 included in the n-th pixel line L # n of the i-th display block BLKi will be sequentially described. same.

The pixel PIX in Fig. 6 is driven in the order of an initialization period TP1, a threshold voltage compensation period TP2, an electron mobility compensation period TP3, and a light emission period TP4 as shown in Fig.

The first switch TFT ST1 is turned on in response to the first gate pulse Pa of the first gate signal WS1 to set the offset voltage Vofs to the gate node N1 in the initialization period TP1 of FIG. And the second switch TFT ST2 turns on according to the second gate signal WS2 to apply the initialization voltage Vinit to the source node N2. Here, the offset voltage Vofs is set higher than the threshold voltage in comparison with the initialization voltage Vinit. Therefore, the gate-source potential of the driving TFT DT becomes higher than the threshold voltage, so that the driving TFT DT is turned on, and the OLED is not emitted.

Then, the gate potential VN1 of the driving TFT DT is held at the offset voltage Vofs by the first switch TFT ST1, which is kept turned on during the threshold voltage compensation period TP2 of Fig. 10B. At this time, the second switch TFT (ST2) is turned off in accordance with the second gate signal WS2, and as a result, the source potential VN2 of the drive TFT DT becomes equal to the current Ids gradually increase from the initialization voltage Vinit. At this time, the source potential VN2 of the driving TFT DT rises until the gate-source voltage Vgs of the driving TFT DT becomes the threshold voltage Vth. The threshold voltage Vth of the sampled driving TFT DT is compensated by being stored in the storage capacitor Cst. The time taken until the gate-source voltage Vgs of the driving TFT DT becomes equal to the threshold voltage Vth is long. According to the present invention, the threshold voltage compensation period TP2 can be sufficiently secured within one frame period through simultaneous compensation for each block, so that the accuracy of compensation for the threshold voltage can be increased.

Subsequently, in the electron mobility compensation period TP3 of FIG. 8C, the first switch TFT ST1 is turned on according to the second gate pulse Pb of the first gate signal WS1 after a predetermined holding period The image display gradation voltage Vdata is applied to the gate node N1 to raise the gate potential VN1 of the driving TFT DT. Then, the source potential VN2 of the driving TFT DT also rises in accordance with the electron mobility characteristic of the driving TFT DT. Eventually, the gradation voltage Vdata for image display and the threshold voltage Vth are applied to the storage capacitor Cst, (Vdata + Vth-? V?) Obtained by subtracting the voltage change amount (? Vm) according to the electron mobility characteristic from the sum of the voltages The voltage (Vdata + Vth-? V?) Stored in the storage capacitor Cst becomes the gate-source voltage Vgs compensated for the electron mobility of the driving TFT DT. This gate-source voltage Vgs is set in inverse proportion to the electron mobility of the drive TFT DT. In other words, if the electron mobility of the driving TFT DT is large, the gate-source voltage (Vdata + Vth-Vm) becomes small. On the contrary, if the electron mobility of the driving TFT DT is small, Vdata + Vth-? V?) Becomes larger. Whereby the electron mobility of the driving TFT DT is compensated.

Subsequently, both the first switch TFT (ST1) and the second switch TFT (ST2) are turned off in the light emission period TP4 of Fig. 8D, and the drive TFT DT is turned off during the electron mobility compensation period TP3 (Vdata + Vth-? V?) Stored in the memory cell (Cst) to apply the driving current Ioled compensated for the threshold voltage (Vth) and the electron mobility (μ) to the OLED. The OLED receives a driving current (Ioled) proportional to (Vdata - Vv) ² . At this time, since the source potential of the driving TFT DT becomes higher than the operating point voltage of the OLED, the OLED emits light by the driving current Ioled.

9 is a diagram showing that the light emission period varies between pixel lines within the same display block.

9, for each pixel line, the holding periods FP1 to FP4 exist after the threshold voltage Vth of the driving TFT DT is compensated until the electron mobility of the driving TFT DT is compensated . Both the gate node N1 and the source node N2 of the driving TFT DT are held in the floating state during the holding periods FP1 to FP4.

After the threshold voltages of the driving TFT DT are simultaneously compensated for the pixel lines belonging to the same display block as described above, the electron mobility of the driving TFT DT in the same display block is sequentially In the case of compensation, the light emitting period is changed due to the difference of the holding period between the pixel lines in the same display block.

In FIG. 9, the holding period (FP1 to FP4) for the pixel line in which the pixel data writing is delayed with respect to the four pixel lines L # n-3, L # n-2, L # n- While the light emission periods EP1 to EP4 are shortened. The first gate signals WS1 i (n-3), WS1 i (n-2), WS1 i (n-1) and WS1 i (n) and the second gate signals WS2 i (n-3), WS2 i (n-2), WS2 i (n-1) and WS2 i (n) maintain a low level during the holding periods FP1 to FP4 of the corresponding pixel line. The holding periods FP1 to FP4 are the shortest in the pixel line L # n-3 having the fastest compensation sequence for the electron mobility of the driving TFT DT and compensated for the electron mobility of the driving TFT DT And the longest in the pixel line (L # n) in which the order is the latest. The light emission periods EP1 to EP4 are the longest in the pixel line L # n-3 having the fastest compensation sequence for the electron mobility of the drive TFT DT and the electron mobility of the drive TFT DT Is the shortest in the pixel line (L # n) where the compensation order is the latest.

In other words, in each display block, the light emission period is the shortest in the pixel line (i.e., the last pixel line) in which the pixel data writing is the longest in the pixel line with the fastest pixel line (i.e., the first pixel line) . When the same gradation is displayed, luminance increases as the emission period becomes longer, so that a luminance deviation may occur between the pixel lines. When sequentially writing the pixel data to the pixel lines (L # n-3, L # n-2, L # n-1 and L # n) in a line-sequential manner, The boundary between the display blocks can be viewed as a line dim. Therefore, a method of minimizing the line depth between display blocks while improving the accuracy of compensation is proposed below.

10 is a diagram showing a driving method for eliminating a light emission period deviation between pixel lines. 11 is a diagram showing one equivalent circuit of a pixel for implementing the driving scheme of FIG.

The panel driving circuit of the present invention sequentially writes the pixel data in the pixel lines belonging to the same display block in accordance with the line sequential method in order to eliminate the light emission period deviation between the pixel lines belonging to the same display block, So that the OLED is simultaneously emitted.

This will be described in detail with reference to FIGS. 10 and 11. FIG.

The pixel PIX in Fig. 11 differs from the pixel PIX in Fig. 6 in that it further includes the third switch TFT ST3, and the remaining configuration is the same as the pixel PIX in Fig. The third switch TFT (ST3) is switched in accordance with the third gate signal EM to control the drain potential of the drive TFT (DT). In other words, the third switch TFT ST3 is switched in accordance with the third gate signal EM applied from the third gate line 15C, so that the input terminal of the high-potential pixel drive voltage EVDD and the gate of the drive TFT DT And controls the electrical connection between the drains. The gate of the third switch TFT (ST3) is connected to the third gate line 15C, the drain of the third switch TFT (ST3) is connected to the input terminal of the high potential pixel drive voltage EVDD, and the gate of the third switch TFT ST3 are connected to the drain of the driving TFT DT.

The first through fourth pixel lines L # 1, L # 2, L # 3 and L # 4 including a plurality of pixels PIX in FIG. 11 are driven as shown in FIG. That is, the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 belonging to the same display block are divided into the initialization period AP, the threshold voltage compensation period BP, The compensation period CP, and the light emission period DP.

The first gate pulse Pa of the first gate signals WS1 (1), WS1 (2), WS1 (3), WS1 4) 1 to the fourth pixel lines L # 1, L # 2, L # 3, and L # 4. The second gate signals WS2 (1), WS2 (2), WS2 (3) and WS2 (4) are applied to the first to fourth pixel lines L # 1, L # 2, L # 3, L # 4). The third gate signals EM (1), EM (2), EM (3), EM (4)) are applied to the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 at the same time.

Thus, during the initialization period AP, the source of the driving TFT DT at the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # The potential is initialized at the same time so as to be lower than the operating point voltage of the OLED. During the threshold voltage compensation period BP, the driving TFT DT is turned on in the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # Are simultaneously compensated.

Subsequently, in the electron mobility compensation period CP, the second gate pulse Pb of the first gate signals WS1 (1), WS1 (2), WS1 (3), WS1 (4) And the third gate signals EM (1), EM (2), EM (3), and L (3) are applied to the fourth pixel lines L # ) And EM 4 are simultaneously applied to the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 in off-level.

Accordingly, during the electron mobility compensation period CP, the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # The pixel data is sequentially written in synchronization with the second gate pulse Pb of the first gate pulse WS1 (1), WS1 (2), WS1 (3), WS1 (4) As a result, the electron mobility of the driving TFT DT is sequentially compensated in units of pixel lines. L # 3, and L # 4 disposed in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 while pixel data is written in a line sequential manner in the electron mobility compensation period CP (PIX) is disconnected from the high-potential pixel drive voltage (EVDD), the pixel data is not immediately emitted after the pixel data is written, and the non-emission state is maintained.

Next, during the light emission period DP, the third gate signals EM (1), EM (2), EM (3), EM (4) # 2, L # 3, L # 4). The timing at which the third gate signals EM (1), EM (2), EM (3), EM (4)) rise to the on level is the timing at which the first to fourth pixel lines L # L # 2, L # 3, L # 4).

Accordingly, since the pixels PIX arranged in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 are connected to the high potential pixel driving voltage EVDD, The light is emitted.

12 is a view showing another driving method for eliminating a light emission period deviation between pixel lines.

The panel driving circuit of the present invention is characterized in that before the threshold voltage of the driving TFT is simultaneously compensated for the pixel lines belonging to the same display block in order to eliminate the light emission period deviation between the pixel lines belonging to the same display block, Sequentially initialize in units of pixel lines. Then, the pixel data is sequentially written to the pixel lines belonging to the same display block in a line sequential manner to sequentially compensate the electron mobility of the driving TFT in units of pixel lines, and sequentially emit the OLEDs in units of pixel lines. This drive scheme differs from the drive scheme of FIG. 9 in that the initialization start order is differentiated according to the light emission start order according to pixel data writing. Initializing the source potential of the driving TFT means that the source potential of the driving TFT is lower than the operating point voltage of the OLED so that the OLED is not emitted. After the OLED maintains the non-emission state during the initialization period and the threshold voltage compensation period, the OLED starts emitting light immediately after the pixel data is written in the electron mobility compensation period. Then, the OLED holds the light emission state until the source potential of the drive TFT is initialized. Therefore, if the order of initializing the source potential of the driving TFT is set to be the same as the writing order of the pixel data, the light emission periods between the pixel lines belonging to the same display block can be made equal.

This will be described in detail with reference to FIGS. 6 and 12. FIG.

The first through fourth pixel lines L # 1, L # 2, L # 3, and L # 4 including a plurality of pixels PIX in FIG. 6 are driven as shown in FIG. Namely, the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 belonging to the same display block are divided into the initializing periods AP1 to AP4, the threshold voltage compensating periods BP1 to BP4, The electron mobility compensation periods CP1 to CP4, and the light emission periods DP1 to DP4. The initialization periods AP1 to AP4 are different from each other in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4.

The first gate pulse Pa of the first gate signals WS1 (1), WS1 (2), WS1 3 and WS1 4 is supplied to the initializing periods AP1 to AP4 and the threshold voltage compensating periods BP1- L # 2, L # 3, and L # 4 in the first through fourth pixel lines BP1 through BP4. The second gate signals WS2 (1), WS2 (2), WS2 (3) and WS2 (4) are supplied to the first through fourth pixel lines L # 1 and L # 2, L # 3, L # 4).

Thus, during the initialization periods AP1 to AP4, the driving TFT DT is turned on in the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # The source potential of the OLED is sequentially lowered to be lower than the operating point voltage of the OLED. At this time, a pixel line whose initialization timing is late is delayed in timing when the OLED starts to emit no light as compared with a pixel line whose initialization timing is fast.

During the threshold voltage compensating periods BP1 to BP4, the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # DT are simultaneously compensated.

Subsequently, in the electron mobility compensation periods CP1 to CP4, the second gate pulse Pb of the first gate signals WS1 (1), WS1 (2), WS1 (3), WS1 (4) 1 to the fourth pixel lines L # 1, L # 2, L # 3, and L # 4 according to a line sequential method.

Accordingly, the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 during the mobility compensation periods CP1 to CP4 are connected to the first The pixel data is sequentially written in synchronization with the second gate pulse Pb of the gate signals WS1 (1), WS1 (2), WS1 (3), WS1 (4). As a result, the electron mobility of the driving TFT DT is sequentially compensated in units of pixel lines.

The light emission periods DP1 to DP4 are sequentially started from the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 by the pixel data written in the line sequential manner do. The start timing of the light emission periods DP1 to DP4 depends on the writing order of the pixel data. The timing of starting the emission of the OLED is slower than that of the pixel line in which the writing timing of the pixel data is late.

Pixel lines having relatively fast writing timing of pixel data have a relatively high initialization timing, while pixel lines having relatively slow writing timing of pixel data have relatively slow initialization timing. Therefore, the periods during which the emission of the OLEDs are maintained in all the pixel lines belonging to the same display block become equal to each other.

FIGS. 13 and 14 are views showing a driving method for minimizing block boundary line visibility due to a light emission period deviation between pixel lines. FIG.

The panel driving circuit of the present invention is characterized in that before the threshold voltage of the driving TFT is simultaneously compensated for the pixel lines belonging to the same display block in order to eliminate the light emission period deviation between the pixel lines belonging to the same display block, Initialize the OLED simultaneously at a lower voltage than the operating point voltage. Then, the pixel data belonging to the same display block are simultaneously compensated for the threshold voltage of the driving TFT, and then pixel data is written in a line nonsequential manner to compensate the electron mobility of the driving TFT in units of pixel lines in a nonsequential manner, Thereby emitting the OLEDs in a non-sequential manner on a pixel-by-pixel line basis.

This will be described in detail with reference to FIGS. 6, 13, and 14. FIG. In Fig. 13, (1) to (4) show a sequence of writing pixel data to pixel lines (L # 1 to L # 4, or L # 5 to L # 8) belonging to the same display block (BLK1 or BLK2). FIG. 14 shows drive waveforms of the pixel lines L # 1 to L # 4 belonging to the first display block BLK1 of FIG. The second display block BLK2 of Fig. 13 is also driven as in Fig.

The first through fourth pixel lines L # 1, L # 2, L # 3, and L # 4 including a plurality of pixels PIX in FIG. 6 are driven as shown in FIGS. That is, the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 belonging to the same display block are divided into the initialization period AP, the threshold voltage compensation period BP, The compensation periods CP1 to CP4, and the light emission periods DP1 to DP4.

The first gate pulse Pa of the first gate signals WS1 (1), WS1 (2), WS1 (3), WS1 4) 1 to the fourth pixel lines L # 1, L # 2, L # 3, and L # 4. The second gate signals WS2 (1), WS2 (2), WS2 (3) and WS2 (4) are applied to the first to fourth pixel lines L # 1, L # 2, L # 3, L # 4). The third gate signals EM (1), EM (2), EM (3), EM (4)) are applied to the first to fourth pixel lines L # 1, L # 2, L # 3, and L # 4 at the same time.

Thus, during the initialization period AP, the source of the driving TFT DT at the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # The potential is initialized at the same time so as to be lower than the operating point voltage of the OLED. During the threshold voltage compensation period BP, the driving TFT DT is turned on in the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3, and L # Are simultaneously compensated.

Subsequently, in the electron mobility compensation periods CP1 to CP4, the second gate pulse Pb of the first gate signals WS1 (1), WS1 (2), WS1 (3), WS1 (4) 1 to the fourth pixel lines L # 1, L # 2, L # 3, and L # 4 in accordance with a line nonsequential method.

Accordingly, the pixels PIX disposed in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 during the mobility compensation periods CP1 to CP4 are connected to the first The pixel data is sequentially written in synchronization with the second gate pulse Pb of the gate signals WS1 (1), WS1 (2), WS1 (3), WS1 (4). In other words, pixel data is written in the first pixel line L # 1, pixel data is written in the second pixel line L # 2, and then pixel data is written in the third pixel line L # And then pixel data is written in the fourth pixel line L # 4. As a result, the electron mobility of the driving TFT DT is compensated in a non-sequential manner in units of pixel lines.

Then, the light emission periods DP1 to DP4 in the first to fourth pixel lines L # 1, L # 2, L # 3 and L # 4 are sequentially It starts. The start timing of the light emission periods DP1 to DP4 depends on the writing order of the pixel data. The timing of starting the emission of the OLED is slower than that of the pixel line in which the writing timing of the pixel data is late.

In the case of writing the pixel data in the line nonsequential manner, as shown in FIG. 13, the fourth pixel line L # 4 belonging to the first display block BLK1 and the fifth pixel line belonging to the second display block BLK2 L # 5), that is, the luminance deviation is reduced as compared with the line sequential method. Specifically, the light emission period DP2 of the fourth pixel line L # 4 is the second longest in the first display block BLK1. The fifth pixel line L # 5 has the longest light emission period in the second display block BLK2. Therefore, the deviation of the light emission period between the fourth pixel line L # 4 and the fifth pixel line L # 5 disposed at the boundary between the first and second display blocks BLK1 and BLK2 can be minimized.

The driving method of the present invention minimizes the luminance deviation at the boundary between neighboring display blocks by changing the pixel data writing order in each of the display blocks. This driving method is a method in which the pixel block line that emits the latest light in the first display block (that is, the pixel data is written most late) and the pixel block line that emits light the fastest in the second display block neighboring the first display block Pixel data is written) so that the pixel block lines are not adjacent to each other. Accordingly, at least one or more pixel block lines are disposed between the pixel block line that emits the slowest light in the first display block and the pixel block line that emits the fastest light in the second display block.

FIGS. 15A and 16B are diagrams showing another driving method for minimizing block boundary line visibility due to a light emission period deviation between pixel lines. FIG.

The panel driving circuit of the present invention drives the signal lines of the display panel to simultaneously compensate the threshold voltage of the driving TFT with respect to the pixel lines belonging to the same display block and write the pixel data, And compensates in a sequential manner. When the pixel data is written in this line sequential manner, the block boundary can be visually recognized due to the light emission period deviation between the pixel lines. The panel driving circuit of the present invention can drive the signal lines of the display panel to minimize the visibility of block boundary lines without changing the position of each display block on the display panel in a temporal manner. 10 to 14, the positions of the display blocks are fixed in terms of time, whereas in the driving methods of Figs. 15A to 16B, the positions of the display blocks change in time.

When the number of pixel lines belonging to the same display block is J (J is a positive integer equal to or larger than 2), the panel driving circuit of the present invention sets the position of each display block on the display panel to K Integer) pixel lines, it is possible to spatially disperse block boundary lines having a large luminance deviation, thereby making them less conspicuous to the user's eyes.

For example, as shown in FIGS. 15A to 16B, the panel driving circuit of the present invention can shift the position of each display block by one pixel line at intervals of one frame period. Specifically, in the Nth frame, the pixel lines L # 1 to L # 3 are driven as the first display block BLK1 and the pixel lines L # 4 to L # 6 are driven as the second display block BLK2 , The pixel lines L # 7 to L # 9 are driven as the third display block BLK3, and the pixel lines L # 10 to L # 12 are driven as the fourth display block BLK4. Next, in the (N + 1) th frame, the pixel lines L # 2 to L # 4 are driven as the first display block BLK1 and the pixel lines L # 5 to L # 7 are driven as the second display block BLK2 The pixel lines L # 8 to L # 10 are driven as the third display block BLK3, and the pixel lines L # 11 to L # 13 are driven as the fourth display block BLK4.

As described above, according to the present invention, pixel lines in which pixels are arranged are divided and driven in units of display blocks, and pixel lines belonging to the same display block are simultaneously compensated for the threshold voltages of the driving elements, Sufficient time can be ensured to enhance the compensation performance.

Further, in the present invention, in the same display block, after sequentially compensating the electron mobility of the driving element in units of pixel lines, the pixels arranged in the pixel lines are concurrently connected to the high-potential pixel driving voltage so as to emit light simultaneously , It is possible to eliminate the deviation of the light emission period between the pixel lines according to the pixel data written in the line sequential manner.

Further, in the present invention, in the same display block, before the threshold voltage of the driving element is simultaneously compensated, the source potential of the driving element is sequentially lowered to be lower than the operating point voltage of the light emitting element in units of pixel lines, And sequentially emit light emitting elements in units of pixel lines, it is possible to eliminate the deviation of the light emitting period between the pixel lines according to the pixel data written in the line sequential manner.

Further, in the present invention, in the same display block, before the threshold voltage of the driving element is simultaneously compensated, the source potential of the driving element is simultaneously initialized to be lower than the operating point voltage of the light emitting element, and pixel data is written in a line non- By causing the elements to emit light in a non-sequential manner on a pixel-by-pixel line basis, the luminance deviation at the boundary between neighboring display blocks is minimized.

Further, according to the present invention, when the number of pixel lines belonging to the same display block is J (J is a positive integer of 2 or more), the position of each display block on the display panel is set to K (K is a positive integer smaller than J) By shifting the pixel line by pixel line, it is possible to disperse the block boundary line having a large luminance deviation spatially so as not to be conspicuous to the user's eyes.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit

Claims (20)

A display panel having a plurality of pixel lines driven in units of display blocks, a plurality of pixels in each pixel line, each of the pixels having a driving element and a light emitting element; And
A panel driving circuit for driving the signal lines of the display panel to compensate the electron mobility of the driving device by simultaneously writing pixel data after compensating the threshold voltage of the driving device for pixel lines belonging to the same display block, And an electroluminescent display device. The method according to claim 1,
In the panel driving circuit,
The pixel blocks belonging to the same display block,
The source potential of the driving element is simultaneously initialized to be lower than the operating point voltage of the light emitting element before simultaneously compensating the threshold voltage of the driving element,
And sequentially writes the pixel data in a line-sequential manner to sequentially compensate the electron mobility of the driving device in units of pixel lines. 3. The method of claim 2,
In the panel driving circuit,
The pixel blocks belonging to the same display block,
And sequentially connecting the pixels arranged in the pixel lines to a high-potential pixel driving voltage to simultaneously emit the light-emitting elements after sequentially compensating the electron mobility of the driving elements in units of the pixel lines. The method according to claim 1,
In the panel driving circuit,
The pixel blocks belonging to the same display block,
The source potential of the driving element is sequentially lowered to a voltage lower than the operating point voltage of the light emitting element in units of a pixel line before the threshold voltage of the driving element is simultaneously compensated,
And sequentially writes the pixel data in a line sequential manner to sequentially compensate the electron mobility of the driving elements in units of the pixel lines, and sequentially emit the light emitting elements in units of the pixel lines. 5. The method of claim 4,
Wherein the order in which the source potential of the driving element is initialized is the same as the writing order of the pixel data. The method according to claim 1,
In the panel driving circuit,
The pixel blocks belonging to the same display block,
The source potential of the driving element is simultaneously initialized to be lower than the operating point voltage of the light emitting element before simultaneously compensating the threshold voltage of the driving element,
Sequentially writes the pixel data in a line non-sequential manner to compensate for the electron mobility of the driving elements in a non-sequential manner on a pixel-by-pixel basis, and to sequentially discharge the light-emitting elements in units of the pixel lines. The method according to claim 6,
Wherein the display panel includes a first display block and a second display block which are adjacent to each other, and when the second display block is driven following the first display block,
Wherein at least one or more pixel block lines are disposed between a pixel block line that is the latest to emit light in the first display block and a pixel block line that emits the fastest light in the second display block. 8. The method according to any one of claims 1 to 7,
In the panel driving circuit,
And the signal lines of the display panel are driven to fix the position of each display block on the display panel in terms of time. 3. The method of claim 2,
In the panel driving circuit,
And driving the signal lines of the display panel to change positions of the respective display blocks on the display panel in a temporal manner. 10. The method of claim 9,
When the number of pixel lines belonging to the same display block is J (J is a positive integer of 2 or more)
In the panel driving circuit,
And driving the signal lines of the display panel to shift the positions of the respective display blocks on the display panel by K (K is a positive integer less than J) pixel lines every predetermined time. A method of driving an electroluminescent display device in which a plurality of pixel lines are provided in a display panel and a plurality of pixels including a driving device and a light emitting device are arranged in each pixel line,
Driving the signal lines of the display panel to drive the pixel lines in units of display blocks; And
And driving the signal lines of the display panel to compensate for the electron mobility of the driving device by simultaneously writing pixel data after compensating the threshold voltage of the driving device for pixel lines belonging to the same display block Emitting device. 12. The method of claim 11,
The pixel blocks belonging to the same display block,
And simultaneously initializing the source potential of the driving element to be lower than the operating point voltage of the light emitting element before simultaneously compensating the threshold voltage of the driving element,
Wherein the electron mobility of the driving element is sequentially compensated in units of pixel lines corresponding to pixel data written in a line sequential manner. 13. The method of claim 12,
The pixel blocks belonging to the same display block,
Sequentially compensating the electron mobility of the driving element in units of the pixel lines, and simultaneously connecting the pixels arranged in the pixel lines to the high-potential pixel driving voltage to simultaneously emit the light-emitting elements, A method of driving a display device. 12. The method of claim 11,
The pixel blocks belonging to the same display block,
Sequentially initializing the source potential of the driving device to a lower voltage than the operating point voltage of the light emitting device in units of a pixel line before simultaneously compensating the threshold voltage of the driving device; And
Sequentially writing the pixel data in a line sequential manner to sequentially compensate the electron mobility of the driving elements in units of the pixel lines and sequentially emitting the light emitting elements in units of the pixel lines, A method of driving a device. 15. The method of claim 14,
And the order of initializing the source potential of the driving element is the same as the writing order of the pixel data. 12. The method of claim 11,
The pixel blocks belonging to the same display block,
Simultaneously initializing the source potential of the driving element to be lower than the operating point voltage of the light emitting element before simultaneously compensating the threshold voltage of the driving element; And
Sequentially writing the pixel data in a line non-sequential manner to non-sequentially compensate the electron mobility of the driving elements in units of pixel lines, and to non-sequentially emit the light emitting elements in units of the pixel lines, A method of driving a light emitting display device. 17. The method of claim 16,
Wherein the display panel includes a first display block and a second display block which are adjacent to each other, and when the second display block is driven following the first display block,
Wherein at least one or more pixel block lines are arranged between a pixel block line that is the latest to emit light in the first display block and a pixel block line that emits the fastest light in the second display block. 18. The method according to any one of claims 11 to 17,
And driving the signal lines of the display panel to temporally fix the position of each display block on the display panel. 13. The method of claim 12,
And driving the signal lines of the display panel to temporally change positions of the respective display blocks on the display panel. 20. The method of claim 19,
When the number of pixel lines belonging to the same display block is J (J is a positive integer of 2 or more)
Wherein the step of temporally changing the position of each display block comprises shifting the position of each display block by a predetermined number of pixel lines K (K is a positive integer less than J) every predetermined time.

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