KR20080082118A - Organic light emitting diode display and driving method thereof - Google Patents

Abstract

An OLED display device and a driving method thereof are provided to enhance display quality and reliability by including a threshold voltage of a driving transistor in a voltage between gate and source terminals of the driving transistor in real time. Plural data lines supply data voltages. Plural signal line groups include a first gate line for supplying a first scan pulse, a second gate line for generating a second scan pulse having an opposite phase on the first scan pulse, and an emission line for supplying an emission pulse. A high voltage source(VDD) supplies a high driving voltage. A base voltage source supplies a base voltage. An OLED(Organic Light Emitting Diode) is illuminated by a current between the high voltage source and the base voltage. A driving element(DR) controls a current flowing in the OLED according to a gate-source voltage. A storage capacitor(Coff) is implemented between first and second nodes. A switch circuit adjusts the gate-source voltage of the driving element using a voltage which the data voltages are added into a compensation voltage caused by adding a threshold voltage of the driving element and a both end voltage of the OLED during an illumination period of the OLED.

Description

Organic Light Emitting Diode Display And Driving Method Thereof}

1 is a diagram illustrating a light emission principle of a general organic light emitting diode display.

Fig. 2 is a circuit diagram equivalently showing one pixel in a conventional active matrix organic light emitting diode display.

3 is a diagram showing the shift of the threshold voltage and the transfer characteristic curve of a TFT according to a voltage application time when a voltage of +30 V is applied to a gate electrode of a sample A-Si: H TFT.

4 is a graph showing a change amount of current flowing through an organic light emitting diode according to a change in a threshold voltage of a conventional driving TFT.

5 is a block diagram illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention.

FIG. 6 is a timing diagram of a driving signal supplied to the pixels of FIG. 5. FIG.

7 is an equivalent circuit diagram of a pixel provided in an organic light emitting diode display according to an exemplary embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a pixel 122 for the precharge period A of FIG. 6.

FIG. 9 is an equivalent circuit diagram of a pixel 122 for the threshold voltage compensation period B of FIG. 6.

FIG. 10 is an equivalent circuit diagram of a pixel 122 for the light emission period C of FIG. 6.

FIG. 11 illustrates a voltage Vg applied to the first node n1 and a voltage Voff stored in the offset capacitor in the precharge period A, the threshold voltage compensation period B, and the emission period C of FIG. 6. ), And a simulation result showing the transient states of the gate-source voltage Vgs and the driving current Ioled of the driving TFT DR.

FIG. 12 is a graph for explaining a change in current Ioled flowing through the organic light emitting diode OLED due to a change in the threshold voltage Vth of the driving TFT DR.

<Description of Symbols for Main Parts of Drawings>

116: display panel 118: gate driving circuit

120: data driving circuit 122: pixels

124: timing controller 130: organic light emitting diode driving circuit

S1: first scan pulse S2: second scan pulse

Ep: Emission pulse SW1, SW2, SW3: Switch TFT

EM: Emission TFT DR: Driving TFT

Coff: Offset Capacitor -Vdata: Data Voltage

The present invention relates to an organic light emitting diode display, and more particularly, to an organic light emitting diode display and a driving method thereof capable of improving display quality.

Recently, various flat panel displays (FPDs) that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such flat panel displays include liquid crystal displays (hereinafter referred to as "LCDs"), field emission displays (FEDs), plasma display panels (hereinafter referred to as "PDPs") and electric fields. Light emitting devices; and the like.

PDP is attracting attention as a display device that is light and small and is most advantageous for large screen because of its simple structure and manufacturing process. However, PDP has low light emission efficiency, low luminance and high power consumption. TFT LCDs with thin film transistors (hereinafter referred to as "TFTs") as switching devices are the most widely used flat panel display devices, but they have a narrow viewing angle and low response speed because they are non-light emitting devices. In contrast, electroluminescent devices are classified into inorganic light emitting diode display devices and organic light emitting diode display devices according to the material of the light emitting layer, and are self-light emitting devices that emit light by themselves, and have fast response speed, high luminous efficiency, luminance, and viewing angle.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. 1. The organic light emitting diode includes an organic compound layer (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL).

When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons, and as a result, the emission layer EML becomes Causes visible light to emanate.

The organic light emitting diode display device arranges the pixels having the organic light emitting diodes in a matrix form as shown in FIG.

Such an organic light emitting diode display is divided into a passive matrix type or an active matrix type display device using a TFT as a switching element.

The active matrix method selectively turns on the active TFT, selects a pixel, and maintains light emission of the pixel at a voltage maintained in a storage capacitor.

2 is an equivalent circuit diagram of one pixel in an active matrix organic light emitting diode display.

Referring to FIG. 2, a pixel of an organic light emitting diode display of an active matrix type includes an organic light emitting diode OLED, a data line DL and a gate line GL, a switch TFT SW, and a driving TFT DR that cross each other. ), And a storage capacitor Cst. The switch TFT (SW) and the driving TFT (DR) are implemented with an N-type MOS-FET.

The switch TFT SW is turned on in response to a scan pulse from the gate line GL to conduct a current path between its source electrode and drain electrode. During the on-time period of the switch TFT SW, the data voltage from the data line DL passes through the gate electrode and the storage capacitor Cst f of the driving TFT DR via the source electrode and the drain electrode of the switch TFT SW. Is applied.

The driving TFT DR controls the current flowing through the organic light emitting diode OLED according to the gate voltage Vg supplied to its gate electrode, that is, the data voltage.

The storage capacitor Cst stores the difference voltage between the data voltage and the high potential power voltage VDD to maintain a constant voltage applied to the gate electrode of the driving TFT DR for one frame period.

The organic light emitting diode OLED is implemented in the structure shown in FIG. 1. This organic light emitting diode OLED is connected between the source electrode of the driving TFT DR and a low potential power supply voltage source.

The brightness of the pixel as shown in FIG. 2 is proportional to the current flowing in the organic light emitting diode OLED, and the current is controlled by the gate voltage of the driving TFT DR.

The current Ioled of the organic light emitting diode OLED controlled by the driving TFT DR is expressed by Equation 1 below.

Here, 'Vgs' is a difference voltage between the gate voltage Vg and the source voltage Vs of the driving TFT DR, 'Vdata' is a data voltage, 'Voled' is a voltage across both ends of the organic light emitting diode OLED, Vth 'denotes a threshold voltage of the driving TFT DR, and' k 'denotes a constant value determined by mobility and parasitic capacitance of the driving TFT DR, respectively.

As shown in Equation 1, the current Ioled of the organic light emitting diode OLED is greatly influenced by the threshold voltage Vth of the driving TFT DR.

In general, when a gate voltage having the same polarity is applied to the gate electrode of the driving TFT DR for a long time, the gate-bias stress increases, thereby increasing the threshold voltage Vth of the driving TFT DR. As a result, the operating characteristics of the driving TFT DR change. The change in operating characteristics of the driving TFT DR can also be seen in the experimental results of FIG. 3.

FIG. 3 shows a positive gate-bias stress applied to a hydrogenated amorphous silicon TFT (A-Si: H TFT) for a sample having a channel width / channel length (W / L) of 120 μm / 6 μm. It is an experimental result showing that the characteristic change of the A-Si: H TFT for a sample is brought about. In Fig. 3, the horizontal axis represents the gate voltage [V] of the sample A-Si: H TFT, and the vertical axis represents the current [A] between the source electrode and the drain electrode of the sample A-Si: H TFT. The index in the box represents the gate voltage application time [sec] for each graph color.

3 shows the shift of the threshold voltage and the transfer characteristic curve of the TFT according to the voltage application time when a voltage of +30 V is applied to the gate electrode of the sample A-Si: H TFT. As can be seen from FIG. 3, as the time for applying the positive voltage to the gate electrode of the A-Si: H TFT increases, the transfer characteristic curve of the TFT shifts 31 to the right, and the threshold of the A-Si: H TFT Voltage rises. (Threshold voltage rises from Vth ₁ to Vth ₄ )

When the threshold voltage of the driving TFT DR rises as described above, the operation of the driving TFT DR becomes unstable, so that the current Ioled flowing to the organic light emitting diode OLED is reduced even when the same data voltage is applied.

As a result, in the conventional bottom anode type organic light emitting diode display device, even if the same data voltage is applied, luminance is varied due to the variation of the driving current Ioled depending on the threshold voltage characteristics of the driving TFT DR as shown in FIG. Non-uniformity appears, and thus there is a problem that the display quality is degraded.

Accordingly, it is an object of the present invention to provide an organic light emitting diode display device and a method of driving the same, which improve the display quality by preventing the current flowing through the organic light emitting diode from being affected by the variation of the threshold voltage of the driving TFT.

In order to achieve the above object, the organic light emitting diode display according to the embodiment of the present invention comprises a plurality of data lines supplied with a data voltage; A plurality of gate lines may include a first gate line to which a first scan pulse is supplied, a second gate line to which a second scan pulse is generated in a reverse phase with respect to the first scan pulse, and an emission line to which an emission pulse is supplied. Signal line group; A high potential drive voltage source for generating a high potential drive voltage; A base voltage source for generating a base voltage; An organic light emitting diode emitting light by a current flowing between the high potential driving voltage source and the base voltage source; A driving element controlling a current flowing through the organic light emitting diode according to a gate electrode connected to a first node and a gate-source voltage Vgs applied between the source electrode; A storage capacitor formed between the first node and the second node; And adjusting the gate-source voltage of the driving device to a voltage obtained by adding the data voltage to a compensation voltage generated by the sum of the threshold voltage of the driving device and the voltage between both ends of the organic light emitting diode during the light emitting period of the organic light emitting diode. A switch circuit is provided.

The switch circuit precharges the first node to the high potential driving voltage and charges the second node to the data voltage during the precharge period preceding the light emission period.

The switch circuit adjusts the potential of the first node to the compensation voltage and maintains the potential of the second node to the data voltage during the threshold voltage interpolation between the light emitting period and the precharge period.

The precharge period is defined as a period between a falling edge of the second scan pulse and a falling edge of the emission pulse that occur later than the rising edge of the first scan pulse.

The threshold voltage compensation period is defined as a period between the falling edge of the emission pulse and the rising edge of the second scan pulse synchronized with the falling edge of the first scan pulse.

The light emission period is defined as the high logic period of the emission pulse starting from the rising edge of the emission pulse which occurs later than the rising edge of the second scan pulse.

The switch circuit includes an emission element for switching a current path between the high potential driving voltage source and the driving element in response to the emission pulse; A first switch element for switching a current path between the emission element and the first node in response to the first scan pulse; A second switch element for switching a current path between the data line and the second node in response to the first scan pulse; And a third switch device for switching a current path between the source electrode of the driving device and the second node in response to the second scan pulse.

The driving device may include a gate electrode connected to the first node; A drain electrode commonly connected to the source electrode of the emission element and the source electrode of the first switch element; And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element.

The emission element may include a gate electrode connected to the emission line; A drain electrode connected to the high potential driving voltage source; And a source electrode commonly connected to the source electrode of the first switch element and the drain electrode of the driving element.

The first switch element may include a gate electrode connected to the first gate line; A drain electrode connected to the first node; And a source electrode commonly connected to the drain electrode of the driving element and the source electrode of the emission element.

The second switch element may include a gate electrode connected to the first gate line; A drain electrode connected to the data line; And a source electrode connected to the second node.

The third switch device may include a gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And a source electrode connected to the second node.

The current Ioled flowing through the organic light emitting diode during the light emitting period is expressed by the following equation.

Where Vgs is the gate-source voltage of the driving device, Vdata is the data voltage, Voled is the voltage across the organic light emitting diode, Vth is the threshold voltage of the driving device, and k is the mobility and parasitic capacitance of the driving device. Each means a constant value to be determined.

The driving device, the emission device and the first to third switch devices may be N-type electron metal oxide semiconductor field effect transistors.

The driving device includes a semiconductor layer formed of an amorphous silicon layer.

A plurality of data lines supplied with a data voltage, a first gate line supplied with a first scan pulse, and a second gate line and an emission pulse supplied with a second scan pulse generated in a reverse phase with respect to the first scan pulse are provided. A plurality of signal line groups each including an emission line supplied, a high potential driving voltage source for generating a high potential driving voltage, a base voltage source for generating a base voltage, and light emission by a current flowing between the high potential driving voltage source and the base voltage source An organic light emitting diode, a gate electrode connected to a first node, and a driving element controlling a current flowing through the organic light emitting diode according to a gate-source voltage Vgs applied between a source electrode, the first node, and a second node A storage capacitor formed between the nodes; And a method of driving an organic light emitting diode display device having a switch circuit including a plurality of switch elements, the compensation being generated by the sum of the threshold voltage of the driving element and the voltage between both ends of the organic light emitting diode during the light emitting period of the organic light emitting diode. The voltage between the gate and the source of the driving device is adjusted by the voltage plus the data voltage.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 12.

FIG. 5 is a block diagram illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIG. 6 is a view illustrating emission of first and second scan pulses S1 and S2 supplied to the pixels 122 of FIG. 5. A timing diagram of the pulse Ep.

5 and 6, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 116 in which m × n pixels 122 are formed, and data lines DL [1] through. The data driving circuit 120 for supplying the analog data voltage to DL [m] and the first scan pulse S1 are sequentially supplied to the first gate lines GL1 [1] to GL1 [n]. The second scan pulse S2 is sequentially supplied to the second gate lines GL2 [1] to GL2 [n], and the emission pulse Ep is applied to the emission lines EL [1] to EL [n]. ) And a timing controller 124 for controlling the driving timing of the data driving circuit 120 and the gate driving circuit 118.

The display panel 116 includes gate lines and emission lines GL [1] through GL [n], GL2 [1] through GL2 [n], and EL [1] through EL [n] and data lines Pixels 122 formed in pixel areas defined as intersections of DL [1] to DL [m]. The display panel 116 is provided with signal lines for supplying the high potential driving voltage VDD and signal lines for supplying the low potential driving voltage VSS to the pixels 122.

The data driving circuit 120 converts the digital video data RGB into an analog data voltage in response to the control signal DDC from the timing controller 124, and then converts the analog data voltage (hereinafter, referred to as data voltage) into data. To the lines DL [1] to DL [m]. The polarity of this data voltage is negative. The data voltage is supplied to the pixels 122 through the data lines DL [1] to DL [m].

The gate driving circuit 118 receives the first and second scan pulses S1 and S2 and the emission pulse Ep shown in FIG. 6 in response to the control signal GDC from the timing controller 124. And second gate lines GL1 [1] to GL1 [n] and GL2 [1] to GL2 [n] and emission lines EL [1] to EL [n]. The first and second scan pulses S1 and S2 are pixels 122 through the first and second gate lines GL1 [1] through GL1 [n] and GL2 [1] through GL2 [n], respectively. The emission pulse Ep is supplied to the pixels 122 through the emission lines EL [1] to EL [n].

The timing controller 124 supplies digital video data RGB to the data driving circuit 120 and operates timings of the gate driving circuit 118 and the data driving circuit 120 using vertical / horizontal synchronization signals and clock signals. It generates a control signal (DDC, GDC) to control.

In the timing diagram of FIG. 6, A indicates a precharge period, B indicates a threshold voltage compensation period, and C indicates a light emission period. T1 and T2 indicate the transient period.

The precharge period A refers to a period in which the gate voltage of the driving TFT formed in the pixel 122 is initialized to the high potential driving voltage VDD. The precharge period A is defined as the period between the falling edge of the second scan pulse S2 and the falling edge of the emission pulse Ep.

The threshold voltage compensation period B refers to a period in which the initialized high potential driving voltage VDD is discharged to maintain the gate voltage of the driving TFT as the compensation voltage including the threshold voltage. The threshold voltage compensation period B is defined as a period between the falling edge of the emission pulse Ep and the rising edge of the second scan pulse S2.

The light emitting period C refers to a period during which the organic light emitting diode emits light due to the voltage difference between the gate and the source of the driving TFT including the compensation voltage. The light emission period C is defined as the high logic period of the emission pulse Ep starting from the rising edge of the emission pulse Ep.

The first transient period T1 is a period occurring before the precharge period A, and is defined as a period between the rising edge of the first scan pulse S1 and the falling edge of the second scan pulse S2. The second transient period T2 is a period occurring between the threshold voltage compensation period B and the light emission period C. The rising edge of the second scan pulse S2 and the rising edge of the emission pulse Ep are the second transient period T2. Is defined as the period between. The first scan pulse S1 is polled in synchronization with the rising edge of the second scan pulse S2.

The operations of the pixels 122 in the precharge period A, the threshold voltage compensation period B, and the emission period C will be described in detail with reference to FIGS. 8 to 10.

Meanwhile, the display panel 116 is connected to a high potential driving voltage source VDD for supplying a high potential driving voltage to the pixels 122 and a low potential driving voltage source VSS for supplying a low potential driving voltage. The low potential drive voltage supplied from the low potential drive voltage source VSS is usually set to a base voltage.

Each of the pixels 122 includes an organic light emitting diode OLED, a driving TFT DR, three switch TFTs SW1 to SW3, an emission TFT EM, and an offset capacitor Coff as shown in FIG. 7.

7 is an equivalent circuit diagram illustrating a pixel 122 included in an organic light emitting diode display according to an exemplary embodiment of the present invention.

Referring to FIG. 7, a pixel 122 according to an exemplary embodiment of the present invention may include driving signals supplied from data lines DL [1] to DL [m] and gate lines GL [1] to GL [n]. An organic light emitting diode driving circuit 130 for driving the organic light emitting diode OLED in response to (-Vdata, S1, S2, and Ep), and an organic light emitting diode whose light emission amount is adjusted according to a driving current generated by the driving signal; (OLED).

The organic light emitting diode driving circuit 130 has a high potential across the driving TFT DR for controlling the driving current flowing in the organic light emitting diode OLED, and the gate electrode G of the first node n1: the driving TFT DR. After precharging to the driving voltage VDD, the first switch TFT SW1 for adjusting the compensation threshold voltage and the second switch TFT for supplying the negative data voltage -Vdata to the second node n2 ( Charged in the third switch TFT SW3 and the first and second nodes n1 and n2 for switching the current path between SW2, the second node n2 and the source electrode S of the driving TFT DR. An offset capacitor Coff for storing a voltage and an emission TFT EM for switching a current path between the high potential driving voltage source VDD and the drain electrode D of the driving TFT DR are provided. Here, the TFTs are implemented with an N-type electron metal oxide semiconductor field effect transistor (MOSFET, MetAl-Oxide SemiConduCtor Field EffeCt TrAnsistor). In particular, the semiconductor layer of the driving TFT DR is formed of an amorphous silicon layer so that the amount of change in the threshold voltage between the driving TFTs DR due to the same gate bias stress is almost the same.

The gate electrode G of the driving TFT DR is connected to the first node n1, and the drain electrode D of the driving TFT DR is the source electrode S and the first switch of the emission TFT EM. Commonly connected to the source electrode S of the TFT SW1, the source electrode S of the driving TFT DR is an anode electrode of the organic light emitting diode OLED and a drain electrode D of the third switch TFT SW3. Common connection to The driving TFT DR has an amount of current flowing in the organic light emitting diode OLED according to the difference voltage Vgs between the gate voltage applied to its gate electrode G and the source voltage applied to its source electrode S. To control.

The gate electrode G of the first switch TFT SW1 is connected to the first gate line GL1, and the drain electrode D of the first switch TFT SW1 is connected to the first node n1. The source electrode S of the first switch TFT SW1 is commonly connected to the source electrode S of the emission TFT EM and the drain electrode D of the driving TFT DR. The first switch TFT SW1 is turned on in response to the first scan pulse S1 from the first gate line GL1, thereby precharging the first node n1 to the high potential driving voltage VDD. After that, the potential of the first node n1 is adjusted to the compensation threshold voltage Vth + Voled. "Vth" means the threshold voltage of the driving TFT DR, and "Voled" means the voltage across the organic light emitting diode OLED. The compensation threshold voltage Vth + Voled is stored on the positive side of the storage capacitor Cst f through the first node n1.

The gate electrode G of the second switch TFT SW2 is commonly connected to the first gate line GL1 together with the gate electrode G of the first switch TFT SW1 and drains of the second switch TFT SW2. The electrode D is connected to the data line DL, and the source electrode S of the second switch TFT SW2 is connected to the second node n2. The second switch TFT SW2 is turned on in response to the first scan pulse S1 from the first gate line GL1, so that the negative data voltage -Vdata from the data line DL is reduced. To be supplied to the second node n2. The negative data voltage -Vdata is stored on the negative side of the storage capacitor Cst f through the second node n2.

The gate electrode G of the third switch TFT SW3 is connected to the second gate line GL2, and the drain electrode D of the third switch TFT SW3 is the source electrode S of the driving TFT DR. And a common electrode of the organic light emitting diode OLED, and a source electrode S of the third switch TFT SW3 is connected to the second node n2. The third switch TFT SW3 is turned on in response to the second scan pulse S2 from the second gate line GL2, so that the source voltage of the driving TFT DR and the voltage of the second node n2 are turned on. The equipotential is made with this negative data voltage (-Vdata).

The positive side of the offset capacitor Coff is connected to the first node n1, and the negative side of the offset capacitor Coff is connected to the second node n2. The offset capacitor Coff maintains the potential of the first node n1 at the high potential driving voltage VDD during the precharge period (A in FIG. 6), and then the threshold voltage compensation period (B in FIG. 6) and the light emission period. It remains at the compensation threshold voltage (Vth + Voled) during (Fig. 6C). In addition, the offset capacitor Coff maintains the potential of the second node n2 at a negative data voltage (−Vdata).

The gate electrode G of the emission TFT EM is connected to the emission line EL, the drain electrode D of the emission TFT EM is connected to the high potential driving voltage source VDD, and the emission TFT The source electrode S of the EM is commonly connected to the source electrode S of the first switch TFT SW1 and the drain electrode D of the driving TFT DR. The emission TFT EM switches the current path between the high potential driving voltage source VDD and the drain electrode D of the driving TFT DR.

The anode of the organic light emitting diode OLED is commonly connected to the source electrode S of the driving TFT DR and the drain electrode D of the third switch TFT SW3, and the cathode is connected to the low potential driving voltage source VSS. do. The organic light emitting diode OLED has the structure as shown in FIG. 1, and the amount of light emitted is controlled depending on the change in the data voltage -Vdata regardless of the change in the threshold voltage Vth of the driving TFT DR. Here, the anode electrode of the organic light emitting diode OLED is formed on the same substrate as the driving TFT DR. Accordingly, the pixels 122 emit light according to a bottom emission method.

The operation of the pixels 122 will be described below with reference to FIGS. 8 to 10.

FIG. 8 is an equivalent circuit diagram of the pixel 122 for the precharge period A of FIG. 6.

Referring to FIG. 8, during the precharge period A, the first scan pulse S1 is generated at a high logic voltage to turn on the first switch TFT and the second switch TFTs SW1 and SW2, and the second scan pulse. S2 is generated with a low logic voltage to turn off the third switch TFT SW3, and the emission pulse Ep is generated with a high logic voltage to turn on the emission TFT EM.

Accordingly, the first node n1 connected to the gate electrode G of the driving TFT DR is precharged with the high potential driving voltage VDD, and the first node n1 is disposed with the offset capacitor Coff interposed therebetween. Negative data voltage (-Vdata) is applied to the second node (n2) opposite to ().

FIG. 9 is an equivalent circuit diagram of the pixel 122 for the threshold voltage compensation period B of FIG. 6.

Referring to FIG. 9, during the threshold voltage compensation period B, the first scan pulse S1 is maintained at a high logic voltage to maintain the turn-on state of the first switch TFT and the second switch TFTs SW1 and SW2. The second scan pulse S2 is maintained at a low logic voltage to maintain the turn-off state of the third switch TFT SW3, and the emission pulse Ep is inverted to a low logic voltage to emit the emission TFT EM. Turn off.

Accordingly, the potential of the first node n1 connected to the gate electrode G of the driving TFT DR is discharged from the precharged high potential driving voltage VDD, so that the threshold voltage Vth of the driving TFT DR is discharged. And the compensation threshold voltage Vth + Voled, which is the sum of the voltages across the organic light emitting diode OLED. This is because a current path is formed between the positive terminal of the offset capacitor Coff-the driving TFT (DR)-the organic light emitting diode (OLED)-the ground voltage source (VSS), which is equivalently operated as a diode. Since a negative data voltage (-Vdata) is continuously applied to the negative terminal of the offset capacitor Coff, a voltage as shown in Equation 2 below is stored at both ends of the offset capacitor Coff.

Here, Voff refers to the voltage across the offset capacitor (Coff).

FIG. 10 is an equivalent circuit diagram of the pixel 122 for the light emission period C of FIG. 6.

Referring to FIG. 10, during the light emission period C, the first scan pulse S1 is inverted to a low logic voltage to turn off the first switch TFT and the second switch TFTs SW1 and SW2, and the second scan. The pulse S2 is inverted by a high logic voltage to turn on the third switch TFT SW3, and the emission pulse Ep is inverted to a high logic voltage to turn on the emission TFT EM. .

Accordingly, the voltage difference Vgs between the gate voltage Vg applied to the gate electrode G of the driving TFT DR and the source voltage Vs applied to the source electrode S of the driving TFT DR is offset. It becomes equal to the voltage Voff of the capacitor Coff. Since the voltage Voff at both ends of the offset capacitor Coff is maintained at Equation 2 during the light emission period C, the driving current Ioled flowing to the organic light emitting diode OLED is expressed by Equation 3 below.

Referring to Equation 3, the driving current Ioled flowing in the organic light emitting diode OLED is not influenced at all by the change in the threshold voltage Vth of the driving TFT DR. Accordingly, the phenomenon in which the display quality is deteriorated due to the change in the threshold voltage Vth of the driving TFT DR is prevented.

FIG. 11 illustrates a voltage Vg applied to the first node n1 and a voltage Voff stored in the offset capacitor in the precharge period A, the threshold voltage compensation period B, and the emission period C of FIG. 6. ), A simulation result showing the transient states of the gate-source voltage Vgs and the driving current Ioled of the driving TFT DR.

Referring to FIG. 11, the gate voltage Vg of the driving TFT DR is precharged to the high potential driving voltage VDD during the precharge period A, and then the driving TFT DR during the threshold voltage compensation period B. FIG. The gate voltage Vg is adjusted to the compensation threshold voltage Vth + Voled. By using this, the gate-source voltage Vgs of the driving TFT DR is included in the light emitting period C so that the changed threshold voltage Vth of the driving TFT DR is included, thereby driving the driving current Ioled. It can be seen that the function is independent of the change in the threshold voltage (Vth).

FIG. 12 is a graph for explaining a change in the current Ioled flowing through the organic light emitting diode OLED due to the change in the threshold voltage Vth of the driving TFT DR. In FIG. 12, the horizontal axis represents a change in threshold voltage Vth, and the vertical axis represents a current Ioled flowing through the organic light emitting diode OLED.

Referring to FIG. 12, even if the threshold voltage Vth of the driving TFT DR is changed from 0 V to 2 V due to the gate bias stress, the amount of change ΔIoled of the current flowing through the organic light emitting diode OLED is 4% to Minimized to 15%. This represents a significantly smaller value compared to the amount of change (ΔIoled) of the current amounting to 59% to 91%. Accordingly, the organic light emitting diode display according to the embodiment of the present invention does not change the amount of current flowing through the organic light emitting diode OLED even if the threshold voltage Vth of the driving TFT DR is changed. Is improved.

On the other hand, the reason why the current (Ioled) flowing in the organic light emitting diode (OLED) in the present invention shows a difference of about 4% to 15% is the voltage of both ends of the organic light emitting diode (OLED) is included in the equation This is because the organic light emitting diode (OLED) is affected by the change of the high potential driving voltage (VDD) due to the saturation current and the line resistance of the OLED.

As described above, the organic light emitting diode display and the driving method thereof according to the present invention include the threshold voltage of the driving TFT in real time in the gate-source voltage of the driving TFT so that the current flowing through the organic light emitting diode is increased. The display quality can be improved and the reliability of the image quality can be improved by being not affected by the change of the threshold voltage of the driving TFT.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (22)

A plurality of data lines supplied with data voltages; A plurality of gate lines may include a first gate line to which a first scan pulse is supplied, a second gate line to which a second scan pulse is generated in a reverse phase with respect to the first scan pulse, and an emission line to which an emission pulse is supplied. Signal line group; A high potential drive voltage source for generating a high potential drive voltage; A base voltage source for generating a base voltage; An organic light emitting diode emitting light by a current flowing between the high potential driving voltage source and the base voltage source; A driving element controlling a current flowing through the organic light emitting diode according to a gate electrode connected to a first node and a gate-source voltage Vgs applied between the source electrode; A storage capacitor formed between the first node and the second node; And Adjusting the gate-source voltage of the driving device to a voltage obtained by adding the data voltage to a compensation voltage generated by the sum of the threshold voltage of the driving device and the voltage between both ends of the organic light emitting diode during the light emitting period of the organic light emitting diode. An organic light emitting diode display device comprising a switch circuit. The method of claim 1, The switch circuit, And precharging the first node to the high potential driving voltage and charging the second node to the data voltage during the precharge period preceding the light emitting period. The method of claim 2, The switch circuit, An organic light emitting diode display device wherein the potential of the first node is adjusted to the compensation voltage and the potential of the second node is maintained at the data voltage during the threshold voltage compensation period between the light emission period and the precharge period. . The method of claim 3, wherein The precharge period, And a period between a falling edge of the second scan pulse and a falling edge of the emission pulse generated later than the rising edge of the first scan pulse. The method of claim 3, wherein The threshold voltage compensation period, And a period between the falling edge of the emission pulse and the rising edge of the second scan pulse synchronized with the falling edge of the first scan pulse. The method of claim 3, wherein The light emission period is, And a high logic period of the emission pulse starting from the rising edge of the emission pulse which is generated later than the rising edge of the second scan pulse. The method of claim 1, The switch circuit, An emission element for switching a current path between the high potential driving voltage source and the driving element in response to the emission pulse; A first switch element for switching a current path between the emission element and the first node in response to the first scan pulse; A second switch element for switching a current path between the data line and the second node in response to the first scan pulse; And And a third switch device for switching a current path between the source electrode and the second node of the driving device in response to the second scan pulse. The method of claim 7, wherein The driving device, A gate electrode connected to the first node; A drain electrode commonly connected to the source electrode of the emission element and the source electrode of the first switch element; And And a source electrode commonly connected to the anode electrode of the organic light emitting diode and the drain electrode of the third switch element. The method of claim 7, wherein The emission element, A gate electrode connected to the emission line; A drain electrode connected to the high potential driving voltage source; And And a source electrode commonly connected to the source electrode of the first switch element and the drain electrode of the driving element. The method of claim 7, wherein The first switch device, A gate electrode connected to the first gate line; A drain electrode connected to the first node; And And a source electrode commonly connected to the drain electrode of the driving element and the source electrode of the emission element. The method of claim 7, wherein The second switch device, A gate electrode connected to the first gate line; A drain electrode connected to the data line; And And a source electrode connected to the second node. The method of claim 7, wherein The third switch device, A gate electrode connected to the second gate line; A drain electrode commonly connected to the source electrode of the driving device and the anode electrode of the organic light emitting diode; And And a source electrode connected to the second node. The method of claim 3, wherein An organic light emitting diode display device, wherein the current Ioled flowing through the organic light emitting diode during the light emitting period is as follows.

Where Vgs is the gate-source voltage of the driving device, Vdata is the data voltage, Voled is the voltage across the organic light emitting diode, Vth is the threshold voltage of the driving device, and k is the mobility and parasitic capacitance of the driving device. Each means a constant value to be determined. The method of claim 7, wherein And the driving element, the emission element, and the first to third switch elements are N-type electron metal oxide semiconductor field effect transistors. The method of claim 1, And the driving device includes a semiconductor layer formed of an amorphous silicon layer. A plurality of data lines supplied with data voltages, first gates supplied with first scan pulses, and second gate lines and emission lines provided with second scan pulses generated out of phase with respect to the first scan pulses; A plurality of signal line groups each including an emission line supplied with a pulse, a high potential driving voltage source for generating a high potential driving voltage, a base voltage source for generating a base voltage, and a current flowing between the high potential driving voltage source and the base voltage source An organic light emitting diode that is emitted by the light emitting diode, a gate electrode connected to the first node, a driving element controlling a current flowing through the organic light emitting diode according to the gate-source voltage Vgs applied between the source electrode, and the first node; A storage capacitor formed between the second nodes; A driving method of an organic light emitting diode display device having a switch circuit comprising a plurality of switch elements, Adjusting the gate-source voltage of the driving device to a voltage obtained by adding the data voltage to a compensation voltage generated by the sum of the threshold voltage of the driving device and the voltage between both ends of the organic light emitting diode during the light emitting period of the organic light emitting diode. A method of driving an organic light emitting diode display, characterized in that. The method of claim 16, And precharging the first node to the high potential driving voltage and charging the second node to the data voltage during the precharging period prior to the light emitting period. The method of claim 17, An organic light emitting diode display device wherein the potential of the first node is adjusted to the compensation voltage and the potential of the second node is maintained at the data voltage during the threshold voltage compensation period between the light emission period and the precharge period. Driving method. The method of claim 18, The precharge period, And a period between a falling edge of the second scan pulse and a falling edge of the emission pulse generated later than the rising edge of the first scan pulse. The method of claim 18, The threshold voltage compensation period, And a period between the falling edge of the emission pulse and the rising edge of the second scan pulse synchronized with the falling edge of the first scan pulse. The method of claim 18, The light emission period is, And a high logic period of the emission pulse starting from the rising edge of the emission pulse which is generated later than the rising edge of the second scan pulse. The method of claim 18, A method of driving an organic light emitting diode display device according to claim 1, wherein the current Ioled flowing through the organic light emitting diode during the light emitting period is as follows.

Where Vgs is the gate-source voltage of the driving device, Vdata is the data voltage, Voled is the voltage across the organic light emitting diode, Vth is the threshold voltage of the driving device, and k is the mobility and parasitic capacitance of the driving device. Each means a constant value to be determined.

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