KR102372289B1 - 메모리 액세스 시스템, 그 제어방법, 컴퓨터 판독가능한 기억매체, 및 화상 형성장치 - Google Patents

메모리 액세스 시스템, 그 제어방법, 컴퓨터 판독가능한 기억매체, 및 화상 형성장치 Download PDF

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KR102372289B1
KR102372289B1 KR1020180003626A KR20180003626A KR102372289B1 KR 102372289 B1 KR102372289 B1 KR 102372289B1 KR 1020180003626 A KR1020180003626 A KR 1020180003626A KR 20180003626 A KR20180003626 A KR 20180003626A KR 102372289 B1 KR102372289 B1 KR 102372289B1
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memory
internal bus
masters
access
master
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KR20180088279A (ko
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준이치 고다
야스시 신토
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캐논 가부시끼가이샤
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40—Picture signal circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Facsimiles In General (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
  • Storing Facsimile Image Data (AREA)
KR1020180003626A 2017-01-26 2018-01-11 메모리 액세스 시스템, 그 제어방법, 컴퓨터 판독가능한 기억매체, 및 화상 형성장치 Expired - Fee Related KR102372289B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2017-012541 2017-01-26
JP2017012541A JP6886301B2 (ja) 2017-01-26 2017-01-26 メモリアクセスシステム、その制御方法、プログラム、及び画像形成装置

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KR20180088279A KR20180088279A (ko) 2018-08-03
KR102372289B1 true KR102372289B1 (ko) 2022-03-08

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US (1) US11163711B2 (enExample)
EP (1) EP3355199B1 (enExample)
JP (1) JP6886301B2 (enExample)
KR (1) KR102372289B1 (enExample)
CN (1) CN108363669B (enExample)

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JP6681244B2 (ja) * 2016-03-30 2020-04-15 キヤノン株式会社 画像処理装置、その制御方法、及びプログラム
KR102316154B1 (ko) * 2019-12-30 2021-10-22 서울대학교산학협력단 지역성을 보존하는 메모리 아비터
JP2021152694A (ja) * 2020-03-24 2021-09-30 パナソニックＩｐマネジメント株式会社 監視装置、監視方法及びプログラム
CN113515473B (zh) * 2020-04-09 2024-06-14 珠海全志科技股份有限公司 一种QoS控制方法、总线系统、计算装置和存储介质
JP7494546B2 (ja) * 2020-04-17 2024-06-04 コニカミノルタ株式会社 画像形成装置、画像形成装置の制御方法、および、画像形成装置の制御プログラム
CN111541622A (zh) * 2020-04-17 2020-08-14 西安万像电子科技有限公司 数据传输方法及装置
JP7625802B2 (ja) 2020-07-10 2025-02-04 富士フイルムビジネスイノベーション株式会社 メモリ・アクセス・システムおよび情報処理装置
CN114167972A (zh) * 2020-08-21 2022-03-11 深圳市中兴微电子技术有限公司 存储器的访问方法、模块、控制器、系统和介质
US11899589B2 (en) * 2021-06-22 2024-02-13 Samsung Electronics Co., Ltd. Systems, methods, and devices for bias mode management in memory systems
WO2025059841A1 (en) * 2023-09-19 2025-03-27 Qualcomm Incorporated Integrated circuits (ics) that limit the memory interface utilization of high-priority processing circuits and related methods

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JP2018120490A (ja) 2018-08-02
US11163711B2 (en) 2021-11-02
CN108363669B (zh) 2021-10-22
EP3355199B1 (en) 2023-05-24
JP6886301B2 (ja) 2021-06-16
US20180210849A1 (en) 2018-07-26
KR20180088279A (ko) 2018-08-03
EP3355199A1 (en) 2018-08-01
CN108363669A (zh) 2018-08-03

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