KR102199607B1 - 비휘발성 메모리에 멀티비트 데이터를 저장하기 위한 시스템 및 방법 - Google Patents

비휘발성 메모리에 멀티비트 데이터를 저장하기 위한 시스템 및 방법 Download PDF

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KR102199607B1
KR102199607B1 KR1020207010818A KR20207010818A KR102199607B1 KR 102199607 B1 KR102199607 B1 KR 102199607B1 KR 1020207010818 A KR1020207010818 A KR 1020207010818A KR 20207010818 A KR20207010818 A KR 20207010818A KR 102199607 B1 KR102199607 B1 KR 102199607B1
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read current
voltage
offset value
memory cells
memory cell
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KR20200043501A (ko
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비핀 티와리
엔한 도
히에우 반 트란
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실리콘 스토리지 테크놀로지 인크
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020207010818A 2017-11-03 2018-10-02 비휘발성 메모리에 멀티비트 데이터를 저장하기 위한 시스템 및 방법 Active KR102199607B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762581489P 2017-11-03 2017-11-03
US62/581,489 2017-11-03
US16/148,304 US10515694B2 (en) 2017-11-03 2018-10-01 System and method for storing multibit data in non-volatile memory
US16/148,304 2018-10-01
PCT/US2018/053930 WO2019089168A1 (en) 2017-11-03 2018-10-02 System and method for storing multibit data in non-volatile memory

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KR20200043501A KR20200043501A (ko) 2020-04-27
KR102199607B1 true KR102199607B1 (ko) 2021-01-08

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US (1) US10515694B2 (enExample)
EP (1) EP3704700B1 (enExample)
JP (1) JP6970826B2 (enExample)
KR (1) KR102199607B1 (enExample)
CN (1) CN111344791B (enExample)
TW (1) TWI682393B (enExample)
WO (1) WO2019089168A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671698B1 (ko) * 2004-08-05 2007-01-18 매그나칩 반도체 유한회사 엘디아이 내 디지털 아날로그 변환기의 테스트 장치
KR20230080156A (ko) 2021-11-29 2023-06-07 충남대학교산학협력단 멀티 레벨 구동이 가능한 메모리 소자

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10991433B2 (en) * 2019-09-03 2021-04-27 Silicon Storage Technology, Inc. Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program
US11682459B2 (en) * 2020-05-13 2023-06-20 Silicon Storage Technology, Inc. Analog neural memory array in artificial neural network comprising logical cells and improved programming mechanism
US12080355B2 (en) 2021-06-02 2024-09-03 Silicon Storage Technology, Inc. Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise
US11769558B2 (en) * 2021-06-08 2023-09-26 Silicon Storage Technology, Inc. Method of reducing random telegraph noise in non-volatile memory by grouping and screening memory cells

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US20150085571A1 (en) 2013-09-24 2015-03-26 Sandisk Technologies Inc. Updating read voltages
US20160064058A1 (en) 2014-08-29 2016-03-03 Everspin Technologies, Inc. Configuration and testing for magnetoresistive memory
US20160148701A1 (en) 2014-11-20 2016-05-26 HGST Netherlands B.V. Read level grouping algorithms for increased flash performance

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JP2812202B2 (ja) * 1994-06-27 1998-10-22 ヤマハ株式会社 半導体記憶装置
KR100324594B1 (ko) 1999-06-28 2002-02-16 박종섭 강유전체 메모리 장치
US7082056B2 (en) 2004-03-12 2006-07-25 Super Talent Electronics, Inc. Flash memory device and architecture with multi level cells
US7324374B2 (en) 2003-06-20 2008-01-29 Spansion Llc Memory with a core-based virtual ground and dynamic reference sensing scheme
US7315056B2 (en) 2004-06-07 2008-01-01 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with program/erase and select gates
US7554856B2 (en) * 2006-10-06 2009-06-30 Qimonda Flash Gmbh & Co. Kg Memory cell
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8238149B2 (en) 2009-06-25 2012-08-07 Macronix International Co., Ltd. Methods and apparatus for reducing defect bits in phase change memory
JP2012209004A (ja) 2011-03-30 2012-10-25 Toshiba Corp 半導体記憶装置
US9099202B2 (en) * 2012-11-06 2015-08-04 Sandisk Technologies Inc. 3D stacked non-volatile storage programming to conductive state
KR102043723B1 (ko) 2013-02-28 2019-12-02 에스케이하이닉스 주식회사 반도체 장치 및 이를 포함하는 프로세서와 시스템
KR101716998B1 (ko) 2013-03-14 2017-03-15 실리콘 스토리지 테크놀로지 인크 비휘발성 메모리 프로그램 알고리즘 디바이스 및 방법
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Publication number Priority date Publication date Assignee Title
US20150085571A1 (en) 2013-09-24 2015-03-26 Sandisk Technologies Inc. Updating read voltages
US20160064058A1 (en) 2014-08-29 2016-03-03 Everspin Technologies, Inc. Configuration and testing for magnetoresistive memory
US20160148701A1 (en) 2014-11-20 2016-05-26 HGST Netherlands B.V. Read level grouping algorithms for increased flash performance

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100671698B1 (ko) * 2004-08-05 2007-01-18 매그나칩 반도체 유한회사 엘디아이 내 디지털 아날로그 변환기의 테스트 장치
KR20230080156A (ko) 2021-11-29 2023-06-07 충남대학교산학협력단 멀티 레벨 구동이 가능한 메모리 소자

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TW201931370A (zh) 2019-08-01
JP6970826B2 (ja) 2021-11-24
US20190139602A1 (en) 2019-05-09
WO2019089168A1 (en) 2019-05-09
CN111344791B (zh) 2021-06-25
TWI682393B (zh) 2020-01-11
EP3704700B1 (en) 2022-07-20
JP2021501956A (ja) 2021-01-21
CN111344791A (zh) 2020-06-26
EP3704700A4 (en) 2021-07-21
US10515694B2 (en) 2019-12-24
KR20200043501A (ko) 2020-04-27
EP3704700A1 (en) 2020-09-09

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